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Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
2023-01-09 11:30:08 -05:00
parent 62e2ad1cea fe33066d24
commit cebdfc22da
2483 changed files with 62769 additions and 32768 deletions
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24
arch/arm/Kconfig
View File

@@ -553,6 +553,9 @@ config ARM64_SUPPORT_AARCH32
help
This ARM64 system supports AArch32 execution state.
config IPROC
bool
config S5P
def_bool y if ARCH_EXYNOS || ARCH_S5PC1XX
@@ -586,7 +589,6 @@ config ARCH_KIRKWOOD
config ARCH_MVEBU
bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
select DM
select DM_ETH
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
@@ -659,6 +661,7 @@ config TARGET_BCMCYGNUS
bool "Support bcmcygnus"
select CPU_V7A
select GPIO_EXTRA_HEADER
select IPROC
imply BCM_SF2_ETH
imply BCM_SF2_ETH_GMAC
imply CMD_HASH
@@ -690,7 +693,6 @@ config ARCH_EXYNOS
select DM
select DM_GPIO
select DM_I2C
select DM_ETH
select DM_KEYBOARD
select DM_SERIAL
select DM_SPI
@@ -721,7 +723,6 @@ config ARCH_HIGHBANK
select CLK
select CLK_CCF
select AHCI
select DM_ETH
select PHYS_64BIT
select TIMER
select SP804_TIMER
@@ -918,6 +919,7 @@ config ARCH_MX7
select CPU_V7A
select GPIO_EXTRA_HEADER
select MACH_IMX
select MXC_GPT_HCLK
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
@@ -931,6 +933,7 @@ config ARCH_MX6
select CPU_V7A
select GPIO_EXTRA_HEADER
select MACH_IMX
select MXC_GPT_HCLK
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
@@ -995,7 +998,6 @@ config ARCH_APPLE
config ARCH_OWL
bool "Actions Semi OWL SoCs"
select DM
select DM_ETH
select DM_SERIAL
select GPIO_EXTRA_HEADER
select OWL_SERIAL
@@ -1095,7 +1097,6 @@ config ARCH_SUNXI
select CMD_USB if DISTRO_DEFAULTS && USB_HOST
select CLK
select DM
select DM_ETH
select DM_GPIO
select DM_I2C if I2C
select DM_SPI if SPI
@@ -1174,7 +1175,6 @@ config ARCH_VERSAL
select ARM64
select CLK
select DM
select DM_ETH if NET
select DM_MMC if MMC
select DM_SERIAL
select GICV3
@@ -1188,7 +1188,6 @@ config ARCH_VERSAL_NET
select ARM64
select CLK
select DM
select DM_ETH if NET
select DM_MMC if MMC
select DM_SERIAL
select OF_CONTROL
@@ -1199,6 +1198,7 @@ config ARCH_VF610
bool "Freescale Vybrid"
select CPU_V7A
select GPIO_EXTRA_HEADER
select IOMUX_SHARE_CONF_REG
select MACH_IMX
select SYS_FSL_ERRATUM_ESDHC111
imply CMD_MTDPARTS
@@ -1212,7 +1212,6 @@ config ARCH_ZYNQ
select CPU_V7A
select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
select DM
select DM_ETH if NET
select DM_MMC if MMC
select DM_SERIAL
select DM_SPI
@@ -1242,7 +1241,6 @@ config ARCH_ZYNQMP_R5
select CLK
select CPU_V7R
select DM
select DM_ETH if NET
select DM_MMC if MMC
select DM_SERIAL
select OF_CONTROL
@@ -1255,7 +1253,6 @@ config ARCH_ZYNQMP
select CLK
select DM
select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
select DM_ETH if NET
imply DM_MAILBOX
select DM_MMC if MMC
select DM_SERIAL
@@ -1606,6 +1603,7 @@ config TARGET_LS1021AQDS
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select LS1_DEEP_SLEEP
select PEN_ADDR_BIG_ENDIAN
select SUPPORT_SPL
select SYS_FSL_DDR
select FSL_DDR_INTERACTIVE
@@ -1624,6 +1622,7 @@ config TARGET_LS1021ATWR
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select LS1_DEEP_SLEEP
select PEN_ADDR_BIG_ENDIAN
select SUPPORT_SPL
select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
select GPIO_EXTRA_HEADER
@@ -1688,6 +1687,7 @@ config TARGET_LS1021AIOT
select CPU_V7A
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select PEN_ADDR_BIG_ENDIAN
select SUPPORT_SPL
select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
select GPIO_EXTRA_HEADER
@@ -1802,7 +1802,6 @@ config TARGET_SL28
select DM_I2C
select DM_MMC
select DM_SPI_FLASH
select DM_ETH
select DM_MDIO
select PCI
select DM_RNG
@@ -1839,7 +1838,6 @@ config ARCH_UNIPHIER
bool "Socionext UniPhier SoCs"
select BOARD_LATE_INIT
select DM
select DM_ETH
select DM_GPIO
select DM_I2C
select DM_MMC
@@ -2025,7 +2023,6 @@ config TARGET_POMELO
select SCSI
select DM_SCSI
select DM_SERIAL
select DM_ETH if NET
imply CMD_PCI
help
Support for pomelo platform.
@@ -2295,6 +2292,7 @@ source "board/hisilicon/poplar/Kconfig"
source "board/isee/igep003x/Kconfig"
source "board/kontron/sl28/Kconfig"
source "board/myir/mys_6ulx/Kconfig"
source "board/samsung/common/Kconfig"
source "board/siemens/common/Kconfig"
source "board/seeed/npi_imx6ull/Kconfig"
source "board/socionext/developerbox/Kconfig"

8
arch/arm/config.mk
View File

@@ -3,14 +3,6 @@
# (C) Copyright 2000-2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
ifndef CONFIG_STANDALONE_LOAD_ADDR
ifneq ($(CONFIG_ARCH_OMAP2PLUS),)
CONFIG_STANDALONE_LOAD_ADDR = 0x80300000
else
CONFIG_STANDALONE_LOAD_ADDR = 0xc100000
endif
endif
CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections -fdata-sections \
-fstack-protector-strong
CFLAGS_EFI := -fpic -fshort-wchar

2
arch/arm/cpu/arm1176/start.S
View File

@@ -18,7 +18,7 @@
#include <linux/linkage.h>
#ifndef CONFIG_SYS_PHY_UBOOT_BASE
#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
#define CONFIG_SYS_PHY_UBOOT_BASE CFG_SYS_UBOOT_BASE
#endif
/*

8
arch/arm/cpu/arm920t/imx/Makefile
View File

@@ -1,8 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y += generic.o
obj-y += speed.o
obj-y += timer.o

76
arch/arm/cpu/arm920t/imx/generic.c
View File

@@ -1,76 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* arch/arm/mach-imx/generic.c
*
* author: Sascha Hauer
* Created: april 20th, 2004
* Copyright: Synertronixx GmbH
*
* Common code for i.MX machines
*/
#include <common.h>
#ifdef CONFIG_IMX
#include <asm/arch/imx-regs.h>
void imx_gpio_mode(int gpio_mode)
{
unsigned int pin = gpio_mode & GPIO_PIN_MASK;
unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> 5;
unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> 10;
unsigned int tmp;
/* Pullup enable */
if(gpio_mode & GPIO_PUEN)
PUEN(port) |= (1<<pin);
else
PUEN(port) &= ~(1<<pin);
/* Data direction */
if(gpio_mode & GPIO_OUT)
DDIR(port) |= 1<<pin;
else
DDIR(port) &= ~(1<<pin);
/* Primary / alternate function */
if(gpio_mode & GPIO_AF)
GPR(port) |= (1<<pin);
else
GPR(port) &= ~(1<<pin);
/* use as gpio? */
if( ocr == 3 )
GIUS(port) |= (1<<pin);
else
GIUS(port) &= ~(1<<pin);
/* Output / input configuration */
/* FIXME: I'm not very sure about OCR and ICONF, someone
* should have a look over it
*/
if(pin<16) {
tmp = OCR1(port);
tmp &= ~( 3<<(pin*2));
tmp |= (ocr << (pin*2));
OCR1(port) = tmp;
if( gpio_mode & GPIO_AOUT )
ICONFA1(port) &= ~( 3<<(pin*2));
if( gpio_mode & GPIO_BOUT )
ICONFB1(port) &= ~( 3<<(pin*2));
} else {
tmp = OCR2(port);
tmp &= ~( 3<<((pin-16)*2));
tmp |= (ocr << ((pin-16)*2));
OCR2(port) = tmp;
if( gpio_mode & GPIO_AOUT )
ICONFA2(port) &= ~( 3<<((pin-16)*2));
if( gpio_mode & GPIO_BOUT )
ICONFB2(port) &= ~( 3<<((pin-16)*2));
}
}
#endif /* CONFIG_IMX */

86
arch/arm/cpu/arm920t/imx/speed.c
View File

@@ -1,86 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
*
* (c) 2004 Sascha Hauer <sascha@saschahauer.de>
*/
#include <common.h>
#if defined (CONFIG_IMX)
#include <clock_legacy.h>
#include <asm/arch/imx-regs.h>
/* ------------------------------------------------------------------------- */
/* NOTE: This describes the proper use of this file.
*
* get_board_sys_clk() should be defined as the input frequency of the PLL.
* SH FIXME: 16780000 in our case
* get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
* the specified bus in HZ.
*/
/* ------------------------------------------------------------------------- */
ulong get_systemPLLCLK(void)
{
/* FIXME: We assume System_SEL = 0 here */
u32 spctl0 = SPCTL0;
u32 mfi = (spctl0 >> 10) & 0xf;
u32 mfn = spctl0 & 0x3f;
u32 mfd = (spctl0 >> 16) & 0x3f;
u32 pd = (spctl0 >> 26) & 0xf;
mfi = mfi<=5 ? 5 : mfi;
return (2*(CONFIG_SYSPLL_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
}
ulong get_mcuPLLCLK(void)
{
/* FIXME: We assume System_SEL = 0 here */
u32 mpctl0 = MPCTL0;
u32 mfi = (mpctl0 >> 10) & 0xf;
u32 mfn = mpctl0 & 0x3f;
u32 mfd = (mpctl0 >> 16) & 0x3f;
u32 pd = (mpctl0 >> 26) & 0xf;
mfi = mfi<=5 ? 5 : mfi;
return (2*(get_board_sys_clk()>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
}
ulong get_FCLK(void)
{
return (( CSCR>>15)&1) ? get_mcuPLLCLK()>>1 : get_mcuPLLCLK();
}
/* return HCLK frequency */
ulong get_HCLK(void)
{
u32 bclkdiv = (( CSCR >> 10 ) & 0xf) + 1;
printf("bclkdiv: %d\n", bclkdiv);
return get_systemPLLCLK() / bclkdiv;
}
/* return BCLK frequency */
ulong get_BCLK(void)
{
return get_HCLK();
}
ulong get_PERCLK1(void)
{
return get_systemPLLCLK() / (((PCDR) & 0xf)+1);
}
ulong get_PERCLK2(void)
{
return get_systemPLLCLK() / (((PCDR>>4) & 0xf)+1);
}
ulong get_PERCLK3(void)
{
return get_systemPLLCLK() / (((PCDR>>16) & 0x7f)+1);
}
#endif /* defined (CONFIG_IMX) */

100
arch/arm/cpu/arm920t/imx/timer.c
View File

@@ -1,100 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*/
#include <common.h>
#include <cpu_func.h>
#include <time.h>
#if defined (CONFIG_IMX)
#include <asm/arch/imx-regs.h>
#include <linux/delay.h>
int timer_init (void)
{
int i;
/* setup GP Timer 1 */
TCTL1 = TCTL_SWR;
for ( i=0; i<100; i++) TCTL1 = 0; /* We have no udelay by now */
TPRER1 = get_PERCLK1() / 1000000; /* 1 MHz */
TCTL1 |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */
/* Reset the timer */
TCTL1 &= ~TCTL_TEN;
TCTL1 |= TCTL_TEN; /* Enable timer */
return (0);
}
/*
* timer without interrupts
*/
static ulong get_timer_masked (void)
{
return TCN1;
}
ulong get_timer (ulong base)
{
return get_timer_masked() - base;
}
void __udelay(unsigned long usec)
{
ulong endtime = get_timer_masked() + usec;
signed long diff;
do {
ulong now = get_timer_masked ();
diff = endtime - now;
} while (diff >= 0);
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
return get_timer(0);
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
return CONFIG_SYS_HZ;
}
/*
* Reset the cpu by setting up the watchdog timer and let him time out
*/
void reset_cpu(void)
{
/* Disable watchdog and set Time-Out field to 0 */
WCR = 0x00000000;
/* Write Service Sequence */
WSR = 0x00005555;
WSR = 0x0000AAAA;
/* Enable watchdog */
WCR = 0x00000001;
while (1);
/*NOTREACHED*/
}
#endif /* defined (CONFIG_IMX) */

1
arch/arm/cpu/arm926ejs/Makefile
View File

@@ -12,7 +12,6 @@ extra-y :=
endif
endif
obj-$(CONFIG_MX27) += mx27/
obj-$(if $(filter mxs,$(SOC)),y) += mxs/
obj-$(if $(filter spear,$(SOC)),y) += spear/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/

7
arch/arm/cpu/arm926ejs/mx27/Makefile
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@@ -1,7 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
obj-y += generic.o timer.o reset.o relocate.o

378
arch/arm/cpu/arm926ejs/mx27/generic.c
View File

@@ -1,378 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
* Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
*/
#include <common.h>
#include <div64.h>
#include <net.h>
#include <netdev.h>
#include <vsprintf.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/mach-imx/sys_proto.h>
#ifdef CONFIG_MMC_MXC
#include <asm/arch/mxcmmc.h>
#endif
/*
* get the system pll clock in Hz
*
* mfi + mfn / (mfd +1)
* f = 2 * f_ref * --------------------
* pd + 1
*/
static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
{
unsigned int mfi = (pll >> 10) & 0xf;
unsigned int mfn = pll & 0x3ff;
unsigned int mfd = (pll >> 16) & 0x3ff;
unsigned int pd = (pll >> 26) & 0xf;
mfi = mfi <= 5 ? 5 : mfi;
return lldiv(2 * (u64)f_ref * (mfi * (mfd + 1) + mfn),
(mfd + 1) * (pd + 1));
}
static ulong clk_in_32k(void)
{
return 1024 * CONFIG_MX27_CLK32;
}
static ulong clk_in_26m(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) {
/* divide by 1.5 */
return 26000000 * 2 / 3;
} else {
return 26000000;
}
}
static ulong imx_get_mpllclk(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
ulong cscr = readl(&pll->cscr);
ulong fref;
if (cscr & CSCR_MCU_SEL)
fref = clk_in_26m();
else
fref = clk_in_32k();
return imx_decode_pll(readl(&pll->mpctl0), fref);
}
static ulong imx_get_armclk(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
ulong cscr = readl(&pll->cscr);
ulong fref = imx_get_mpllclk();
ulong div;
if (!(cscr & CSCR_ARM_SRC_MPLL))
fref = lldiv((fref * 2), 3);
div = ((cscr >> 12) & 0x3) + 1;
return lldiv(fref, div);
}
static ulong imx_get_ahbclk(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
ulong cscr = readl(&pll->cscr);
ulong fref = imx_get_mpllclk();
ulong div;
div = ((cscr >> 8) & 0x3) + 1;
return lldiv(fref * 2, 3 * div);
}
static __attribute__((unused)) ulong imx_get_spllclk(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
ulong cscr = readl(&pll->cscr);
ulong fref;
if (cscr & CSCR_SP_SEL)
fref = clk_in_26m();
else
fref = clk_in_32k();
return imx_decode_pll(readl(&pll->spctl0), fref);
}
static ulong imx_decode_perclk(ulong div)
{
return lldiv((imx_get_mpllclk() * 2), (div * 3));
}
static ulong imx_get_perclk1(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
return imx_decode_perclk((readl(&pll->pcdr1) & 0x3f) + 1);
}
static ulong imx_get_perclk2(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
return imx_decode_perclk(((readl(&pll->pcdr1) >> 8) & 0x3f) + 1);
}
static __attribute__((unused)) ulong imx_get_perclk3(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
return imx_decode_perclk(((readl(&pll->pcdr1) >> 16) & 0x3f) + 1);
}
static __attribute__((unused)) ulong imx_get_perclk4(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
return imx_decode_perclk(((readl(&pll->pcdr1) >> 24) & 0x3f) + 1);
}
unsigned int mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
case MXC_ARM_CLK:
return imx_get_armclk();
case MXC_I2C_CLK:
return imx_get_ahbclk()/2;
case MXC_UART_CLK:
return imx_get_perclk1();
case MXC_FEC_CLK:
return imx_get_ahbclk();
case MXC_ESDHC_CLK:
return imx_get_perclk2();
}
return -1;
}
u32 get_cpu_rev(void)
{
return MXC_CPU_MX27 << 12;
}
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo (void)
{
char buf[32];
printf("CPU: Freescale i.MX27 at %s MHz\n\n",
strmhz(buf, imx_get_mpllclk()));
return 0;
}
#endif
int cpu_eth_init(struct bd_info *bis)
{
#if defined(CONFIG_FEC_MXC)
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
/* enable FEC clock */
writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1);
writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0);
return fecmxc_initialize(bis);
#else
return 0;
#endif
}
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
*/
int cpu_mmc_init(struct bd_info *bis)
{
#ifdef CONFIG_MMC_MXC
return mxc_mmc_init(bis);
#else
return 0;
#endif
}
void imx_gpio_mode(int gpio_mode)
{
struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE;
unsigned int pin = gpio_mode & GPIO_PIN_MASK;
unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
unsigned int aout = (gpio_mode & GPIO_AOUT_MASK) >> GPIO_AOUT_SHIFT;
unsigned int bout = (gpio_mode & GPIO_BOUT_MASK) >> GPIO_BOUT_SHIFT;
unsigned int tmp;
/* Pullup enable */
if (gpio_mode & GPIO_PUEN) {
writel(readl(&regs->port[port].puen) | (1 << pin),
&regs->port[port].puen);
} else {
writel(readl(&regs->port[port].puen) & ~(1 << pin),
&regs->port[port].puen);
}
/* Data direction */
if (gpio_mode & GPIO_OUT) {
writel(readl(&regs->port[port].gpio_dir) | 1 << pin,
&regs->port[port].gpio_dir);
} else {
writel(readl(&regs->port[port].gpio_dir) & ~(1 << pin),
&regs->port[port].gpio_dir);
}
/* Primary / alternate function */
if (gpio_mode & GPIO_AF) {
writel(readl(&regs->port[port].gpr) | (1 << pin),
&regs->port[port].gpr);
} else {
writel(readl(&regs->port[port].gpr) & ~(1 << pin),
&regs->port[port].gpr);
}
/* use as gpio? */
if (!(gpio_mode & (GPIO_PF | GPIO_AF))) {
writel(readl(&regs->port[port].gius) | (1 << pin),
&regs->port[port].gius);
} else {
writel(readl(&regs->port[port].gius) & ~(1 << pin),
&regs->port[port].gius);
}
/* Output / input configuration */
if (pin < 16) {
tmp = readl(&regs->port[port].ocr1);
tmp &= ~(3 << (pin * 2));
tmp |= (ocr << (pin * 2));
writel(tmp, &regs->port[port].ocr1);
writel(readl(&regs->port[port].iconfa1) & ~(3 << (pin * 2)),
&regs->port[port].iconfa1);
writel(readl(&regs->port[port].iconfa1) | aout << (pin * 2),
&regs->port[port].iconfa1);
writel(readl(&regs->port[port].iconfb1) & ~(3 << (pin * 2)),
&regs->port[port].iconfb1);
writel(readl(&regs->port[port].iconfb1) | bout << (pin * 2),
&regs->port[port].iconfb1);
} else {
pin -= 16;
tmp = readl(&regs->port[port].ocr2);
tmp &= ~(3 << (pin * 2));
tmp |= (ocr << (pin * 2));
writel(tmp, &regs->port[port].ocr2);
writel(readl(&regs->port[port].iconfa2) & ~(3 << (pin * 2)),
&regs->port[port].iconfa2);
writel(readl(&regs->port[port].iconfa2) | aout << (pin * 2),
&regs->port[port].iconfa2);
writel(readl(&regs->port[port].iconfb2) & ~(3 << (pin * 2)),
&regs->port[port].iconfb2);
writel(readl(&regs->port[port].iconfb2) | bout << (pin * 2),
&regs->port[port].iconfb2);
}
}
#ifdef CONFIG_MXC_UART
void mx27_uart1_init_pins(void)
{
int i;
unsigned int mode[] = {
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
};
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
}
#endif /* CONFIG_MXC_UART */
#ifdef CONFIG_FEC_MXC
void mx27_fec_init_pins(void)
{
int i;
unsigned int mode[] = {
PD0_AIN_FEC_TXD0,
PD1_AIN_FEC_TXD1,
PD2_AIN_FEC_TXD2,
PD3_AIN_FEC_TXD3,
PD4_AOUT_FEC_RX_ER,
PD5_AOUT_FEC_RXD1,
PD6_AOUT_FEC_RXD2,
PD7_AOUT_FEC_RXD3,
PD8_AF_FEC_MDIO,
PD9_AIN_FEC_MDC | GPIO_PUEN,
PD10_AOUT_FEC_CRS,
PD11_AOUT_FEC_TX_CLK,
PD12_AOUT_FEC_RXD0,
PD13_AOUT_FEC_RX_DV,
PD14_AOUT_FEC_CLR,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,
};
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
}
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
int i;
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
struct fuse_bank *bank = &iim->bank[0];
struct fuse_bank0_regs *fuse =
(struct fuse_bank0_regs *)bank->fuse_regs;
for (i = 0; i < 6; i++)
mac[6 - 1 - i] = readl(&fuse->mac_addr[i]) & 0xff;
}
#endif /* CONFIG_FEC_MXC */
#ifdef CONFIG_MMC_MXC
void mx27_sd1_init_pins(void)
{
int i;
unsigned int mode[] = {
PE18_PF_SD1_D0,
PE19_PF_SD1_D1,
PE20_PF_SD1_D2,
PE21_PF_SD1_D3,
PE22_PF_SD1_CMD,
PE23_PF_SD1_CLK,
};
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
}
void mx27_sd2_init_pins(void)
{
int i;
unsigned int mode[] = {
PB4_PF_SD2_D0,
PB5_PF_SD2_D1,
PB6_PF_SD2_D2,
PB7_PF_SD2_D3,
PB8_PF_SD2_CMD,
PB9_PF_SD2_CLK,
};
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
}
#endif /* CONFIG_MMC_MXC */

50
arch/arm/cpu/arm926ejs/mx27/relocate.S
View File

@@ -1,50 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* relocate - i.MX27-specific vector relocation
*
* Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
*/
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
/*
* The i.MX27 SoC is very specific with respect to exceptions: it
* does not provide RAM at the high vectors address (0xFFFF0000),
* thus only the low address (0x00000000) is useable; but that is
* in ROM. Therefore, vectors cannot be changed at all.
*
* However, these ROM-based vectors actually just perform indirect
* calls through pointers located in RAM at SoC-specific addresses,
* as follows:
*
* Offset Exception Use by ROM code
* 0x00000000 reset indirect branch to [0x00000014]
* 0x00000004 undefined instruction indirect branch to [0xfffffef0]
* 0x00000008 software interrupt indirect branch to [0xfffffef4]
* 0x0000000c prefetch abort indirect branch to [0xfffffef8]
* 0x00000010 data abort indirect branch to [0xfffffefc]
* 0x00000014 (reserved in ARMv5) vector to ROM reset: 0xc0000000
* 0x00000018 IRQ indirect branch to [0xffffff00]
* 0x0000001c FIQ indirect branch to [0xffffff04]
*
* In order to initialize exceptions on i.MX27, we must copy U-Boot's
* indirect (not exception!) vector table into 0xfffffef0..0xffffff04
* taking care not to copy vectors number 5 (reserved exception).
*/
.section .text.relocate_vectors,"ax",%progbits
ENTRY(relocate_vectors)
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
ldr r1, =32 /* size of vector table */
add r0, r0, r1 /* skip to indirect table */
ldr r1, =0xFFFFFEF0 /* i.MX27 indirect table */
ldmia r0!, {r2-r8} /* load indirect vectors 1..7 */
stmia r1!, {r2-r5, r7,r8} /* write all but vector 5 */
bx lr
ENDPROC(relocate_vectors)

41
arch/arm/cpu/arm926ejs/mx27/reset.c
View File

@@ -1,41 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* (C) Copyright 2009
* Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
*/
#include <common.h>
#include <cpu_func.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
/*
* Reset the cpu by setting up the watchdog timer and let it time out
*/
void reset_cpu(void)
{
struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
/* Disable watchdog and set Time-Out field to 0 */
writew(0x0000, &regs->wcr);
/* Write Service Sequence */
writew(0x5555, &regs->wsr);
writew(0xAAAA, &regs->wsr);
/* Enable watchdog */
writew(WCR_WDE, &regs->wcr);
while (1);
/*NOTREACHED*/
}

166
arch/arm/cpu/arm926ejs/mx27/timer.c
View File

@@ -1,166 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* (C) Copyright 2009
* Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
*/
#include <common.h>
#include <div64.h>
#include <init.h>
#include <time.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/ptrace.h>
#include <linux/delay.h>
/* General purpose timers bitfields */
#define GPTCR_SWR (1 << 15) /* Software reset */
#define GPTCR_FRR (1 << 8) /* Freerun / restart */
#define GPTCR_CLKSOURCE_32 (4 << 1) /* Clock source */
#define GPTCR_TEN 1 /* Timer enable */
DECLARE_GLOBAL_DATA_PTR;
#define timestamp (gd->arch.tbl)
#define lastinc (gd->arch.lastinc)
/*
* "time" is measured in 1 / CONFIG_SYS_HZ seconds,
* "tick" is internal timer period
*/
#ifdef CONFIG_MX27_TIMER_HIGH_PRECISION
/* ~0.4% error - measured with stop-watch on 100s boot-delay */
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
do_div(tick, CONFIG_MX27_CLK32);
return tick;
}
static inline unsigned long long time_to_tick(unsigned long long time)
{
time *= CONFIG_MX27_CLK32;
do_div(time, CONFIG_SYS_HZ);
return time;
}
static inline unsigned long long us_to_tick(unsigned long long us)
{
us = us * CONFIG_MX27_CLK32 + 999999;
do_div(us, 1000000);
return us;
}
#else
/* ~2% error */
#define TICK_PER_TIME ((CONFIG_MX27_CLK32 + CONFIG_SYS_HZ / 2) / \
CONFIG_SYS_HZ)
#define US_PER_TICK (1000000 / CONFIG_MX27_CLK32)
static inline unsigned long long tick_to_time(unsigned long long tick)
{
do_div(tick, TICK_PER_TIME);
return tick;
}
static inline unsigned long long time_to_tick(unsigned long long time)
{
return time * TICK_PER_TIME;
}
static inline unsigned long long us_to_tick(unsigned long long us)
{
us += US_PER_TICK - 1;
do_div(us, US_PER_TICK);
return us;
}
#endif
/* nothing really to do with interrupts, just starts up a counter. */
/* The 32768Hz 32-bit timer overruns in 131072 seconds */
int timer_init(void)
{
int i;
struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
/* setup GP Timer 1 */
writel(GPTCR_SWR, &regs->gpt_tctl);
writel(readl(&pll->pccr0) | PCCR0_GPT1_EN, &pll->pccr0);
writel(readl(&pll->pccr1) | PCCR1_PERCLK1_EN, &pll->pccr1);
for (i = 0; i < 100; i++)
writel(0, &regs->gpt_tctl); /* We have no udelay by now */
writel(0, &regs->gpt_tprer); /* 32Khz */
/* Freerun Mode, PERCLK1 input */
writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
&regs->gpt_tctl);
writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl);
return 0;
}
unsigned long long get_ticks(void)
{
struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
ulong now = readl(&regs->gpt_tcn); /* current tick value */
if (now >= lastinc) {
/*
* normal mode (non roll)
* move stamp forward with absolut diff ticks
*/
timestamp += (now - lastinc);
} else {
/* we have rollover of incrementer */
timestamp += (0xFFFFFFFF - lastinc) + now;
}
lastinc = now;
return timestamp;
}
static ulong get_timer_masked(void)
{
/*
* get_ticks() returns a long long (64 bit), it wraps in
* 2^64 / CONFIG_MX27_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
* 5 * 10^6 days - long enough.
*/
return tick_to_time(get_ticks());
}
ulong get_timer(ulong base)
{
return get_timer_masked() - base;
}
/* delay x useconds AND preserve advance timstamp value */
void __udelay(unsigned long usec)
{
unsigned long long tmp;
ulong tmo;
tmo = us_to_tick(usec);
tmp = get_ticks() + tmo; /* get current timestamp */
while (get_ticks() < tmp) /* loop till event */
/*NOP*/;
}
ulong get_tbclk(void)
{
return CONFIG_MX27_CLK32;
}

2
arch/arm/cpu/arm926ejs/start.S
View File

@@ -95,7 +95,7 @@ flush_dcache:
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
#ifdef CFG_SYS_EXCEPTION_VECTORS_HIGH
orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */
#else
bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */

6
arch/arm/cpu/armv7/arch_timer.c
View File

@@ -14,7 +14,7 @@
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_HZ_CLOCK
#ifndef CFG_SYS_HZ_CLOCK
static inline u32 read_cntfrq(void)
{
u32 frq;
@@ -29,8 +29,8 @@ int timer_init(void)
gd->arch.tbl = 0;
gd->arch.tbu = 0;
#ifdef CONFIG_SYS_HZ_CLOCK
gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK;
#ifdef CFG_SYS_HZ_CLOCK
gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK;
#else
gd->arch.timer_rate_hz = read_cntfrq();
#endif

11
arch/arm/cpu/armv7/ls102xa/Kconfig
View File

@@ -1,6 +1,8 @@
config ARCH_LS1021A
bool
select FSL_DEVICE_DISABLE
select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI
select LS102XA_STREAM_ID
select SYS_FSL_DDR_BE if SYS_FSL_DDR
select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
select SYS_FSL_IFC_BE
@@ -30,9 +32,15 @@ config ARCH_LS1021A
menu "LS102xA architecture"
depends on ARCH_LS1021A
config FSL_DEVICE_DISABLE
bool
config LS1_DEEP_SLEEP
bool "Deep sleep"
config LS102XA_STREAM_ID
bool
config MAX_CPUS
int "Maximum number of CPUs permitted for LS102xA"
default 2
@@ -43,6 +51,9 @@ config MAX_CPUS
cores, count the reserved ports. This will allocate enough memory
in spin table to properly handle all cores.
config PEN_ADDR_BIG_ENDIAN
bool
config SYS_CCI400_OFFSET
hex "Offset for CCI400 base"
depends on SYS_FSL_HAS_CCI400

29
arch/arm/cpu/armv7/ls102xa/cpu.c
View File

@@ -168,18 +168,18 @@ static void mmu_setup(void)
/* Level 1 has 512 entries */
for (i = 0; i < 512; i++) {
/* Mapping for PCIe 1 */
if (va_start >= CONFIG_SYS_PCIE1_VIRT_ADDR &&
va_start < (CONFIG_SYS_PCIE1_VIRT_ADDR +
CONFIG_SYS_PCIE_MMAP_SIZE))
if (va_start >= CFG_SYS_PCIE1_VIRT_ADDR &&
va_start < (CFG_SYS_PCIE1_VIRT_ADDR +
CFG_SYS_PCIE_MMAP_SIZE))
set_pgsection(level1_table, i,
CONFIG_SYS_PCIE1_PHYS_BASE + va_start,
CFG_SYS_PCIE1_PHYS_BASE + va_start,
MT_DEVICE_MEM);
/* Mapping for PCIe 2 */
else if (va_start >= CONFIG_SYS_PCIE2_VIRT_ADDR &&
va_start < (CONFIG_SYS_PCIE2_VIRT_ADDR +
CONFIG_SYS_PCIE_MMAP_SIZE))
else if (va_start >= CFG_SYS_PCIE2_VIRT_ADDR &&
va_start < (CFG_SYS_PCIE2_VIRT_ADDR +
CFG_SYS_PCIE_MMAP_SIZE))
set_pgsection(level1_table, i,
CONFIG_SYS_PCIE2_PHYS_BASE + va_start,
CFG_SYS_PCIE2_PHYS_BASE + va_start,
MT_DEVICE_MEM);
else
set_pgsection(level1_table, i,
@@ -302,20 +302,11 @@ int cpu_mmc_init(struct bd_info *bis)
}
#endif
int cpu_eth_init(struct bd_info *bis)
{
#if defined(CONFIG_TSEC_ENET) && !defined(CONFIG_DM_ETH)
tsec_standard_init(bis);
#endif
return 0;
}
int arch_cpu_init(void)
{
void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *rcpm2_base =
(void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
(void *)(CFG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
struct ccsr_scfg *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
u32 state;

4
arch/arm/cpu/armv7/ls102xa/fdt.c
View File

@@ -125,7 +125,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
#ifdef CONFIG_SYS_NS16550
do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64",
"clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
"clock-frequency", CFG_SYS_NS16550_CLK, 1);
#endif
sysclk_path = fdt_get_alias(blob, "sysclk");
@@ -183,7 +183,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
CONFIG_SYS_IFC_ADDR);
CFG_SYS_IFC_ADDR);
fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
#else
off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,

6
arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
View File

@@ -29,7 +29,7 @@
*/
static void __secure ls1_save_ddr_head(void)
{
const char *src = (const char *)CONFIG_SYS_SDRAM_BASE;
const char *src = (const char *)CFG_SYS_SDRAM_BASE;
char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);
struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
int i;
@@ -42,7 +42,7 @@ static void __secure ls1_save_ddr_head(void)
static void __secure ls1_fsm_setup(void)
{
void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *dcsr_rcpm_base = (void *)SYS_FSL_DCSR_RCPM_ADDR;
out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x00001001);
@@ -118,7 +118,7 @@ static void __secure ls1_delay(unsigned int loop)
static void __secure ls1_start_fsm(void)
{
void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR;
struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;

11
arch/arm/cpu/armv7/nonsec_virt.S
View File

@@ -112,8 +112,8 @@ ENTRY(_do_nonsec_entry)
ENDPROC(_do_nonsec_entry)
.macro get_cbar_addr addr
#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
ldr \addr, =CONFIG_ARM_GIC_BASE_ADDRESS
#ifdef CFG_ARM_GIC_BASE_ADDRESS
ldr \addr, =CFG_ARM_GIC_BASE_ADDRESS
#else
mrc p15, 4, \addr, c15, c0, 0 @ read CBAR
bfc \addr, #0, #15 @ clear reserved bits
@@ -205,11 +205,11 @@ ENTRY(_nonsec_init)
bx lr
ENDPROC(_nonsec_init)
#ifdef CONFIG_SMP_PEN_ADDR
#ifdef CFG_SMP_PEN_ADDR
/* void __weak smp_waitloop(unsigned previous_address); */
ENTRY(smp_waitloop)
WEAK(smp_waitloop)
wfi
ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address
ldr r1, =CFG_SMP_PEN_ADDR @ load start address
ldr r1, [r1]
#ifdef CONFIG_PEN_ADDR_BIG_ENDIAN
rev r1, r1
@@ -219,7 +219,6 @@ ENTRY(smp_waitloop)
mov r0, r1
b _do_nonsec_entry
ENDPROC(smp_waitloop)
.weak smp_waitloop
#endif
.popsection

75
arch/arm/cpu/armv7/psci.S
View File

@@ -36,34 +36,32 @@ _psci_vectors:
b default_psci_vector @ irq
b psci_fiq_enter @ fiq
ENTRY(psci_fiq_enter)
WEAK(psci_fiq_enter)
movs pc, lr
ENDPROC(psci_fiq_enter)
.weak psci_fiq_enter
ENTRY(default_psci_vector)
WEAK(default_psci_vector)
movs pc, lr
ENDPROC(default_psci_vector)
.weak default_psci_vector
ENTRY(psci_version)
ENTRY(psci_cpu_suspend)
ENTRY(psci_cpu_off)
ENTRY(psci_cpu_on)
ENTRY(psci_affinity_info)
ENTRY(psci_migrate)
ENTRY(psci_migrate_info_type)
ENTRY(psci_migrate_info_up_cpu)
ENTRY(psci_system_off)
ENTRY(psci_system_reset)
ENTRY(psci_features)
ENTRY(psci_cpu_freeze)
ENTRY(psci_cpu_default_suspend)
ENTRY(psci_node_hw_state)
ENTRY(psci_system_suspend)
ENTRY(psci_set_suspend_mode)
ENTRY(psi_stat_residency)
ENTRY(psci_stat_count)
WEAK(psci_version)
WEAK(psci_cpu_suspend)
WEAK(psci_cpu_off)
WEAK(psci_cpu_on)
WEAK(psci_affinity_info)
WEAK(psci_migrate)
WEAK(psci_migrate_info_type)
WEAK(psci_migrate_info_up_cpu)
WEAK(psci_system_off)
WEAK(psci_system_reset)
WEAK(psci_features)
WEAK(psci_cpu_freeze)
WEAK(psci_cpu_default_suspend)
WEAK(psci_node_hw_state)
WEAK(psci_system_suspend)
WEAK(psci_set_suspend_mode)
WEAK(psi_stat_residency)
WEAK(psci_stat_count)
mov r0, #ARM_PSCI_RET_NI @ Return -1 (Not Implemented)
mov pc, lr
ENDPROC(psci_stat_count)
@@ -84,24 +82,6 @@ ENDPROC(psci_cpu_on)
ENDPROC(psci_cpu_off)
ENDPROC(psci_cpu_suspend)
ENDPROC(psci_version)
.weak psci_version
.weak psci_cpu_suspend
.weak psci_cpu_off
.weak psci_cpu_on
.weak psci_affinity_info
.weak psci_migrate
.weak psci_migrate_info_type
.weak psci_migrate_info_up_cpu
.weak psci_system_off
.weak psci_system_reset
.weak psci_features
.weak psci_cpu_freeze
.weak psci_cpu_default_suspend
.weak psci_node_hw_state
.weak psci_system_suspend
.weak psci_set_suspend_mode
.weak psi_stat_residency
.weak psci_stat_count
_psci_table:
.word ARM_PSCI_FN_CPU_SUSPEND
@@ -179,12 +159,11 @@ _smc_psci:
movs pc, lr @ Return to the kernel
@ Requires dense and single-cluster CPU ID space
ENTRY(psci_get_cpu_id)
WEAK(psci_get_cpu_id)
mrc p15, 0, r0, c0, c0, 5 /* read MPIDR */
and r0, r0, #0xff /* return CPU ID in cluster */
bx lr
ENDPROC(psci_get_cpu_id)
.weak psci_get_cpu_id
/* Imported from Linux kernel */
ENTRY(psci_v7_flush_dcache_all)
@@ -236,7 +215,7 @@ finished:
bx lr
ENDPROC(psci_v7_flush_dcache_all)
ENTRY(psci_disable_smp)
WEAK(psci_disable_smp)
mrc p15, 0, r0, c1, c0, 1 @ ACTLR
bic r0, r0, #(1 << 6) @ Clear SMP bit
mcr p15, 0, r0, c1, c0, 1 @ ACTLR
@@ -244,16 +223,14 @@ ENTRY(psci_disable_smp)
dsb
bx lr
ENDPROC(psci_disable_smp)
.weak psci_disable_smp
ENTRY(psci_enable_smp)
WEAK(psci_enable_smp)
mrc p15, 0, r0, c1, c0, 1 @ ACTLR
orr r0, r0, #(1 << 6) @ Set SMP bit
mcr p15, 0, r0, c1, c0, 1 @ ACTLR
isb
bx lr
ENDPROC(psci_enable_smp)
.weak psci_enable_smp
ENTRY(psci_cpu_off_common)
push {lr}
@@ -316,15 +293,13 @@ ENTRY(psci_stack_setup)
bx r6
ENDPROC(psci_stack_setup)
ENTRY(psci_arch_init)
WEAK(psci_arch_init)
mov pc, lr
ENDPROC(psci_arch_init)
.weak psci_arch_init
ENTRY(psci_arch_cpu_entry)
WEAK(psci_arch_cpu_entry)
mov pc, lr
ENDPROC(psci_arch_cpu_entry)
.weak psci_arch_cpu_entry
ENTRY(psci_cpu_entry)
bl psci_enable_smp

11
arch/arm/cpu/armv7/s5p-common/pwm.c
View File

@@ -7,12 +7,11 @@
#include <common.h>
#include <errno.h>
#include <pwm.h>
#include <asm/io.h>
#include <asm/arch/pwm.h>
#include <asm/arch/clk.h>
int pwm_enable(int pwm_id)
int s5p_pwm_enable(int pwm_id)
{
const struct s5p_timer *pwm =
#if defined(CONFIG_ARCH_NEXELL)
@@ -30,7 +29,7 @@ int pwm_enable(int pwm_id)
return 0;
}
void pwm_disable(int pwm_id)
void s5p_pwm_disable(int pwm_id)
{
const struct s5p_timer *pwm =
#if defined(CONFIG_ARCH_NEXELL)
@@ -92,7 +91,7 @@ static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq)
#define NS_IN_SEC 1000000000UL
int pwm_config(int pwm_id, int duty_ns, int period_ns)
int s5p_pwm_config(int pwm_id, int duty_ns, int period_ns)
{
const struct s5p_timer *pwm =
#if defined(CONFIG_ARCH_NEXELL)
@@ -157,7 +156,7 @@ int pwm_config(int pwm_id, int duty_ns, int period_ns)
return 0;
}
int pwm_init(int pwm_id, int div, int invert)
int s5p_pwm_init(int pwm_id, int div, int invert)
{
u32 val;
const struct s5p_timer *pwm =
@@ -219,7 +218,7 @@ int pwm_init(int pwm_id, int div, int invert)
val |= TCON_INVERTER(pwm_id);
writel(val, &pwm->tcon);
pwm_enable(pwm_id);
s5p_pwm_enable(pwm_id);
return 0;
}

10
arch/arm/cpu/armv7/s5p-common/timer.c
View File

@@ -16,10 +16,6 @@
#include <asm/arch/clk.h>
#include <linux/delay.h>
/* Use the old PWM interface for now */
#undef CONFIG_DM_PWM
#include <pwm.h>
DECLARE_GLOBAL_DATA_PTR;
unsigned long get_current_tick(void);
@@ -49,9 +45,9 @@ static unsigned long timer_get_us_down(void)
int timer_init(void)
{
/* PWM Timer 4 */
pwm_init(4, MUX_DIV_4, 0);
pwm_config(4, 100000, 100000);
pwm_enable(4);
s5p_pwm_init(4, MUX_DIV_4, 0);
s5p_pwm_config(4, 100000, 100000);
s5p_pwm_enable(4);
/* Use this as the current monotonic time in us */
gd->arch.timer_reset_value = 0;

29
arch/arm/cpu/armv7/s5p4418/cpu.c
View File

@@ -13,10 +13,8 @@
#include <asm/io.h>
#include <asm/arch/nexell.h>
#include <asm/arch/clk.h>
#include <asm/arch/reset.h>
#include <asm/arch/tieoff.h>
#include <cpu_func.h>
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -45,39 +43,12 @@ static void cpu_soc_init(void)
nx_tieoff_set(NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_1, 1);
}
#ifdef CONFIG_PL011_SERIAL
static void serial_device_init(void)
{
char dev[10];
int id;
sprintf(dev, "nx-uart.%d", CONFIG_CONS_INDEX);
id = RESET_ID_UART0 + CONFIG_CONS_INDEX;
struct clk *clk = clk_get((const char *)dev);
/* reset control: Low active ___|--- */
nx_rstcon_setrst(id, RSTCON_ASSERT);
udelay(10);
nx_rstcon_setrst(id, RSTCON_NEGATE);
udelay(10);
/* set clock */
clk_disable(clk);
clk_set_rate(clk, CONFIG_PL011_CLOCK);
clk_enable(clk);
}
#endif
int arch_cpu_init(void)
{
flush_dcache_all();
cpu_soc_init();
clk_init();
if (IS_ENABLED(CONFIG_PL011_SERIAL))
serial_device_init();
return 0;
}

6
arch/arm/cpu/armv7/start.S
View File

@@ -151,16 +151,14 @@ ENDPROC(c_runtime_cpu_setup)
* Don't save anything to stack even if compiled with -O0
*
*************************************************************************/
ENTRY(save_boot_params)
WEAK(save_boot_params)
b save_boot_params_ret @ back to my caller
ENDPROC(save_boot_params)
.weak save_boot_params
#ifdef CONFIG_ARMV7_LPAE
ENTRY(switch_to_hypervisor)
WEAK(switch_to_hypervisor)
b switch_to_hypervisor_ret
ENDPROC(switch_to_hypervisor)
.weak switch_to_hypervisor
#endif
/*************************************************************************

4
arch/arm/cpu/armv7/stv0991/timer.c
View File

@@ -18,7 +18,7 @@ static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
(struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING)
#define GPT_RESOLUTION (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
#define GPT_RESOLUTION (CFG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
DECLARE_GLOBAL_DATA_PTR;
@@ -67,7 +67,7 @@ void __udelay(unsigned long usec)
{
ulong tmo;
ulong start = get_timer_masked();
ulong tenudelcnt = CONFIG_SYS_HZ_CLOCK / (1000 * 100);
ulong tenudelcnt = CFG_SYS_HZ_CLOCK / (1000 * 100);
ulong rndoff;
rndoff = (usec % 10) ? 1 : 0;

4
arch/arm/cpu/armv7/virt-v7.c
View File

@@ -26,8 +26,8 @@ static unsigned int read_id_pfr1(void)
static unsigned long get_gicd_base_address(void)
{
#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET;
#ifdef CFG_ARM_GIC_BASE_ADDRESS
return CFG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET;
#else
unsigned periphbase;

8
arch/arm/cpu/armv7m/systick-timer.c
View File

@@ -18,7 +18,7 @@
* The number of reference clock ticks that correspond to 10ms is normally
* defined in the SysTick Calibration register's TENMS field. However, on some
* devices this is wrong, so this driver allows the clock rate to be defined
* using CONFIG_SYS_HZ_CLOCK.
* using CFG_SYS_HZ_CLOCK.
*/
#include <common.h>
@@ -76,10 +76,10 @@ int timer_init(void)
/*
* If the TENMS field is inexact or wrong, specify the clock rate using
* CONFIG_SYS_HZ_CLOCK.
* CFG_SYS_HZ_CLOCK.
*/
#if defined(CONFIG_SYS_HZ_CLOCK)
gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK;
#if defined(CFG_SYS_HZ_CLOCK)
gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK;
#else
gd->arch.timer_rate_hz = (cal & SYSTICK_CAL_TENMS_MASK) * 100;
#endif

3
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View File

@@ -29,6 +29,7 @@ config ARCH_LS1028A
select ESBC_HDR_LS if CHAIN_OF_TRUST
select FSL_LAYERSCAPE
select FSL_LSCH3
select FSL_TZASC_400
select GICV3
select NXP_LSCH3_2
select SYS_FSL_HAS_CCI400
@@ -69,6 +70,7 @@ config ARCH_LS1043A
select GICV2
select HAS_FSL_XHCI_USB if USB_HOST
select SKIP_LOWLEVEL_INIT
select SYS_DPAA_FMAN
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
@@ -106,6 +108,7 @@ config ARCH_LS1046A
select GICV2
select HAS_FSL_XHCI_USB if USB_HOST
select SKIP_LOWLEVEL_INIT
select SYS_DPAA_FMAN
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR

115
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
View File

@@ -114,7 +114,7 @@ static struct mm_region early_map[] = {
CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
{ CFG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
CONFIG_SYS_FSL_IFC_SIZE1,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
@@ -130,9 +130,9 @@ static struct mm_region early_map[] = {
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
#ifdef CONFIG_FSL_IFC
/* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
/* Map IFC region #2 up to CFG_SYS_FLASH_BASE for NAND boot */
{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
CFG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
#endif
@@ -257,26 +257,26 @@ static struct mm_region final_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
CONFIG_SYS_PCIE1_PHYS_SIZE,
{ CFG_SYS_PCIE1_PHYS_ADDR, CFG_SYS_PCIE1_PHYS_ADDR,
CFG_SYS_PCIE1_PHYS_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
CONFIG_SYS_PCIE2_PHYS_SIZE,
{ CFG_SYS_PCIE2_PHYS_ADDR, CFG_SYS_PCIE2_PHYS_ADDR,
CFG_SYS_PCIE2_PHYS_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
CONFIG_SYS_PCIE3_PHYS_SIZE,
#ifdef CFG_SYS_PCIE3_PHYS_ADDR
{ CFG_SYS_PCIE3_PHYS_ADDR, CFG_SYS_PCIE3_PHYS_ADDR,
CFG_SYS_PCIE3_PHYS_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
#endif
#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
CONFIG_SYS_PCIE4_PHYS_SIZE,
#ifdef CFG_SYS_PCIE4_PHYS_ADDR
{ CFG_SYS_PCIE4_PHYS_ADDR, CFG_SYS_PCIE4_PHYS_ADDR,
CFG_SYS_PCIE4_PHYS_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
@@ -368,19 +368,19 @@ static struct mm_region final_map[] = {
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
CONFIG_SYS_PCIE1_PHYS_SIZE,
{ CFG_SYS_PCIE1_PHYS_ADDR, CFG_SYS_PCIE1_PHYS_ADDR,
CFG_SYS_PCIE1_PHYS_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
CONFIG_SYS_PCIE2_PHYS_SIZE,
{ CFG_SYS_PCIE2_PHYS_ADDR, CFG_SYS_PCIE2_PHYS_ADDR,
CFG_SYS_PCIE2_PHYS_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
CONFIG_SYS_PCIE3_PHYS_SIZE,
#ifdef CFG_SYS_PCIE3_PHYS_ADDR
{ CFG_SYS_PCIE3_PHYS_ADDR, CFG_SYS_PCIE3_PHYS_ADDR,
CFG_SYS_PCIE3_PHYS_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
@@ -391,7 +391,7 @@ static struct mm_region final_map[] = {
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
#endif
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
#ifdef CFG_SYS_MEM_RESERVE_SECURE
{}, /* space holder for secure mem */
#endif
{},
@@ -445,7 +445,7 @@ static inline void early_mmu_setup(void)
if (el == 3)
gd->arch.tlb_addr = CFG_SYS_FSL_OCRAM_BASE;
else
gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
gd->arch.tlb_addr = CFG_SYS_DDR_SDRAM_BASE;
gd->arch.tlb_fillptr = gd->arch.tlb_addr;
gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
@@ -477,25 +477,25 @@ static void fix_pcie_mmu_map(void)
(ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
for (i = 0; i < ARRAY_SIZE(final_map); i++) {
switch (final_map[i].phys) {
case CONFIG_SYS_PCIE1_PHYS_ADDR:
case CFG_SYS_PCIE1_PHYS_ADDR:
final_map[i].phys = 0x2000000000ULL;
final_map[i].virt = 0x2000000000ULL;
final_map[i].size = 0x800000000ULL;
break;
case CONFIG_SYS_PCIE2_PHYS_ADDR:
case CFG_SYS_PCIE2_PHYS_ADDR:
final_map[i].phys = 0x2800000000ULL;
final_map[i].virt = 0x2800000000ULL;
final_map[i].size = 0x800000000ULL;
break;
#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
case CONFIG_SYS_PCIE3_PHYS_ADDR:
#ifdef CFG_SYS_PCIE3_PHYS_ADDR
case CFG_SYS_PCIE3_PHYS_ADDR:
final_map[i].phys = 0x3000000000ULL;
final_map[i].virt = 0x3000000000ULL;
final_map[i].size = 0x800000000ULL;
break;
#endif
#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
case CONFIG_SYS_PCIE4_PHYS_ADDR:
#ifdef CFG_SYS_PCIE4_PHYS_ADDR
case CFG_SYS_PCIE4_PHYS_ADDR:
final_map[i].phys = 0x3800000000ULL;
final_map[i].virt = 0x3800000000ULL;
final_map[i].size = 0x800000000ULL;
@@ -568,7 +568,7 @@ static inline void final_mmu_setup(void)
}
}
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
#ifdef CFG_SYS_MEM_RESERVE_SECURE
if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
if (el == 3) {
/*
@@ -580,7 +580,7 @@ static inline void final_mmu_setup(void)
gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
final_map[index].virt = gd->arch.secure_ram & ~0x3;
final_map[index].phys = final_map[index].virt;
final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
final_map[index].size = CFG_SYS_MEM_RESERVE_SECURE;
final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
tlb_addr_save = gd->arch.tlb_addr;
@@ -1057,9 +1057,6 @@ int cpu_eth_init(struct bd_info *bis)
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
error = fsl_mc_ldpaa_init(bis);
#endif
#ifdef CONFIG_FMAN_ENET
fm_standard_init(bis);
#endif
return error;
}
@@ -1311,22 +1308,22 @@ phys_size_t get_effective_memsize(void)
* allocated from first region. If the memory extends to the second
* region (or the third region if applicable), Management Complex (MC)
* memory should be put into the highest region, i.e. the end of DDR
* memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so
* memory. CFG_MAX_MEM_MAPPED is set to the size of first region so
* U-Boot doesn't relocate itself into higher address. Should DDR be
* configured to skip the first region, this function needs to be
* adjusted.
*/
if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
ea_size = CONFIG_MAX_MEM_MAPPED;
if (gd->ram_size > CFG_MAX_MEM_MAPPED) {
ea_size = CFG_MAX_MEM_MAPPED;
rem = gd->ram_size - ea_size;
} else {
ea_size = gd->ram_size;
}
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
#ifdef CFG_SYS_MEM_RESERVE_SECURE
/* Check if we have enough space for secure memory */
if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
if (ea_size > CFG_SYS_MEM_RESERVE_SECURE)
ea_size -= CFG_SYS_MEM_RESERVE_SECURE;
else
printf("Error: No enough space for secure memory.\n");
#endif
@@ -1433,7 +1430,7 @@ int dram_init_banksize(void)
* gd->arch.secure_ram should be done to avoid running it repeatedly.
*/
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
#ifdef CFG_SYS_MEM_RESERVE_SECURE
if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
debug("No need to run again, skip %s\n", __func__);
@@ -1441,12 +1438,12 @@ int dram_init_banksize(void)
}
#endif
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
if (gd->ram_size > CFG_SYS_DDR_BLOCK1_SIZE) {
gd->bd->bi_dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE;
gd->bd->bi_dram[1].start = CFG_SYS_DDR_BLOCK2_BASE;
gd->bd->bi_dram[1].size = gd->ram_size -
CONFIG_SYS_DDR_BLOCK1_SIZE;
CFG_SYS_DDR_BLOCK1_SIZE;
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
@@ -1458,17 +1455,17 @@ int dram_init_banksize(void)
} else {
gd->bd->bi_dram[0].size = gd->ram_size;
}
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
#ifdef CFG_SYS_MEM_RESERVE_SECURE
if (gd->bd->bi_dram[0].size >
CONFIG_SYS_MEM_RESERVE_SECURE) {
CFG_SYS_MEM_RESERVE_SECURE) {
gd->bd->bi_dram[0].size -=
CONFIG_SYS_MEM_RESERVE_SECURE;
CFG_SYS_MEM_RESERVE_SECURE;
gd->arch.secure_ram = gd->bd->bi_dram[0].start +
gd->bd->bi_dram[0].size;
gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
gd->ram_size -= CFG_SYS_MEM_RESERVE_SECURE;
}
#endif /* CONFIG_SYS_MEM_RESERVE_SECURE */
#endif /* CFG_SYS_MEM_RESERVE_SECURE */
#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
/* Assign memory for MC */
@@ -1520,7 +1517,7 @@ int dram_init_banksize(void)
}
#endif
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
#ifdef CFG_SYS_MEM_RESERVE_SECURE
debug("%s is called. gd->ram_size is reduced to %lu\n",
__func__, (ulong)gd->ram_size);
#endif
@@ -1571,7 +1568,7 @@ void update_early_mmu_table(void)
if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
mmu_change_region_attr(
CONFIG_SYS_SDRAM_BASE,
CFG_SYS_SDRAM_BASE,
gd->ram_size,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
@@ -1579,8 +1576,8 @@ void update_early_mmu_table(void)
PTE_TYPE_VALID);
} else {
mmu_change_region_attr(
CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_DDR_BLOCK1_SIZE,
CFG_SYS_SDRAM_BASE,
CFG_SYS_DDR_BLOCK1_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
PTE_BLOCK_NS |
@@ -1589,10 +1586,10 @@ void update_early_mmu_table(void)
#ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
#error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
#endif
if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
if (gd->ram_size - CFG_SYS_DDR_BLOCK1_SIZE >
CONFIG_SYS_DDR_BLOCK2_SIZE) {
mmu_change_region_attr(
CONFIG_SYS_DDR_BLOCK2_BASE,
CFG_SYS_DDR_BLOCK2_BASE,
CONFIG_SYS_DDR_BLOCK2_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
@@ -1601,7 +1598,7 @@ void update_early_mmu_table(void)
mmu_change_region_attr(
CONFIG_SYS_DDR_BLOCK3_BASE,
gd->ram_size -
CONFIG_SYS_DDR_BLOCK1_SIZE -
CFG_SYS_DDR_BLOCK1_SIZE -
CONFIG_SYS_DDR_BLOCK2_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
@@ -1611,9 +1608,9 @@ void update_early_mmu_table(void)
#endif
{
mmu_change_region_attr(
CONFIG_SYS_DDR_BLOCK2_BASE,
CFG_SYS_DDR_BLOCK2_BASE,
gd->ram_size -
CONFIG_SYS_DDR_BLOCK1_SIZE,
CFG_SYS_DDR_BLOCK1_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
PTE_BLOCK_NS |

4
arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
View File

@@ -116,10 +116,10 @@ Flash Layout
Environment Variables
=====================
mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
the value CFG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
mcmemsize: MC DRAM block size in hex. If this variable is not defined, the value
CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
mcinitcmd: This environment variable is defined to initiate MC and DPL deployment
from the location where it is stored(NOR, NAND, SD, SATA, USB)during

2
arch/arm/cpu/armv8/fsl-layerscape/fdt.c
View File

@@ -646,7 +646,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
#ifdef CONFIG_SYS_NS16550
do_fixup_by_compat_u32(blob, "fsl,ns16550",
"clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
"clock-frequency", CFG_SYS_NS16550_CLK, 1);
#endif
do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency",

8
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
View File

@@ -24,11 +24,7 @@ void get_sys_info(struct sys_info *sys_info)
/* rcw_tmp is needed to get FMAN clock, or to get cluster group A
* mux 2 clock for LS1043A/LS1046A.
*/
#if defined(CONFIG_SYS_DPAA_FMAN) || \
defined(CONFIG_ARCH_LS1046A) || \
defined(CONFIG_ARCH_LS1043A)
u32 rcw_tmp;
#endif
__maybe_unused u32 rcw_tmp;
struct ccsr_clk *clk = (void *)(CFG_SYS_FSL_CLK_ADDR);
unsigned int cpu;
const u8 core_cplx_pll[8] = {
@@ -96,7 +92,7 @@ void get_sys_info(struct sys_info *sys_info)
#define HWA_CGA_M1_CLK_SEL 0xe0000000
#define HWA_CGA_M1_CLK_SHIFT 29
#ifdef CONFIG_SYS_DPAA_FMAN
#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
rcw_tmp = in_be32(&gur->rcwsr[7]);
switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
case 2:

2
arch/arm/cpu/armv8/fsl-layerscape/icid.c
View File

@@ -41,7 +41,7 @@ void set_icids(void)
/* setup general icid offsets */
set_icid(icid_tbl, icid_tbl_sz);
#ifdef CONFIG_SYS_DPAA_FMAN
#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
set_fman_icids(fman_icid_tbl, fman_icid_tbl_sz);
#endif
}

4
arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
View File

@@ -10,7 +10,7 @@
#include <fsl_sec.h>
#ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
@@ -59,7 +59,7 @@ struct icid_id_table icid_tbl[] = {
int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
#ifdef CONFIG_SYS_DPAA_FMAN
#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
struct fman_icid_id_table fman_icid_tbl[] = {
/* port id, icid */
SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END),

4
arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
View File

@@ -9,7 +9,7 @@
#include <asm/arch-fsl-layerscape/fsl_portals.h>
#ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
@@ -58,7 +58,7 @@ struct icid_id_table icid_tbl[] = {
int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
#ifdef CONFIG_SYS_DPAA_FMAN
#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
struct fman_icid_id_table fman_icid_tbl[] = {
/* port id, icid */
SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END),

6
arch/arm/cpu/armv8/fsl-layerscape/soc.c
View File

@@ -531,7 +531,7 @@ static void erratum_a010539(void)
porsr1 = in_be32(&gur->porsr1);
porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
out_be32((void *)(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
porsr1);
out_be32((void *)(CFG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
#endif
@@ -643,8 +643,8 @@ void init_pfe_scfg_dcfg_regs(void)
out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
| SCFG_RD_QOS1_PFE2_QOS));
ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
ecccr2 = in_be32(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
out_be32((void *)CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
ecccr2 | (unsigned int)DISABLE_PFE_ECC);
}
#endif

2
arch/arm/cpu/armv8/fsl-layerscape/spl.c
View File

@@ -116,7 +116,7 @@ void board_init_f(ulong dummy)
#endif
dram_init();
#ifdef CONFIG_SPL_FSL_LS_PPA
#ifndef CONFIG_SYS_MEM_RESERVE_SECURE
#ifndef CFG_SYS_MEM_RESERVE_SECURE
#error Need secure RAM for PPA
#endif
/*

12
arch/arm/cpu/armv8/psci.S
View File

@@ -12,11 +12,10 @@
/* Default PSCI function, return -1, Not Implemented */
#define PSCI_DEFAULT(__fn) \
ENTRY(__fn); \
WEAK(__fn); \
mov w0, #ARM_PSCI_RET_NI; \
ret; \
ENDPROC(__fn); \
.weak __fn
/* PSCI function and ID table definition*/
#define PSCI_TABLE(__id, __fn) \
@@ -207,7 +206,7 @@ handle_smc64:
* used for the return value, while in this PSCI environment, X0 usually holds
* the SMC function identifier, so X0 should be saved by caller function.
*/
ENTRY(psci_get_cpu_id)
WEAK(psci_get_cpu_id)
#ifdef CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER
mrs x9, MPIDR_EL1
ubfx x9, x9, #8, #8
@@ -221,7 +220,6 @@ ENTRY(psci_get_cpu_id)
add x0, x10, x9
ret
ENDPROC(psci_get_cpu_id)
.weak psci_get_cpu_id
/* CPU ID input in x0, stack top output in x0*/
LENTRY(psci_get_cpu_stack_top)
@@ -261,10 +259,9 @@ handle_sync:
* Override this function if custom error handling is
* needed for asynchronous aborts
*/
ENTRY(plat_error_handler)
WEAK(plat_error_handler)
ret
ENDPROC(plat_error_handler)
.weak plat_error_handler
handle_error:
bl psci_get_cpu_id
@@ -323,9 +320,8 @@ ENTRY(psci_setup_vectors)
ret
ENDPROC(psci_setup_vectors)
ENTRY(psci_arch_init)
WEAK(psci_arch_init)
ret
ENDPROC(psci_arch_init)
.weak psci_arch_init
.popsection

4
arch/arm/cpu/armv8/sec_firmware.c
View File

@@ -198,7 +198,7 @@ static int sec_firmware_load_image(const void *sec_firmware_img,
goto out;
}
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
#ifdef CFG_SYS_MEM_RESERVE_SECURE
/*
* The SEC Firmware must be stored in secure memory.
* Append SEC Firmware to secure mmu table.
@@ -211,7 +211,7 @@ static int sec_firmware_load_image(const void *sec_firmware_img,
sec_firmware_addr = (gd->arch.secure_ram & MEM_RESERVE_SECURE_ADDR_MASK) +
gd->arch.tlb_size;
#else
#error "The CONFIG_SYS_MEM_RESERVE_SECURE must be defined when enabled SEC Firmware support"
#error "The CFG_SYS_MEM_RESERVE_SECURE must be defined when enabled SEC Firmware support"
#endif
/* Align SEC Firmware base address to 4K */

3
arch/arm/dts/Makefile
View File

@@ -1259,6 +1259,9 @@ dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \
k3-am625-r5-sk.dtb
dtb-$(CONFIG_SOC_K3_AM625) += k3-am62a7-sk.dtb \
k3-am62a7-r5-sk.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7622-rfb.dtb \
mt7623a-unielec-u7623-02-emmc.dtb \

21
arch/arm/dts/at91-sam9x60_curiosity.dts
View File

@@ -49,6 +49,13 @@
atmel,pins =
<AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
usb1 {
pinctrl_usb_default: usb_default {
atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
};
};
};
};
@@ -89,3 +96,17 @@
phy-mode = "rmii";
status = "okay";
};
&usb1 {
num-ports = <3>;
atmel,vbus-gpio = <0
&pioD 15 GPIO_ACTIVE_HIGH
&pioD 18 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_default>;
status = "okay";
};
&usb2 {
status = "okay";
};

25
arch/arm/dts/at91-sama5d27_wlsom1_ek.dts
View File

@@ -143,7 +143,32 @@
pinmux = <PIN_PC9__GPIO>;
bias-pull-up;
};
pinctrl_usb_default: usb_default {
pinmux = <PIN_PA10__GPIO>;
bias-disable;
};
pinctrl_usba_vbus: usba_vbus {
pinmux = <PIN_PA16__GPIO>;
bias-disable;
};
};
};
};
};
&usb1 {
num-ports = <3>;
atmel,vbus-gpio = <0
&pioA PIN_PA10 GPIO_ACTIVE_HIGH
0
>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_default>;
status = "okay";
};
&usb2 {
status = "okay";
};

22
arch/arm/dts/at91-sama5d2_icp.dts
View File

@@ -154,7 +154,29 @@
<PIN_PA13__SDMMC0_CD>;
bias-disable;
};
pinctrl_usb_default: usb_default {
pinmux = <PIN_PC17__GPIO>;
bias-disable;
};
pinctrl_usba_vbus: usba_vbus {
pinmux = <PIN_PD23__GPIO>;
bias-disable;
};
};
};
};
};
&usb1 {
num-ports = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_default>;
status = "okay";
};
&usb2 {
phy_type = "hsic";
status = "okay";
};

108
arch/arm/dts/at91-sama7g5ek-u-boot.dtsi
View File

@@ -10,13 +10,88 @@
*
*/
#include "sama7g5-pinfunc.h"
#include <dt-bindings/reset/sama7g5-reset.h>
#include <dt-bindings/clock/at91.h>
/ {
chosen {
u-boot,dm-pre-reloc;
};
utmi {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
usb_phy0: phy@0 {
compatible = "microchip,sama7g5-usb-phy";
sfr-phandle = <&sfr>;
reg = <0>;
clocks = <&utmi_clk USB_UTMI1>;
clock-names = "utmi_clk";
status = "disabled";
#phy-cells = <0>;
};
usb_phy1: phy@1 {
compatible = "microchip,sama7g5-usb-phy";
sfr-phandle = <&sfr>;
reg = <1>;
clocks = <&utmi_clk USB_UTMI2>;
clock-names = "utmi_clk";
status = "disabled";
#phy-cells = <0>;
};
usb_phy2: phy@2 {
compatible = "microchip,sama7g5-usb-phy";
sfr-phandle = <&sfr>;
reg = <2>;
clocks = <&utmi_clk USB_UTMI3>;
clock-names = "utmi_clk";
status = "disabled";
#phy-cells = <0>;
};
};
utmi_clk: utmi-clk {
compatible = "microchip,sama7g5-utmi-clk";
sfr-phandle = <&sfr>;
#clock-cells = <1>;
clocks = <&pmc PMC_TYPE_CORE 27>;
clock-names = "utmi_clk";
resets = <&reset_controller SAMA7G5_RESET_USB_PHY1>,
<&reset_controller SAMA7G5_RESET_USB_PHY2>,
<&reset_controller SAMA7G5_RESET_USB_PHY3>;
reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
};
soc {
u-boot,dm-pre-reloc;
usb2: usb@400000 {
compatible = "microchip,sama7g5-ohci", "usb-ohci";
reg = <0x00400000 0x100000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 106>, <&utmi_clk USB_UTMI1>, <&usb_clk>;
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
usb3: usb@500000 {
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00500000 0x100000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&usb_clk>, <&pmc PMC_TYPE_PERIPHERAL 106>;
clock-names = "usb_clk", "ehci_clk";
status = "disabled";
};
sfr: sfr@e1624000 {
compatible = "microchip,sama7g5-sfr", "syscon";
reg = <0xe1624000 0x4000>;
};
};
};
@@ -38,6 +113,11 @@
&pioA {
u-boot,dm-pre-reloc;
pinctrl_usb_default: usb_default {
pinmux = <PIN_PC6__GPIO>;
bias-disable;
};
};
&pit64b0 {
@@ -60,3 +140,31 @@
u-boot,dm-pre-reloc;
};
&usb2 {
num-ports = <3>;
atmel,vbus-gpio = <0
0
&pioA PIN_PC6 GPIO_ACTIVE_HIGH
>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_default>;
phys = <&usb_phy2>;
phy-names = "usb";
status = "okay";
};
&usb3 {
status = "okay";
};
&usb_phy0 {
status = "okay";
};
&usb_phy1 {
status = "okay";
};
&usb_phy2 {
status = "okay";
};

23
arch/arm/dts/at91-sama7g5ek.dts
View File

@@ -45,13 +45,13 @@
};
};
gpio_keys {
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_key_gpio_default>;
bp1 {
button {
label = "PB_USER";
gpios = <&pioA PIN_PA12 GPIO_ACTIVE_LOW>;
linux,code = <KEY_PROG1>;
@@ -244,8 +244,8 @@
regulators {
vdd_3v3: VDD_IO {
regulator-name = "VDD_IO";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3700000>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
@@ -264,8 +264,8 @@
vddioddr: VDD_DDR {
regulator-name = "VDD_DDR";
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1450000>;
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
@@ -285,8 +285,8 @@
vddcore: VDD_CORE {
regulator-name = "VDD_CORE";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1850000>;
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1150000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
@@ -306,7 +306,7 @@
vddcpu: VDD_OTHER {
regulator-name = "VDD_OTHER";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1850000>;
regulator-max-microvolt = <1250000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-ramp-delay = <3125>;
@@ -326,8 +326,8 @@
vldo1: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3700000>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-state-standby {
@@ -707,7 +707,6 @@
ck_cd_rstn_vddsel {
pinmux = <PIN_PA0__SDMMC0_CK>,
<PIN_PA2__SDMMC0_RSTN>,
<PIN_PA14__SDMMC0_CD>,
<PIN_PA11__SDMMC0_DS>;
slew-rate = <0>;
bias-pull-up;

54
arch/arm/dts/k3-am62-main.dtsi
View File

@@ -165,6 +165,19 @@
};
};
crypto: crypto@40900000 {
compatible = "ti,am62-sa3ul";
reg = <0x00 0x40900000 0x00 0x1200>;
power-domains = <&k3_pds 70 TI_SCI_PD_SHARED>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
<&main_pktdma 0x7507 0>;
dma-names = "tx", "rx1", "rx2";
};
main_pmx0: pinctrl@f4000 {
compatible = "pinctrl-single";
reg = <0x00 0xf4000 0x00 0x2ac>;
@@ -530,4 +543,45 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
};
ecap0: pwm@23100000 {
compatible = "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x00 0x23100000 0x00 0x100>;
power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 51 0>;
clock-names = "fck";
};
ecap1: pwm@23110000 {
compatible = "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x00 0x23110000 0x00 0x100>;
power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 52 0>;
clock-names = "fck";
};
ecap2: pwm@23120000 {
compatible = "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x00 0x23120000 0x00 0x100>;
power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 53 0>;
clock-names = "fck";
};
main_mcan0: can@20701000 {
compatible = "bosch,m_can";
reg = <0x00 0x20701000 0x00 0x200>,
<0x00 0x20708000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 98 6>, <&k3_clks 98 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
};

28
arch/arm/dts/k3-am62-mcu.dtsi
View File

@@ -53,4 +53,32 @@
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 148 0>;
};
mcu_gpio_intr: interrupt-controller@4210000 {
compatible = "ti,sci-intr";
reg = <0x00 0x04210000 0x00 0x200>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <1>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <5>;
ti,interrupt-ranges = <0 104 4>;
};
mcu_gpio0: gpio@4201000 {
compatible = "ti,am64-gpio", "ti,keystone-gpio";
reg = <0x00 0x4201000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&mcu_gpio_intr>;
interrupts = <30>, <31>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <24>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 79 0>;
clock-names = "gpio";
};
};

1
arch/arm/dts/k3-am62.dtsi
View File

@@ -66,6 +66,7 @@
<0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
<0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
<0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
<0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
<0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
<0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */

5
arch/arm/dts/k3-am625-r5-sk.dts
View File

@@ -155,3 +155,8 @@
status = "okay";
u-boot,dm-spl;
};
&ospi0 {
reg = <0x00 0x0fc40000 0x00 0x100>,
<0x00 0x60000000 0x00 0x08000000>;
};

24
arch/arm/dts/k3-am625-sk-u-boot.dtsi
View File

@@ -102,3 +102,27 @@
&main_mmc1_pins_default {
u-boot,dm-spl;
};
&fss {
u-boot,dm-spl;
};
&ospi0_pins_default {
u-boot,dm-spl;
};
&ospi0 {
u-boot,dm-spl;
flash@0 {
u-boot,dm-spl;
partitions {
u-boot,dm-spl;
partition@3fc0000 {
u-boot,dm-spl;
};
};
};
};

354
arch/arm/dts/k3-am625-sk.dts
View File

@@ -18,7 +18,12 @@
aliases {
serial2 = &main_uart0;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
mmc2 = &sdhci2;
spi0 = &ospi0;
ethernet0 = &cpsw_port1;
ethernet1 = &cpsw_port2;
};
chosen {
@@ -38,6 +43,15 @@
#size-cells = <2>;
ranges;
ramoops@9ca00000 {
compatible = "ramoops";
reg = <0x00 0x9ca00000 0x00 0x00100000>;
record-size = <0x8000>;
console-size = <0x8000>;
ftrace-size = <0x00>;
pmsg-size = <0x8000>;
};
secure_tfa_ddr: tfa@9e780000 {
reg = <0x00 0x9e780000 0x00 0x80000>;
alignment = <0x1000>;
@@ -56,6 +70,79 @@
no-map;
};
};
vmain_pd: regulator-0 {
/* TPS65988 PD CONTROLLER OUTPUT */
compatible = "regulator-fixed";
regulator-name = "vmain_pd";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
vcc_5v0: regulator-1 {
/* Output of LM34936 */
compatible = "regulator-fixed";
regulator-name = "vcc_5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vmain_pd>;
regulator-always-on;
regulator-boot-on;
};
vcc_3v3_sys: regulator-2 {
/* output of LM61460-Q1 */
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_sys";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vmain_pd>;
regulator-always-on;
regulator-boot-on;
};
vdd_mmc1: regulator-3 {
/* TPS22918DBVR */
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
enable-active-high;
vin-supply = <&vcc_3v3_sys>;
gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
};
vdd_sd_dv: regulator-4 {
/* Output of TLV71033 */
compatible = "regulator-gpio";
regulator-name = "tlv71033";
pinctrl-names = "default";
pinctrl-0 = <&vdd_sd_dv_pins_default>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
vin-supply = <&vcc_5v0>;
gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>;
states = <1800000 0x0>,
<3300000 0x1>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&usr_led_pins_default>;
led-0 {
label = "am62-sk:green:heartbeat";
gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
function = LED_FUNCTION_HEARTBEAT;
default-state = "off";
};
};
};
&main_pmx0 {
@@ -66,6 +153,42 @@
>;
};
main_i2c0_pins_default: main-i2c0-pins-default {
pinctrl-single,pins = <
AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
>;
};
main_i2c1_pins_default: main-i2c1-pins-default {
pinctrl-single,pins = <
AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
>;
};
main_i2c2_pins_default: main-i2c2-pins-default {
pinctrl-single,pins = <
AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */
AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
>;
};
main_mmc0_pins_default: main-mmc0-pins-default {
pinctrl-single,pins = <
AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */
AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */
AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */
AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */
AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */
AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */
AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */
>;
};
main_mmc1_pins_default: main-mmc1-pins-default {
pinctrl-single,pins = <
AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
@@ -77,6 +200,81 @@
AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */
>;
};
usr_led_pins_default: usr-led-pins-default {
pinctrl-single,pins = <
AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */
>;
};
main_mdio1_pins_default: main-mdio1-pins-default {
pinctrl-single,pins = <
AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */
AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */
>;
};
main_rgmii1_pins_default: main-rgmii1-pins-default {
pinctrl-single,pins = <
AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */
AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */
AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */
AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */
AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */
AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */
AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */
AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */
AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */
AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */
AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */
AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */
>;
};
main_rgmii2_pins_default: main-rgmii2-pins-default {
pinctrl-single,pins = <
AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */
AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */
AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */
AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */
AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
>;
};
ospi0_pins_default: ospi0-pins-default {
pinctrl-single,pins = <
AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */
AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */
AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */
AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */
AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */
AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */
AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */
AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */
AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */
AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */
>;
};
vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
pinctrl-single,pins = <
AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */
>;
};
main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-pins-default {
pinctrl-single,pins = <
AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */
>;
};
};
&wkup_uart0 {
@@ -128,10 +326,41 @@
&main_i2c0 {
status = "disabled";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
};
&main_i2c1 {
status = "disabled";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
exp1: gpio@22 {
compatible = "ti,tca6424";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
"PRU_DETECT", "MMC1_SD_EN",
"VPP_LDO_EN", "EXP_PS_3V3_En",
"EXP_PS_5V0_En", "EXP_HAT_DETECT",
"GPIO_AUD_RSTn", "GPIO_eMMC_RSTn",
"UART1_FET_BUF_EN", "WL_LT_EN",
"GPIO_HDMI_RSTn", "CSI_GPIO1",
"CSI_GPIO2", "PRU_3V3_EN",
"HDMI_INTn", "TEST_GPIO2",
"MCASP1_FET_EN", "MCASP1_BUF_BT_EN",
"MCASP1_FET_SEL", "UART1_FET_SEL",
"TSINT#", "IO_EXP_TEST_LED";
interrupt-parent = <&main_gpio1>;
interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;
};
};
&main_i2c2 {
@@ -142,9 +371,134 @@
status = "disabled";
};
&sdhci0 {
pinctrl-names = "default";
pinctrl-0 = <&main_mmc0_pins_default>;
ti,driver-strength-ohm = <50>;
disable-wp;
};
&sdhci1 {
/* SD/MMC */
vmmc-supply = <&vdd_mmc1>;
vqmmc-supply = <&vdd_sd_dv>;
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
disable-wp;
};
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&main_mdio1_pins_default
&main_rgmii1_pins_default
&main_rgmii2_pins_default>;
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy0>;
};
&cpsw_port2 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy1>;
};
&cpsw3g_mdio {
cpsw3g_phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,min-output-impedance;
};
cpsw3g_phy1: ethernet-phy@1 {
reg = <1>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,min-output-impedance;
};
};
&mailbox0_cluster0 {
mbox_m4_0: mbox-m4-0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
};
&ospi0 {
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
flash@0{
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <25000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "ospi.tiboot3";
reg = <0x0 0x80000>;
};
partition@80000 {
label = "ospi.tispl";
reg = <0x80000 0x200000>;
};
partition@280000 {
label = "ospi.u-boot";
reg = <0x280000 0x400000>;
};
partition@680000 {
label = "ospi.env";
reg = <0x680000 0x40000>;
};
partition@6c0000 {
label = "ospi.env.backup";
reg = <0x6c0000 0x40000>;
};
partition@800000 {
label = "ospi.rootfs";
reg = <0x800000 0x37c0000>;
};
partition@3fc0000 {
label = "ospi.phypattern";
reg = <0x3fc0000 0x40000>;
};
};
};
};
&ecap0 {
status = "disabled";
};
&ecap1 {
status = "disabled";
};
&ecap2 {
status = "disabled";
};
&main_mcan0 {
status = "disabled";
};

2798
arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi Normal file
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2814
arch/arm/dts/k3-am62a-ddr.dtsi Normal file
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298
arch/arm/dts/k3-am62a-main.dtsi Normal file
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@@ -0,0 +1,298 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for AM62A SoC Family Main Domain peripherals
*
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_main {
oc_sram: sram@70000000 {
compatible = "mmio-sram";
reg = <0x00 0x70000000 0x00 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x70000000 0x10000>;
};
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
<0x00 0x01880000 0x00 0xc0000>, /* GICR */
<0x00 0x01880000 0x00 0xc0000>, /* GICR */
<0x01 0x00000000 0x00 0x2000>, /* GICC */
<0x01 0x00010000 0x00 0x1000>, /* GICH */
<0x01 0x00020000 0x00 0x2000>; /* GICV */
#address-cells = <2>;
#size-cells = <2>;
ranges;
#interrupt-cells = <3>;
interrupt-controller;
/*
* vcpumntirq:
* virtual CPU interface maintenance interrupt
*/
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
gic_its: msi-controller@1820000 {
compatible = "arm,gic-v3-its";
reg = <0x00 0x01820000 0x00 0x10000>;
socionext,synquacer-pre-its = <0x1000000 0x400000>;
msi-controller;
#msi-cells = <1>;
};
};
main_conf: syscon@100000 {
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
reg = <0x00 0x00100000 0x00 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00 0x00 0x00100000 0x20000>;
};
dmss: bus@48000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges;
ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>;
ti,sci-dev-id = <25>;
secure_proxy_main: mailbox@4d000000 {
compatible = "ti,am654-secure-proxy";
reg = <0x00 0x4d000000 0x00 0x80000>,
<0x00 0x4a600000 0x00 0x80000>,
<0x00 0x4a400000 0x00 0x80000>;
reg-names = "target_data", "rt", "scfg";
#mbox-cells = <1>;
interrupt-names = "rx_012";
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
};
};
dmsc: system-controller@44043000 {
compatible = "ti,k2g-sci";
reg = <0x00 0x44043000 0x00 0xfe0>;
reg-names = "debug_messages";
ti,host-id = <12>;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 12>,
<&secure_proxy_main 13>;
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
};
k3_clks: clock-controller {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
k3_reset: reset-controller {
compatible = "ti,sci-reset";
#reset-cells = <2>;
};
};
main_pmx0: pinctrl@f4000 {
compatible = "pinctrl-single";
reg = <0x00 0xf4000 0x00 0x2ac>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
main_uart0: serial@2800000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 146 0>;
clock-names = "fclk";
status = "disabled";
};
main_uart1: serial@2810000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02810000 0x00 0x100>;
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 152 0>;
clock-names = "fclk";
status = "disabled";
};
main_uart2: serial@2820000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02820000 0x00 0x100>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 153 0>;
clock-names = "fclk";
status = "disabled";
};
main_uart3: serial@2830000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02830000 0x00 0x100>;
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 154 0>;
clock-names = "fclk";
status = "disabled";
};
main_uart4: serial@2840000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02840000 0x00 0x100>;
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 155 0>;
clock-names = "fclk";
status = "disabled";
};
main_uart5: serial@2850000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02850000 0x00 0x100>;
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 156 0>;
clock-names = "fclk";
status = "disabled";
};
main_uart6: serial@2860000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02860000 0x00 0x100>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 158 0>;
clock-names = "fclk";
status = "disabled";
};
main_i2c0: i2c@20000000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x00 0x20000000 0x00 0x100>;
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 102 2>;
clock-names = "fck";
status = "disabled";
};
main_i2c1: i2c@20010000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x00 0x20010000 0x00 0x100>;
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 103 2>;
clock-names = "fck";
status = "disabled";
};
main_i2c2: i2c@20020000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x00 0x20020000 0x00 0x100>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 104 2>;
clock-names = "fck";
status = "disabled";
};
main_i2c3: i2c@20030000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x00 0x20030000 0x00 0x100>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 105 2>;
clock-names = "fck";
status = "disabled";
};
main_gpio_intr: interrupt-controller@a00000 {
compatible = "ti,sci-intr";
reg = <0x00 0x00a00000 0x00 0x800>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <1>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <3>;
ti,interrupt-ranges = <0 32 16>;
status = "disabled";
};
main_gpio0: gpio@600000 {
compatible = "ti,am64-gpio", "ti,keystone-gpio";
reg = <0x00 0x00600000 0x0 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <190>, <191>, <192>,
<193>, <194>, <195>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <87>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 77 0>;
clock-names = "gpio";
status = "disabled";
};
main_gpio1: gpio@601000 {
compatible = "ti,am64-gpio", "ti,keystone-gpio";
reg = <0x00 0x00601000 0x0 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <180>, <181>, <182>,
<183>, <184>, <185>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <88>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 78 0>;
clock-names = "gpio";
status = "disabled";
};
sdhci1: mmc@fa00000 {
compatible = "ti,am62-sdhci";
reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
clock-names = "clk_ahb", "clk_xin";
ti,trm-icp = <0x2>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
ti,otap-del-sel-sdr104 = <0x6>;
ti,otap-del-sel-ddr50 = <0x9>;
ti,itap-del-sel-legacy = <0x0>;
ti,itap-del-sel-sd-hs = <0x0>;
ti,itap-del-sel-sdr12 = <0x0>;
ti,itap-del-sel-sdr25 = <0x0>;
ti,clkbuf-sel = <0x7>;
bus-width = <4>;
no-1-8-v;
status = "disabled";
};
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for AM625 SoC Family MCU Domain peripherals
*
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_mcu {
mcu_pmx0: pinctrl@4084000 {
compatible = "pinctrl-single";
reg = <0x00 0x04084000 0x00 0x88>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
status = "disabled";
};
mcu_uart0: serial@4a00000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a00000 0x00 0x100>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 149 0>;
clock-names = "fclk";
status = "disabled";
};
mcu_i2c0: i2c@4900000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x00 0x04900000 0x00 0x100>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 106 2>;
clock-names = "fck";
status = "disabled";
};
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for AM62A SoC Family Wakeup Domain peripherals
*
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_wakeup {
wkup_conf: syscon@43000000 {
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
reg = <0x00 0x43000000 0x00 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00 0x00 0x43000000 0x20000>;
chipid: chipid@14 {
compatible = "ti,am654-chipid";
reg = <0x14 0x4>;
};
};
wkup_uart0: serial@2b300000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x2b300000 0x00 0x100>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 114 0>;
clock-names = "fclk";
status = "disabled";
};
wkup_i2c0: i2c@2b200000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x00 0x02b200000 0x00 0x100>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 107 4>;
clock-names = "fck";
status = "disabled";
};
wkup_rtc0: rtc@2b1f0000 {
compatible = "ti,am62-rtc";
reg = <0x00 0x2b1f0000 0x00 0x100>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 117 6> , <&k3_clks 117 0>;
clock-names = "vbus", "osc32k";
power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>;
wakeup-source;
status = "disabled";
};
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for AM62A SoC Family
*
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
/ {
model = "Texas Instruments K3 AM62A SoC";
compatible = "ti,am62a7";
interrupt-parent = <&gic500>;
#address-cells = <2>;
#size-cells = <2>;
chosen { };
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
psci: psci {
compatible = "arm,psci-1.0";
method = "smc";
};
};
a53_timer0: timer-cl0-cpu0 {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
};
pmu: pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
cbass_main: bus@f0000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
<0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
<0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
<0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
<0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
<0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
<0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
<0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
<0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
<0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
<0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */
<0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
<0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */
<0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
<0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
<0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
<0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
<0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
<0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */
<0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
<0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
<0x00 0x7e000000 0x00 0x7e000000 0x00 0x00100000>, /* C7x_0 */
<0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
/* MCU Domain Range */
<0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
<0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
<0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
<0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU R5 IRAM0 */
<0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>, /* MCU R5 IRAM1 */
/* Wakeup Domain Range */
<0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>,
<0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>,
<0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM */
<0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM */
cbass_mcu: bus@4000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */
<0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
<0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
<0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */
<0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */
};
cbass_wakeup: bus@b00000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
<0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */
<0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/
<0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
};
};
};
/* Now include the peripherals for each bus segments */
#include "k3-am62a-main.dtsi"
#include "k3-am62a-mcu.dtsi"
#include "k3-am62a-wakeup.dtsi"

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// SPDX-License-Identifier: GPL-2.0
/*
* AM62A7 SK dts file for R5 SPL
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-am62a7-sk.dts"
#include "k3-am62a-ddr-1866mhz-32bit.dtsi"
#include "k3-am62a-ddr.dtsi"
#include "k3-am62a7-sk-u-boot.dtsi"
/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
serial0 = &wkup_uart0;
serial3 = &main_uart1;
};
chosen {
stdout-path = "serial2:115200n8";
tick-timer = &timer1;
};
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0x00000000 0x80000000>; /* 2G RAM */
u-boot,dm-spl;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
alignment = <0x1000>;
no-map;
};
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>;
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1200000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
u-boot,dm-spl;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <36>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 22>,
<&secure_proxy_main 23>;
u-boot,dm-spl;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&cbass_main {
sa3_secproxy: secproxy@44880000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg = <0x00 0x44880000 0x00 0x20000>,
<0x0 0x44860000 0x0 0x20000>,
<0x0 0x43600000 0x0 0x10000>;
reg-names = "rt", "scfg", "target_data";
u-boot,dm-spl;
};
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
mboxes= <&secure_proxy_main 1>,
<&secure_proxy_main 0>,
<&sa3_secproxy 0>;
mbox-names = "tx", "rx", "boot_notify";
u-boot,dm-spl;
};
};
&mcu_pmx0 {
status = "okay";
u-boot,dm-spl;
wkup_uart0_pins_default: wkup-uart0-pins-default {
pinctrl-single,pins = <
AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6) WKUP_UART0_CTSn */
AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */
AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4) WKUP_UART0_RXD */
AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */
>;
u-boot,dm-spl;
};
};
&main_pmx0 {
u-boot,dm-spl;
main_uart1_pins_default: main-uart1-pins-default {
pinctrl-single,pins = <
AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */
AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */
AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */
AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */
>;
u-boot,dm-spl;
};
};
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
status = "okay";
u-boot,dm-spl;
};
/* Main UART1 is used for TIFS firmware logs */
&main_uart1 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
status = "okay";
u-boot,dm-spl;
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Common AM62A EVM dts file for SPLs
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
chosen {
stdout-path = "serial2:115200n8";
tick-timer = &timer1;
};
memory@80000000 {
u-boot,dm-spl;
};
};
&cbass_main{
u-boot,dm-spl;
timer1: timer@2400000 {
compatible = "ti,omap5430-timer";
reg = <0x00 0x2400000 0x00 0x80>;
ti,timer-alwon;
clock-frequency = <25000000>;
u-boot,dm-spl;
};
};
&dmss {
u-boot,dm-spl;
};
&secure_proxy_main {
u-boot,dm-spl;
};
&dmsc {
u-boot,dm-spl;
};
&k3_pds {
u-boot,dm-spl;
};
&k3_clks {
u-boot,dm-spl;
};
&k3_reset {
u-boot,dm-spl;
};
&wkup_conf {
u-boot,dm-spl;
};
&chipid {
u-boot,dm-spl;
};
&main_pmx0 {
u-boot,dm-spl;
};
&main_uart0 {
u-boot,dm-spl;
};
&main_uart0_pins_default {
u-boot,dm-spl;
};
&main_uart1 {
u-boot,dm-spl;
};
&cbass_mcu {
u-boot,dm-spl;
};
&cbass_wakeup {
u-boot,dm-spl;
};
&mcu_pmx0 {
u-boot,dm-spl;
};
&wkup_uart0 {
u-boot,dm-spl;
};
&main_gpio0 {
u-boot,dm-spl;
};
&main_i2c0 {
u-boot,dm-spl;
};
&main_i2c0_pins_default {
u-boot,dm-spl;
};
&main_i2c1 {
u-boot,dm-spl;
};
&main_i2c1_pins_default {
u-boot,dm-spl;
};
&exp1 {
u-boot,dm-spl;
};
&sdhci1 {
u-boot,dm-spl;
};
&main_mmc1_pins_default {
u-boot,dm-spl;
};
&k3_reset {
u-boot,dm-spl;
};
&dmsc {
u-boot,dm-spl;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
u-boot,dm-spl;
};
};
&vdd_mmc1 {
u-boot,dm-spl;
};

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// SPDX-License-Identifier: GPL-2.0
/*
* AM62A SK: https://www.ti.com/lit/zip/sprr459
*
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include "k3-am62a7.dtsi"
/ {
compatible = "ti,am62a7-sk", "ti,am62a7";
model = "Texas Instruments AM62A7 SK";
aliases {
serial2 = &main_uart0;
mmc1 = &sdhci1;
};
chosen {
stdout-path = "serial2:115200n8";
};
memory@80000000 {
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_tfa_ddr: tfa@9e780000 {
reg = <0x00 0x9e780000 0x00 0x80000>;
alignment = <0x1000>;
no-map;
};
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
alignment = <0x1000>;
no-map;
};
wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 {
compatible = "shared-dma-pool";
reg = <0x00 0x9c900000 0x00 0x01e00000>;
no-map;
};
};
vmain_pd: regulator-0 {
/* TPS25750 PD CONTROLLER OUTPUT */
compatible = "regulator-fixed";
regulator-name = "vmain_pd";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
vcc_5v0: regulator-1 {
/* Output of TPS63070 */
compatible = "regulator-fixed";
regulator-name = "vcc_5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vmain_pd>;
regulator-always-on;
regulator-boot-on;
};
vcc_3v3_sys: regulator-2 {
/* output of LM5141-Q1 */
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_sys";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vmain_pd>;
regulator-always-on;
regulator-boot-on;
};
vdd_mmc1: regulator-3 {
/* TPS22918DBVR */
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
enable-active-high;
gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&usr_led_pins_default>;
led-0 {
label = "am62a-sk:green:heartbeat";
gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
function = LED_FUNCTION_HEARTBEAT;
default-state = "off";
};
};
};
&main_pmx0 {
main_uart0_pins_default: main-uart0-pins-default {
pinctrl-single,pins = <
AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
>;
};
main_i2c0_pins_default: main-i2c0-pins-default {
pinctrl-single,pins = <
AM62AX_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
AM62AX_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
>;
};
main_i2c1_pins_default: main-i2c1-pins-default {
pinctrl-single,pins = <
AM62AX_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
AM62AX_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
>;
};
main_i2c2_pins_default: main-i2c2-pins-default {
pinctrl-single,pins = <
AM62AX_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */
AM62AX_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
>;
};
main_mmc1_pins_default: main-mmc1-pins-default {
pinctrl-single,pins = <
AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
AM62AX_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
AM62AX_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
AM62AX_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
AM62AX_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
AM62AX_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
AM62AX_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */
>;
};
usr_led_pins_default: usr-led-pins-default {
pinctrl-single,pins = <
AM62AX_IOPAD(0x244, PIN_OUTPUT, 7) /* (D18) MMC1_SDWP.GPIO1_49 */
>;
};
};
&main_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
};
&main_i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
exp1: gpio@22 {
compatible = "ti,tca6424";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
"BT_EN_SOC", "MMC1_SD_EN",
"VPP_EN", "EXP_PS_3V3_En",
"EXP_PS_5V0_En", "EXP_HAT_DETECT",
"GPIO_AUD_RSTn", "GPIO_eMMC_RSTn",
"UART1_FET_BUF_EN", "BT_UART_WAKE_SOC",
"GPIO_HDMI_RSTn", "CSI_GPIO0",
"CSI_GPIO1", "WLAN_ALERTn",
"HDMI_INTn", "TEST_GPIO2",
"MCASP1_FET_EN", "MCASP1_BUF_BT_EN",
"MCASP1_FET_SEL", "UART1_FET_SEL",
"PD_I2C_IRQ", "IO_EXP_TEST_LED";
};
};
&sdhci1 {
/* SD/MMC */
status = "okay";
vmmc-supply = <&vdd_mmc1>;
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
disable-wp;
};
&main_gpio0 {
status = "okay";
};
&main_gpio1 {
status = "okay";
};
&main_gpio_intr {
status = "okay";
};
&main_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
};

103
arch/arm/dts/k3-am62a7.dtsi Normal file
View File

@@ -0,0 +1,103 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for AM62A7 SoC family in Quad core configuration
*
* TRM: https://www.ti.com/lit/zip/spruj16
*
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include "k3-am62a.dtsi"
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0: cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
};
cpu0: cpu@0 {
compatible = "arm,cortex-a53";
reg = <0x000>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53";
reg = <0x001>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53";
reg = <0x002>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53";
reg = <0x003>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
};
};
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-size = <0x40000>;
cache-line-size = <64>;
cache-sets = <512>;
};
};

8
arch/arm/dts/k3-am64-mcu.dtsi
View File

@@ -97,4 +97,12 @@
clocks = <&k3_clks 79 0>;
clock-names = "gpio";
};
mcu_pmx0: pinctrl@4084000 {
compatible = "pinctrl-single";
reg = <0x00 0x4084000 0x00 0x84>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
};

92
arch/arm/dts/nuvoton-common-npcm8xx.dtsi
View File

@@ -4,6 +4,7 @@
#include <dt-bindings/clock/nuvoton,npcm845-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
/ {
#address-cells = <2>;
@@ -60,6 +61,70 @@
reg = <0x0 0xf0801000 0x0 0x1000>;
};
sdhci0: sdhci@f0842000 {
compatible = "nuvoton,npcm845-sdhci";
reg = <0x0 0xf0842000 0x0 0x100>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_AHB>;
clock-names = "clk_mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc8_pins
&mmc_pins>;
status = "disabled";
};
fiu0: spi@fb000000 {
compatible = "nuvoton,npcm845-fiu";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0xfb000000 0x0 0x1000>,
<0x0 0x80000000 0x0 0x10000000>;
reg-names = "control", "memory";
clocks = <&clk NPCM8XX_CLK_SPI0>;
clock-names = "clk_ahb";
status = "disabled";
};
fiu1: spi@fb002000 {
compatible = "nuvoton,npcm845-fiu";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0xfb002000 0x0 0x1000>,
<0x0 0x90000000 0x0 0x4000000>;
reg-names = "control", "memory";
clocks = <&clk NPCM8XX_CLK_SPI1>;
clock-names = "clk_spi1";
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins>;
status = "disabled";
};
fiu3: spi@c0000000 {
compatible = "nuvoton,npcm845-fiu";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0xc0000000 0x0 0x1000>,
<0x0 0xA0000000 0x0 0x20000000>;
reg-names = "control", "memory";
clocks = <&clk NPCM8XX_CLK_SPI3>;
clock-names = "clk_spi3";
pinctrl-names = "default";
pinctrl-0 = <&spi3_pins>;
status = "disabled";
};
fiux: spi@fb001000 {
compatible = "nuvoton,npcm845-fiu";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0xfb001000 0x0 0x1000>,
<0x0 0xf8000000 0x0 0x2000000>;
reg-names = "control", "memory";
clocks = <&clk NPCM8XX_CLK_SPIX>;
clock-names = "clk_ahb";
status = "disabled";
};
apb {
#address-cells = <1>;
#size-cells = <1>;
@@ -68,6 +133,19 @@
ranges = <0x0 0x0 0xf0000000 0x00300000>,
<0xfff00000 0x0 0xfff00000 0x00016000>;
spi1: spi@201000 {
compatible = "nuvoton,npcm845-pspi";
reg = <0x201000 0x1000>;
pinctrl-names = "default";
pinctrl-0 = <&pspi_pins>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_APB5>;
clock-names = "clk_apb5";
status = "disabled";
};
timer0: timer@8000 {
compatible = "nuvoton,npcm845-timer";
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
@@ -165,6 +243,20 @@
clocks = <&clk NPCM8XX_CLK_REFCLK>;
syscon = <&gcr>;
};
i2c0: i2c@80000 {
compatible = "nuvoton,npcm845-i2c";
reg = <0x80000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk NPCM8XX_CLK_APB2>;
clock-frequency = <100000>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&smb0_pins>;
syscon = <&gcr>;
status = "disabled";
};
};
};
};

16
arch/arm/dts/nuvoton-npcm7xx-u-boot.dtsi
View File

@@ -220,7 +220,7 @@
clocks = <&clk NPCM7XX_CLK_APB1>;
};
gpio_0: gpio0@10000 {
compatible = "nuvoton,npcm-gpio";
compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio";
reg = <0x10000 0xB0>;
#gpio-cells = <2>;
gpio-controller;
@@ -228,7 +228,7 @@
};
gpio_1: gpio1@11000 {
compatible = "nuvoton,npcm-gpio";
compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio";
reg = <0x11000 0xB0>;
#gpio-cells = <2>;
gpio-controller;
@@ -236,14 +236,14 @@
};
gpio_2: gpio2@12000 {
compatible = "nuvoton,npcm-gpio";
compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio";
reg = <0x12000 0xB0>;
#gpio-cells = <2>;
gpio-controller;
gpio-bank-name = "gpio2";
};
gpio_3: gpio3@13000 {
compatible = "nuvoton,npcm-gpio";
compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio";
reg = <0x13000 0xB0>;
#gpio-cells = <2>;
gpio-controller;
@@ -251,7 +251,7 @@
};
gpio_4: gpio4@14000 {
compatible = "nuvoton,npcm-gpio";
compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio";
reg = <0x14000 0xB0>;
#gpio-cells = <2>;
gpio-controller;
@@ -259,7 +259,7 @@
};
gpio_5: gpio5@15000 {
compatible = "nuvoton,npcm-gpio";
compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio";
reg = <0x15000 0xB0>;
#gpio-cells = <2>;
gpio-controller;
@@ -267,14 +267,14 @@
};
gpio_6: gpio6@16000 {
compatible = "nuvoton,npcm-gpio";
compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio";
reg = <0x16000 0xB0>;
#gpio-cells = <2>;
gpio-controller;
gpio-bank-name = "gpio6";
};
gpio_7: gpio7@17000 {
compatible = "nuvoton,npcm-gpio";
compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio";
reg = <0x17000 0xB0>;
#gpio-cells = <2>;
gpio-controller;

129
arch/arm/dts/nuvoton-npcm845-evb.dts
View File

@@ -3,6 +3,7 @@
/dts-v1/;
#include "nuvoton-npcm845.dtsi"
#include "nuvoton-npcm845-pincfg.dtsi"
/ {
model = "Nuvoton npcm845 Development Board (Device Tree)";
@@ -10,6 +11,15 @@
aliases {
serial0 = &serial0;
i2c0 = &i2c0;
spi0 = &fiu0;
spi1 = &fiu1;
spi3 = &fiu3;
spi4 = &fiux;
spi5 = &spi1;
usb0 = &udc0;
usb1 = &ehci1;
usb2 = &ehci2;
};
chosen {
@@ -19,6 +29,31 @@
memory {
reg = <0x0 0x0 0x0 0x40000000>;
};
vsbr2: vsbr2 {
compatible = "regulator-npcm845";
regulator-name = "vr2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vsbv8: vsbv8 {
compatible = "regulator-npcm845";
regulator-name = "v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vsbv5: vsbv5 {
compatible = "regulator-npcm845";
regulator-name = "v5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
&serial0 {
@@ -28,3 +63,97 @@
&watchdog1 {
status = "okay";
};
&fiu0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0cs1_pins>;
spi-nor@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
};
spi_flash@1 {
compatible = "jedec,spi-nor";
reg = <1>;
spi-max-frequency = <25000000>;
};
};
&fiu1 {
status = "okay";
spi-nor@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
};
};
&fiu3 {
pinctrl-0 = <&spi3_pins>, <&spi3quad_pins>;
status = "okay";
vqspi-supply = <&vsbv5>;
vqspi-microvolt = <3300000>;
spi-nor@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
};
};
&fiux {
nuvoton,spix-mode;
status = "okay";
};
&spi1 {
status = "okay";
};
&usbphy1 {
status = "okay";
};
&usbphy2 {
status = "okay";
};
&usbphy3 {
status = "okay";
};
&udc0 {
status = "okay";
phys = <&usbphy1 0>;
};
&sdhci0 {
bus-width = <0x8>;
status = "okay";
};
&ehci1 {
status = "okay";
phys = <&usbphy2 3>;
};
&ehci2 {
status = "okay";
phys = <&usbphy3 4>;
};
&i2c0 {
status = "okay";
};
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <
&gspi_pins
&vgadig_pins
&spix_pins
&r1_pins
&r1en_pins
&r1oen_pins
>;
};

2007
arch/arm/dts/nuvoton-npcm845-pincfg.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

832
arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi
View File

@@ -59,6 +59,174 @@
clocks = <&clk_refclk>;
};
ehci1: usb@f0828100 {
compatible = "nuvoton,npcm845-ehci";
reg = <0x0 0xf0828100 0x0 0x1000>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rstc2 NPCM8XX_RESET_USBH1>;
status = "disabled";
};
ehci2: usb@f082a100 {
compatible = "nuvoton,npcm845-ehci";
reg = <0x0 0xf082a100 0x0 0x1000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rstc4 NPCM8XX_RESET_USBH2>;
status = "disabled";
};
ohci1: usb@f0829000 {
compatible = "nuvoton,npcm845-ohci";
reg = <0x0 0xF0829000 0x0 0x1000>;
resets = <&rstc2 NPCM8XX_RESET_USBH1>;
status = "disabled";
};
ohci2: usb@f082b000 {
compatible = "nuvoton,npcm845-ohci";
reg = <0x0 0xF082B000 0x0 0x1000>;
resets = <&rstc4 NPCM8XX_RESET_USBH2>;
status = "disabled";
};
usbphy {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
syscon = <&gcr>;
usbphy1: usbphy@1 {
compatible = "nuvoton,npcm845-usb-phy";
#phy-cells = <1>;
reg = <1>;
resets = <&rstc3 NPCM8XX_RESET_USBPHY1>;
status = "disabled";
};
usbphy2: usbphy@2 {
compatible = "nuvoton,npcm845-usb-phy";
#phy-cells = <1>;
reg = <2>;
resets = <&rstc3 NPCM8XX_RESET_USBPHY2>;
status = "disabled";
};
usbphy3: usbphy@3 {
compatible = "nuvoton,npcm845-usb-phy";
#phy-cells = <1>;
reg = <3>;
resets = <&rstc3 NPCM8XX_RESET_USBPHY3>;
status = "disabled";
};
};
udc0:udc@f0830100 {
compatible = "nuvoton,npcm845-udc";
reg = <0x0 0xf0830100 0x0 0x100
0x0 0xfffb0000 0x0 0x800>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_SU>;
clock-names = "clk_usb_bridge";
resets = <&rstc3 NPCM8XX_RESET_UDC0>;
status = "disable";
};
udc1:udc@f0831100 {
compatible = "nuvoton,npcm845-udc";
reg = <0x0 0xf0831100 0x0 0x100
0x0 0xfffb0800 0x0 0x800>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_SU>;
clock-names = "clk_usb_bridge";
resets = <&rstc1 NPCM8XX_RESET_UDC1>;
status = "disable";
};
udc2:udc@f0832100 {
compatible = "nuvoton,npcm845-udc";
reg = <0x0 0xf0832100 0x0 0x100
0x0 0xfffb1000 0x0 0x800>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_SU>;
clock-names = "clk_usb_bridge";
resets = <&rstc1 NPCM8XX_RESET_UDC2>;
status = "disable";
};
udc3:udc@f0833100 {
compatible = "nuvoton,npcm845-udc";
reg = <0x0 0xf0833100 0x0 0x100
0x0 0xfffb1800 0x0 0x800>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_SU>;
clock-names = "clk_usb_bridge";
resets = <&rstc1 NPCM8XX_RESET_UDC3>;
status = "disable";
};
udc4:udc@f0834100 {
compatible = "nuvoton,npcm845-udc";
reg = <0x0 0xf0834100 0x0 0x100
0x0 0xfffb2000 0x0 0x800>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_SU>;
clock-names = "clk_usb_bridge";
resets = <&rstc1 NPCM8XX_RESET_UDC4>;
status = "disable";
};
udc5:udc@f0835100 {
compatible = "nuvoton,npcm845-udc";
reg = <0x0 0xf0835100 0x0 0x100
0x0 0xfffb2800 0x0 0x800>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_SU>;
clock-names = "clk_usb_bridge";
resets = <&rstc1 NPCM8XX_RESET_UDC5>;
status = "disable";
};
udc6:udc@f0836100 {
compatible = "nuvoton,npcm845-udc";
reg = <0x0 0xf0836100 0x0 0x100
0x0 0xfffb3000 0x0 0x800>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_SU>;
clock-names = "clk_usb_bridge";
resets = <&rstc1 NPCM8XX_RESET_UDC6>;
status = "disable";
};
udc7:udc@f0837100 {
compatible = "nuvoton,npcm845-udc";
reg = <0x0 0xf0837100 0x0 0x100
0x0 0xfffb3800 0x0 0x800>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_SU>;
clock-names = "clk_usb_bridge";
resets = <&rstc3 NPCM8XX_RESET_UDC7>;
status = "disable";
};
udc8:udc@f0838100 {
compatible = "nuvoton,npcm845-udc";
reg = <0x0 0xf0838100 0x0 0x100
0x0 0xfffb4000 0x0 0x800>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_SU>;
clock-names = "clk_usb_bridge";
resets = <&rstc3 NPCM8XX_RESET_UDC8>;
status = "disable";
};
udc9:udc@f0839100 {
compatible = "nuvoton,npcm845-udc";
reg = <0x0 0xf0839100 0x0 0x100
0x0 0xfffb4800 0x0 0x800>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_SU>;
clock-names = "clk_usb_bridge";
resets = <&rstc3 NPCM8XX_RESET_UDC9>;
status = "disable";
};
apb {
serial0: serial@0 {
compatible = "nuvoton,npcm845-uart";
@@ -69,7 +237,7 @@
};
gpio0: gpio0@10000 {
compatible = "nuvoton,npcm-gpio";
compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
reg = <0x10000 0xB0>;
#gpio-cells = <2>;
gpio-controller;
@@ -77,7 +245,7 @@
};
gpio1: gpio1@11000 {
compatible = "nuvoton,npcm-gpio";
compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
reg = <0x11000 0xB0>;
#gpio-cells = <2>;
gpio-controller;
@@ -85,7 +253,7 @@
};
gpio2: gpio2@12000 {
compatible = "nuvoton,npcm-gpio";
compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
reg = <0x12000 0xB0>;
#gpio-cells = <2>;
gpio-controller;
@@ -93,7 +261,7 @@
};
gpio3: gpio3@13000 {
compatible = "nuvoton,npcm-gpio";
compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
reg = <0x13000 0xB0>;
#gpio-cells = <2>;
gpio-controller;
@@ -101,7 +269,7 @@
};
gpio4: gpio4@14000 {
compatible = "nuvoton,npcm-gpio";
compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
reg = <0x14000 0xB0>;
#gpio-cells = <2>;
gpio-controller;
@@ -109,7 +277,7 @@
};
gpio5: gpio5@15000 {
compatible = "nuvoton,npcm-gpio";
compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
reg = <0x15000 0xB0>;
#gpio-cells = <2>;
gpio-controller;
@@ -117,7 +285,7 @@
};
gpio6: gpio6@16000 {
compatible = "nuvoton,npcm-gpio";
compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
reg = <0x16000 0xB0>;
#gpio-cells = <2>;
gpio-controller;
@@ -125,7 +293,7 @@
};
gpio7: gpio7@17000 {
compatible = "nuvoton,npcm-gpio";
compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
reg = <0x17000 0xB0>;
#gpio-cells = <2>;
gpio-controller;
@@ -133,4 +301,652 @@
};
};
};
pinctrl: pinctrl@f0800000 {
compatible = "nuvoton,npcm845-pinctrl", "syscon", "simple-mfd";
reg = <0x0 0xf0010000 0x0 0x8000>;
syscon-gcr = <&gcr>;
syscon-rst = <&rstc>;
status = "okay";
iox1_pins: iox1-pins {
groups = "iox1";
function = "iox1";
};
iox2_pins: iox2-pins {
groups = "iox2";
function = "iox2";
};
smb1d_pins: smb1d-pins {
groups = "smb1d";
function = "smb1d";
};
smb2d_pins: smb2d-pins {
groups = "smb2d";
function = "smb2d";
};
lkgpo1_pins: lkgpo1-pins {
groups = "lkgpo1";
function = "lkgpo1";
};
lkgpo2_pins: lkgpo2-pins {
groups = "lkgpo2";
function = "lkgpo2";
};
ioxh_pins: ioxh-pins {
groups = "ioxh";
function = "ioxh";
};
gspi_pins: gspi-pins {
groups = "gspi";
function = "gspi";
};
smb5b_pins: smb5b-pins {
groups = "smb5b";
function = "smb5b";
};
smb5c_pins: smb5c-pins {
groups = "smb5c";
function = "smb5c";
};
lkgpo0_pins: lkgpo0-pins {
groups = "lkgpo0";
function = "lkgpo0";
};
pspi_pins: pspi-pins {
groups = "pspi";
function = "pspi";
};
vgadig_pins: vgadig-pins {
groups = "vgadig";
function = "vgadig";
};
jm1_pins: jm1-pins {
groups = "jm1";
function = "jm1";
};
jm2_pins: jm2-pins {
groups = "jm2";
function = "jm2";
};
smb4b_pins: smb4b-pins {
groups = "smb4b";
function = "smb4b";
};
smb4c_pins: smb4c-pins {
groups = "smb4c";
function = "smb4c";
};
smb15_pins: smb15-pins {
groups = "smb15";
function = "smb15";
};
smb16_pins: smb16-pins {
groups = "smb16";
function = "smb16";
};
smb17_pins: smb17-pins {
groups = "smb17";
function = "smb17";
};
smb18_pins: smb18-pins {
groups = "smb18";
function = "smb18";
};
smb19_pins: smb19-pins {
groups = "smb19";
function = "smb19";
};
smb20_pins: smb20-pins {
groups = "smb20";
function = "smb20";
};
smb21_pins: smb21-pins {
groups = "smb21";
function = "smb21";
};
smb22_pins: smb22-pins {
groups = "smb22";
function = "smb22";
};
smb23_pins: smb23-pins {
groups = "smb23";
function = "smb23";
};
smb4d_pins: smb4d-pins {
groups = "smb4d";
function = "smb4d";
};
smb14_pins: smb14-pins {
groups = "smb14";
function = "smb14";
};
smb5_pins: smb5-pins {
groups = "smb5";
function = "smb5";
};
smb4_pins: smb4-pins {
groups = "smb4";
function = "smb4";
};
smb3_pins: smb3-pins {
groups = "smb3";
function = "smb3";
};
spi0cs1_pins: spi0cs1-pins {
groups = "spi0cs1";
function = "spi0cs1";
};
spi0cs2_pins: spi0cs2-pins {
groups = "spi0cs2";
function = "spi0cs2";
};
spi0cs3_pins: spi0cs3-pins {
groups = "spi0cs3";
function = "spi0cs3";
};
smb3c_pins: smb3c-pins {
groups = "smb3c";
function = "smb3c";
};
smb3b_pins: smb3b-pins {
groups = "smb3b";
function = "smb3b";
};
hsi1a_pins: hsi1a-pins {
groups = "hsi1a";
function = "hsi1a";
};
hsi1b_pins: hsi1b-pins {
groups = "hsi1b";
function = "hsi1b";
};
hsi1c_pins: hsi1c-pins {
groups = "hsi1c";
function = "hsi1c";
};
hsi2a_pins: hsi2a-pins {
groups = "hsi2a";
function = "hsi2a";
};
hsi2b_pins: hsi2b-pins {
groups = "hsi2b";
function = "hsi2b";
};
hsi2c_pins: hsi2c-pins {
groups = "hsi2c";
function = "hsi2c";
};
bmcuart0a_pins: bmcuart0a-pins {
groups = "bmcuart0a";
function = "bmcuart0a";
};
bmcuart0b_pins: bmcuart0b-pins {
groups = "bmcuart0b";
function = "bmcuart0b";
};
bmcuart1_pins: bmcuart1-pins {
groups = "bmcuart1";
function = "bmcuart1";
};
bu4_pins: bu4-pins {
groups = "bu4";
function = "bu4";
};
bu5_pins: bu5-pins {
groups = "bu5";
function = "bu5";
};
bu6_pins: bu6-pins {
groups = "bu6";
function = "bu6";
};
r1err_pins: r1err-pins {
groups = "r1err";
function = "r1err";
};
r1md_pins: r1md-pins {
groups = "r1md";
function = "r1md";
};
r1oen_pins: r1oen-pins {
groups = "r1oen";
function = "r1oen";
};
r1en_pins: r1en-pins {
groups = "r1en";
function = "r1en";
};
r2oen_pins: r2oen-pins {
groups = "r2oen";
function = "r2oen";
};
r2en_pins: r2en-pins {
groups = "r2en";
function = "r2en";
};
rmii3_pins: rmii3_pins {
groups = "rmii3";
function = "rmii3";
};
r3oen_pins: r3oen-pins {
groups = "r3oen";
function = "r3oen";
};
r3en_pins: r3en-pins {
groups = "r3en";
function = "r3en";
};
smb3d_pins: smb3d-pins {
groups = "smb3d";
function = "smb3d";
};
fanin0_pins: fanin0-pins {
groups = "fanin0";
function = "fanin0";
};
fanin1_pins: fanin1-pins {
groups = "fanin1";
function = "fanin1";
};
fanin2_pins: fanin2-pins {
groups = "fanin2";
function = "fanin2";
};
fanin3_pins: fanin3-pins {
groups = "fanin3";
function = "fanin3";
};
fanin4_pins: fanin4-pins {
groups = "fanin4";
function = "fanin4";
};
fanin5_pins: fanin5-pins {
groups = "fanin5";
function = "fanin5";
};
fanin6_pins: fanin6-pins {
groups = "fanin6";
function = "fanin6";
};
fanin7_pins: fanin7-pins {
groups = "fanin7";
function = "fanin7";
};
fanin8_pins: fanin8-pins {
groups = "fanin8";
function = "fanin8";
};
fanin9_pins: fanin9-pins {
groups = "fanin9";
function = "fanin9";
};
fanin10_pins: fanin10-pins {
groups = "fanin10";
function = "fanin10";
};
fanin11_pins: fanin11-pins {
groups = "fanin11";
function = "fanin11";
};
fanin12_pins: fanin12-pins {
groups = "fanin12";
function = "fanin12";
};
fanin13_pins: fanin13-pins {
groups = "fanin13";
function = "fanin13";
};
fanin14_pins: fanin14-pins {
groups = "fanin14";
function = "fanin14";
};
fanin15_pins: fanin15-pins {
groups = "fanin15";
function = "fanin15";
};
pwm0_pins: pwm0-pins {
groups = "pwm0";
function = "pwm0";
};
pwm1_pins: pwm1-pins {
groups = "pwm1";
function = "pwm1";
};
pwm2_pins: pwm2-pins {
groups = "pwm2";
function = "pwm2";
};
pwm3_pins: pwm3-pins {
groups = "pwm3";
function = "pwm3";
};
r2_pins: r2-pins {
groups = "r2";
function = "r2";
};
r2err_pins: r2err-pins {
groups = "r2err";
function = "r2err";
};
r2md_pins: r2md-pins {
groups = "r2md";
function = "r2md";
};
r3rxer_pins: r3rxer_pins {
groups = "r3rxer";
function = "r3rxer";
};
ga20kbc_pins: ga20kbc-pins {
groups = "ga20kbc";
function = "ga20kbc";
};
smb5d_pins: smb5d-pins {
groups = "smb5d";
function = "smb5d";
};
lpc_pins: lpc-pins {
groups = "lpc";
function = "lpc";
};
espi_pins: espi-pins {
groups = "espi";
function = "espi";
};
rg1_pins: rg1-pins {
groups = "rg1";
function = "rg1";
};
rg1mdio_pins: rg1mdio-pins {
groups = "rg1mdio";
function = "rg1mdio";
};
rg2_pins: rg2-pins {
groups = "rg2";
function = "rg2";
};
ddr_pins: ddr-pins {
groups = "ddr";
function = "ddr";
};
i3c0_pins: i3c0-pins {
groups = "i3c0";
function = "i3c0";
};
i3c1_pins: i3c1-pins {
groups = "i3c1";
function = "i3c1";
};
i3c2_pins: i3c2-pins {
groups = "i3c2";
function = "i3c2";
};
i3c3_pins: i3c3-pins {
groups = "i3c3";
function = "i3c3";
};
i3c4_pins: i3c4-pins {
groups = "i3c4";
function = "i3c4";
};
i3c5_pins: i3c5-pins {
groups = "i3c5";
function = "i3c5";
};
smb0_pins: smb0-pins {
groups = "smb0";
function = "smb0";
};
smb1_pins: smb1-pins {
groups = "smb1";
function = "smb1";
};
smb2_pins: smb2-pins {
groups = "smb2";
function = "smb2";
};
smb2c_pins: smb2c-pins {
groups = "smb2c";
function = "smb2c";
};
smb2b_pins: smb2b-pins {
groups = "smb2b";
function = "smb2b";
};
smb1c_pins: smb1c-pins {
groups = "smb1c";
function = "smb1c";
};
smb1b_pins: smb1b-pins {
groups = "smb1b";
function = "smb1b";
};
smb8_pins: smb8-pins {
groups = "smb8";
function = "smb8";
};
smb9_pins: smb9-pins {
groups = "smb9";
function = "smb9";
};
smb10_pins: smb10-pins {
groups = "smb10";
function = "smb10";
};
smb11_pins: smb11-pins {
groups = "smb11";
function = "smb11";
};
sd1_pins: sd1-pins {
groups = "sd1";
function = "sd1";
};
sd1pwr_pins: sd1pwr-pins {
groups = "sd1pwr";
function = "sd1pwr";
};
pwm4_pins: pwm4-pins {
groups = "pwm4";
function = "pwm4";
};
pwm5_pins: pwm5-pins {
groups = "pwm5";
function = "pwm5";
};
pwm6_pins: pwm6-pins {
groups = "pwm6";
function = "pwm6";
};
pwm7_pins: pwm7-pins {
groups = "pwm7";
function = "pwm7";
};
pwm8_pins: pwm8-pins {
groups = "pwm8";
function = "pwm8";
};
pwm9_pins: pwm9-pins {
groups = "pwm9";
function = "pwm9";
};
pwm10_pins: pwm10-pins {
groups = "pwm10";
function = "pwm10";
};
pwm11_pins: pwm11-pins {
groups = "pwm11";
function = "pwm11";
};
mmc8_pins: mmc8-pins {
groups = "mmc8";
function = "mmc8";
};
mmc_pins: mmc-pins {
groups = "mmc";
function = "mmc";
};
mmcwp_pins: mmcwp-pins {
groups = "mmcwp";
function = "mmcwp";
};
mmccd_pins: mmccd-pins {
groups = "mmccd";
function = "mmccd";
};
mmcrst_pins: mmcrst-pins {
groups = "mmcrst";
function = "mmcrst";
};
clkout_pins: clkout-pins {
groups = "clkout";
function = "clkout";
};
serirq_pins: serirq-pins {
groups = "serirq";
function = "serirq";
};
scipme_pins: scipme-pins {
groups = "scipme";
function = "scipme";
};
sci_pins: sci-pins {
groups = "sci";
function = "sci";
};
smb6_pins: smb6-pins {
groups = "smb6";
function = "smb6";
};
smb7_pins: smb7-pins {
groups = "smb7";
function = "smb7";
};
spi1_pins: spi1-pins {
groups = "spi1";
function = "spi1";
};
spi1d23_pins: spi1d23-pins {
groups = "spi1d23";
function = "spi1d23";
};
faninx_pins: faninx-pins {
groups = "faninx";
function = "faninx";
};
r1_pins: r1-pins {
groups = "r1";
function = "r1";
};
spi3_pins: spi3-pins {
groups = "spi3";
function = "spi3";
};
spi3cs1_pins: spi3cs1-pins {
groups = "spi3cs1";
function = "spi3cs1";
};
spi3quad_pins: spi3quad-pins {
groups = "spi3quad";
function = "spi3quad";
};
spi3cs2_pins: spi3cs2-pins {
groups = "spi3cs2";
function = "spi3cs2";
};
spi3cs3_pins: spi3cs3-pins {
groups = "spi3cs3";
function = "spi3cs3";
};
nprd_smi_pins: nprd-smi-pins {
groups = "nprd_smi";
function = "nprd_smi";
};
smb0b_pins: smb0b-pins {
groups = "smb0b";
function = "smb0b";
};
smb0c_pins: smb0c-pins {
groups = "smb0c";
function = "smb0c";
};
smb0den_pins: smb0den-pins {
groups = "smb0den";
function = "smb0den";
};
smb0d_pins: smb0d-pins {
groups = "smb0d";
function = "smb0d";
};
rg2mdio_pins: rg2mdio-pins {
groups = "rg2mdio";
function = "rg2mdio";
};
rg2refck_pins: rg2refck-pins {
groups = "rg2refck";
function = "rg2refck";
};
wdog1_pins: wdog1-pins {
groups = "wdog1";
function = "wdog1";
};
wdog2_pins: wdog2-pins {
groups = "wdog2";
function = "wdog2";
};
smb12_pins: smb12-pins {
groups = "smb12";
function = "smb12";
};
smb13_pins: smb13-pins {
groups = "smb13";
function = "smb13";
};
spix_pins: spix-pins {
groups = "spix";
function = "spix";
};
spixcs1_pins: spixcs1-pins {
groups = "spixcs1";
function = "spixcs1";
};
clkreq_pins: clkreq-pins {
groups = "clkreq";
function = "clkreq";
};
hgpio0_pins: hgpio0-pins {
groups = "hgpio0";
function = "hgpio0";
};
hgpio1_pins: hgpio1-pins {
groups = "hgpio1";
function = "hgpio1";
};
hgpio2_pins: hgpio2-pins {
groups = "hgpio2";
function = "hgpio2";
};
hgpio3_pins: hgpio3-pins {
groups = "hgpio3";
function = "hgpio3";
};
hgpio4_pins: hgpio4-pins {
groups = "hgpio4";
function = "hgpio4";
};
hgpio5_pins: hgpio5-pins {
groups = "hgpio5";
function = "hgpio5";
};
hgpio6_pins: hgpio6-pins {
groups = "hgpio6";
function = "hgpio6";
};
hgpio7_pins: hgpio7-pins {
groups = "hgpio7";
function = "hgpio7";
};
jtag2_pins: jtag2-pins {
groups = "jtag2";
function = "jtag2";
};
};
};

8
arch/arm/dts/omap4-u-boot.dtsi
View File

@@ -17,6 +17,14 @@
compatible = "simple-bus";
};
};
segment@80000 {
/* USB OTG */
target-module@2b000 {
compatible = "simple-bus";
};
};
};
&l4_per {

4
arch/arm/dts/rockchip-optee.dtsi
View File

@@ -32,8 +32,8 @@
arch = "arm";
os = "tee";
compression = "none";
load = <(CONFIG_SYS_SDRAM_BASE + 0x8400000)>;
entry = <(CONFIG_SYS_SDRAM_BASE + 0x8400000)>;
load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
blob-ext {
filename = "tee.bin";

6
arch/arm/dts/s5p4418-nanopi2.dts
View File

@@ -25,6 +25,7 @@
i2c0 = "/i2c@c00a4000";
i2c1 = "/i2c@c00a5000";
i2c2 = "/i2c@c00a6000";
serial0 = "/uart@c00a1000";
};
mmc0:mmc@c0062000 {
@@ -107,4 +108,9 @@
};
};
};
uart0:uart@c00a1000 {
skip-init;
status = "okay";
};
};

71
arch/arm/dts/s5p4418-pinctrl.dtsi
View File

@@ -132,4 +132,75 @@ pinctrl@C0010000 {
pin-pull = <2>;
pin-strength = <0>;
};
/* UART */
uart0_rx:uart0-rx {
pins = "gpiod-14";
pin-function = <1>;
pin-pull = <2>;
pin-strength = <0>;
};
uart0_tx:uart0-tx {
pins = "gpiod-18";
pin-function = <1>;
pin-pull = <2>;
pin-strength = <0>;
};
uart1_rx:uart1-rx {
pins = "gpiod-15";
pin-function = <2>;
pin-pull = <2>;
pin-strength = <0>;
};
uart1_tx:uart1-tx {
pins = "gpiod-19";
pin-function = <2>;
pin-pull = <2>;
pin-strength = <0>;
};
uart2_rx:uart2-rx {
pins = "gpiod-16";
pin-function = <1>;
pin-pull = <2>;
pin-strength = <0>;
};
uart2_tx:uart2-tx {
pins = "gpiod-20";
pin-function = <1>;
pin-pull = <2>;
pin-strength = <0>;
};
uart3_rx:uart3-rx {
pins = "gpiod-17";
pin-function = <1>;
pin-pull = <2>;
pin-strength = <0>;
};
uart3_tx:uart3-tx {
pins = "gpiod-21";
pin-function = <1>;
pin-pull = <2>;
pin-strength = <0>;
};
uart4_rx:uart4-rx {
pins = "gpiob-28";
pin-function = <3>;
pin-pull = <2>;
pin-strength = <0>;
};
uart4_tx:uart4-tx {
pins = "gpiob-29";
pin-function = <3>;
pin-pull = <2>;
pin-strength = <0>;
};
};

40
arch/arm/dts/s5p4418.dtsi
View File

@@ -167,4 +167,44 @@
reg = <0xc0010000 0xf000>;
u-boot,dm-pre-reloc;
};
uart0:uart@c00a1000 {
compatible = "nexell,s5p4418-pl011", "arm,primecell";
reg = <0xc00a1000 0x1000>;
pinctrl-names = "default";
pinctrl-0 = <&uart0_rx>, <&uart0_tx>;
status = "disabled";
};
uart1:uart@c00a0000 {
compatible = "nexell,s5p4418-pl011", "arm,primecell";
reg = <0xc00a0000 0x1000>;
pinctrl-names = "default";
pinctrl-0 = <&uart1_rx>, <&uart1_tx>;
status = "disabled";
};
uart2:uart@c00a2000 {
compatible = "nexell,s5p4418-pl011", "arm,primecell";
reg = <0xc00a2000 0x1000>;
pinctrl-names = "default";
pinctrl-0 = <&uart2_rx>, <&uart2_tx>;
status = "disabled";
};
uart3:uart@c00a3000 {
compatible = "nexell,s5p4418-pl011", "arm,primecell";
reg = <0xc00a3000 0x1000>;
pinctrl-names = "default";
pinctrl-0 = <&uart3_rx>, <&uart3_tx>;
status = "disabled";
};
uart4:uart@c006d000 {
compatible = "nexell,s5p4418-pl011", "arm,primecell";
reg = <0xc006d000 0x1000>;
pinctrl-names = "default";
pinctrl-0 = <&uart4_rx>, <&uart4_tx>;
status = "disabled";
};
};

85
arch/arm/dts/sam9x60.dtsi
View File

@@ -69,6 +69,50 @@
#size-cells = <1>;
ranges;
usb1: usb@600000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00600000 0x100000>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 21>;
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
usb2: usb@700000 {
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00700000 0x100000>;
clocks = <&pmc PMC_TYPE_CORE 8>, <&pmc PMC_TYPE_PERIPHERAL 22>;
clock-names = "usb_clk", "ehci_clk";
assigned-clocks = <&pmc PMC_TYPE_CORE 8>;
assigned-clock-rates = <480000000>;
status = "disabled";
};
ebi: ebi@10000000 {
compatible = "microchip,sam9x60-ebi";
#address-cells = <2>;
#size-cells = <1>;
atmel,smc = <&smc>;
microchip,sfr = <&sfr>;
reg = <0x10000000 0x60000000>;
ranges = <0x0 0x0 0x10000000 0x10000000
0x1 0x0 0x20000000 0x10000000
0x2 0x0 0x30000000 0x10000000
0x3 0x0 0x40000000 0x10000000
0x4 0x0 0x50000000 0x10000000
0x5 0x0 0x60000000 0x10000000>;
clocks = <&pmc PMC_TYPE_CORE 11>;
status = "disabled";
nand_controller: nand-controller {
compatible = "microchip,sam9x60-nand-controller";
ecc-engine = <&pmecc>;
#address-cells = <2>;
#size-cells = <1>;
ranges;
status = "disabled";
};
};
sdhci0: sdhci-host@80000000 {
compatible = "microchip,sam9x60-sdhci";
reg = <0x80000000 0x300>;
@@ -82,6 +126,19 @@
pinctrl-0 = <&pinctrl_sdhci0>;
};
sdhci1: sdhci-host@90000000 {
compatible = "microchip,sam9x60-sdhci";
reg = <0x90000000 0x300>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>;
clock-names = "hclock", "multclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
assigned-clock-rates = <100000000>;
assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* ID_PLL_A_DIV */
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci1>;
};
apb {
compatible = "simple-bus";
#address-cells = <1>;
@@ -119,6 +176,11 @@
status = "disabled";
};
sfr: sfr@f8050000 {
compatible = "microchip,sam9x60-sfr", "syscon";
reg = <0xf8050000 0x100>;
};
dbgu: serial@fffff200 {
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
reg = <0xfffff200 0x200>;
@@ -180,6 +242,29 @@
(AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>; /* PA20 DAT3 periph A with pullup */
};
};
sdhci1 {
pinctrl_sdhci1: sdhci1 {
atmel,pins =
<AT91_PIOA 13 AT91_PERIPH_B (AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA13 CK periph B */
AT91_PIOA 12 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA12 CMD periph B with pullup */
AT91_PIOA 11 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA11 DAT0 periph B with pullup */
AT91_PIOA 2 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA2 DAT1 periph B with pullup */
AT91_PIOA 3 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA3 DAT2 periph B with pullup */
AT91_PIOA 4 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>; /* PA4 DAT3 periph B with pullup */
};
};
};
pmecc: ecc-engine@ffffe000 {
compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc";
reg = <0xffffe000 0x300>,
<0xffffe600 0x100>;
};
smc: smc@ffffea00 {
compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon";
reg = <0xffffea00 0x100>;
};
pioA: gpio@fffff400 {

124
arch/arm/dts/sam9x60ek.dts
View File

@@ -80,6 +80,44 @@
};
pinctrl {
nand {
pinctrl_nand_oe_we: nand-oe-we-0 {
atmel,pins =
<AT91_PIOD 0 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 1 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
};
pinctrl_nand_rb: nand-rb-0 {
atmel,pins =
<AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
pinctrl_nand_cs: nand-cs-0 {
atmel,pins =
<AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
};
ebi {
pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
atmel,pins =
<AT91_PIOD 6 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 7 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 8 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 9 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 10 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 11 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 12 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 13 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
};
pinctrl_ebi_addr_nand: ebi-addr-0 {
atmel,pins =
<AT91_PIOD 2 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 3 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
};
};
pinctrl_qspi: qspi {
atmel,pins =
<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE
@@ -101,6 +139,78 @@
<AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
usb1 {
pinctrl_usb_default: usb_default {
atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
AT91_PIOD 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
};
};
};
};
};
&ebi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>;
status = "okay";
nand_controller: nand-controller {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs &pinctrl_nand_rb>;
status = "okay";
nand@3 {
reg = <0x3 0x0 0x800000>;
rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
nand-on-flash-bbt;
label = "atmel_nand";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
at91bootstrap@0 {
label = "at91bootstrap";
reg = <0x0 0x40000>;
};
uboot@40000 {
label = "u-boot";
reg = <0x40000 0xc0000>;
};
ubootenvred@100000 {
label = "U-Boot Env Redundant";
reg = <0x100000 0x40000>;
};
ubootenv@140000 {
label = "U-Boot Env";
reg = <0x140000 0x40000>;
};
dtb@180000 {
label = "device tree";
reg = <0x180000 0x80000>;
};
kernel@200000 {
label = "kernel";
reg = <0x200000 0x600000>;
};
rootfs@800000 {
label = "rootfs";
reg = <0x800000 0x1f800000>;
};
};
};
};
@@ -110,3 +220,17 @@
phy-mode = "rmii";
status = "okay";
};
&usb1 {
num-ports = <3>;
atmel,vbus-gpio = <0
&pioD 15 GPIO_ACTIVE_HIGH
&pioD 16 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_default>;
status = "okay";
};
&usb2 {
status = "okay";
};

1
arch/arm/dts/sama5d2.dtsi
View File

@@ -84,7 +84,6 @@
reg = <0xf0014000 0x160>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
u-boot,dm-pre-reloc;
main: mainck {

27
arch/arm/dts/sama7g5.dtsi
View File

@@ -15,6 +15,7 @@
#include <dt-bindings/clk/at91.h>
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mfd/at91-usart.h>
/ {
model = "Microchip SAMA7G5 family SoC";
@@ -195,11 +196,11 @@
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
};
pmc: pmc@e0018000 {
@@ -211,6 +212,13 @@
clock-names = "td_slck", "md_slck", "main_xtal", "main_rc";
};
reset_controller: reset-controller@e001d000 {
compatible = "microchip,sama7g5-rstc";
reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>;
#reset-cells = <1>;
clocks = <&clk32k 0>;
};
shdwc: shdwc@e001d010 {
compatible = "microchip,sama7g5-shdwc", "syscon";
reg = <0xe001d010 0x10>;
@@ -229,13 +237,6 @@
clocks = <&clk32k 0>;
};
reset_controller: rstc@e001d000 {
compatible = "microchip,sama7g5-rstc", "microchip,sam9x60-rstc";
reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>;
#reset-cells = <1>;
clocks = <&clk32k 0>;
};
clk32k: clock-controller@e001d050 {
compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc";
reg = <0xe001d050 0x4>;
@@ -620,6 +621,7 @@
uart0: serial@200 {
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
clock-names = "usart";
@@ -668,6 +670,7 @@
uart3: serial@200 {
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
clock-names = "usart";
@@ -711,6 +714,7 @@
uart4: serial@200 {
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
clock-names = "usart";
@@ -736,6 +740,7 @@
uart7: serial@200 {
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
clock-names = "usart";
@@ -884,9 +889,9 @@
#address-cells = <1>;
#size-cells = <0>;
atmel,fifo-size = <32>;
dmas = <&dma0 AT91_XDMAC_DT_PERID(27)>,
<&dma0 AT91_XDMAC_DT_PERID(28)>;
dma-names = "rx", "tx";
dmas = <&dma0 AT91_XDMAC_DT_PERID(28)>,
<&dma0 AT91_XDMAC_DT_PERID(27)>;
dma-names = "tx", "rx";
status = "disabled";
};
};

4
arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
View File

@@ -20,10 +20,8 @@
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
active_clk_edges;
chipselect_num = <1>;
spi-flash@0 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";

2
arch/arm/dts/synquacer-sc2a11-developerbox.dts
View File

@@ -18,7 +18,7 @@
compatible = "gpio-keys";
interrupt-parent = <&exiu>;
power {
power-button {
label = "Power Button";
linux,code = <KEY_POWER>;
interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_FALLING>;

71
arch/arm/dts/synquacer-sc2a11.dtsi
View File

@@ -41,168 +41,168 @@
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x1>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x100>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x101>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU4: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x200>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU5: cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x201>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU6: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x300>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU7: cpu@301 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x301>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU8: cpu@400 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x400>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU9: cpu@401 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x401>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU10: cpu@500 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x500>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU11: cpu@501 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x501>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU12: cpu@600 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x600>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU13: cpu@601 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x601>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU14: cpu@700 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x700>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU15: cpu@701 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x701>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU16: cpu@800 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x800>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU17: cpu@801 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x801>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU18: cpu@900 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x900>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU19: cpu@901 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x901>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU20: cpu@a00 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0xa00>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU21: cpu@a01 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0xa01>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU22: cpu@b00 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0xb00>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU23: cpu@b01 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0xb01>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -309,7 +309,7 @@
};
idle-states {
entry-method = "arm,psci";
entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
@@ -344,7 +344,7 @@
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
its: gic-its@30020000 {
its: msi-controller@30020000 {
compatible = "arm,gic-v3-its";
reg = <0x0 0x30020000 0x0 0x20000>;
#msi-cells = <1>;
@@ -361,16 +361,16 @@
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; // HYP
};
mmio-timer@2a810000 {
timer@2a810000 {
compatible = "arm,armv7-timer-mem";
reg = <0x0 0x2a810000 0x0 0x10000>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
frame@2a830000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x2a810000 0x30000>;
frame@20000 {
frame-number = <0>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x2a830000 0x0 0x10000>;
reg = <0x20000 0x10000>;
};
};
@@ -398,7 +398,7 @@
clock-output-names = "apb_pclk";
};
soc_uart0: uart@2a400000 {
soc_uart0: serial@2a400000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x2a400000 0x0 0x1000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
@@ -406,7 +406,7 @@
clock-names = "uartclk", "apb_pclk";
};
fuart: uart@51040000 {
fuart: serial@51040000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x51040000 0x0 0x1000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
@@ -497,7 +497,6 @@
gpio-controller;
#gpio-cells = <2>;
clocks = <&clk_apb>;
base = <0>;
};
exiu: interrupt-controller@510c0000 {
@@ -523,7 +522,7 @@
clock-output-names = "sd_sd4clk";
};
sdhci: sdhci@52300000 {
sdhci: mmc@52300000 {
compatible = "socionext,synquacer-sdhci", "fujitsu,mb86s70-sdhci-3.0";
reg = <0 0x52300000 0x0 0x1000>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,

4
arch/arm/dts/uniphier-v7-u-boot.dtsi
View File

@@ -2,6 +2,10 @@
soc {
u-boot,dm-pre-reloc;
timer@60000200 {
u-boot,dm-pre-reloc;
};
serial@54006800 {
u-boot,dm-pre-reloc;
};

2
arch/arm/include/asm/arch-am33xx/clock.h
View File

@@ -13,7 +13,7 @@
#include <asm/arch/clocks_am33xx.h>
#include <asm/arch/hardware.h>
#if defined(CONFIG_TI816X) || defined(CONFIG_TI814X)
#if defined(CONFIG_TI816X)
#include <asm/arch/clock_ti81xx.h>
#endif

36
arch/arm/include/asm/arch-am33xx/clock_ti81xx.h
View File

@@ -44,9 +44,7 @@ struct cm_alwon {
unsigned int mmu_clkstctrl;
unsigned int mmucfg_clkstctrl;
unsigned int ocmc0clkstctrl;
#if defined(CONFIG_TI814X)
unsigned int vcpclkstctrl;
#elif defined(CONFIG_TI816X)
#if defined(CONFIG_TI816X)
unsigned int ocmc1clkstctrl;
#endif
unsigned int mpuclkstctrl;
@@ -67,16 +65,7 @@ struct cm_alwon {
unsigned int gpio1clkctrl;
unsigned int i2c0clkctrl;
unsigned int i2c1clkctrl;
#if defined(CONFIG_TI814X)
unsigned int mcasp345clkctrl;
unsigned int atlclkctrl;
unsigned int mlbclkctrl;
unsigned int pataclkctrl;
unsigned int resv1[1];
unsigned int uart3clkctrl;
unsigned int uart4clkctrl;
unsigned int uart5clkctrl;
#elif defined(CONFIG_TI816X)
#if defined(CONFIG_TI816X)
unsigned int resv1[1];
unsigned int timer1clkctrl;
unsigned int timer2clkctrl;
@@ -93,16 +82,12 @@ struct cm_alwon {
unsigned int mmudataclkctrl;
unsigned int resv2[2];
unsigned int mmucfgclkctrl;
#if defined(CONFIG_TI814X)
unsigned int resv3[2];
#elif defined(CONFIG_TI816X)
#if defined(CONFIG_TI816X)
unsigned int resv3[1];
unsigned int sdioclkctrl;
#endif
unsigned int ocmc0clkctrl;
#if defined(CONFIG_TI814X)
unsigned int vcpclkctrl;
#elif defined(CONFIG_TI816X)
#if defined(CONFIG_TI816X)
unsigned int ocmc1clkctrl;
#endif
unsigned int resv4[2];
@@ -112,9 +97,7 @@ struct cm_alwon {
unsigned int ethernet0clkctrl;
unsigned int ethernet1clkctrl;
unsigned int mpuclkctrl;
#if defined(CONFIG_TI814X)
unsigned int debugssclkctrl;
#elif defined(CONFIG_TI816X)
#if defined(CONFIG_TI816X)
unsigned int resv6[1];
#endif
unsigned int l3clkctrl;
@@ -126,14 +109,7 @@ struct cm_alwon {
unsigned int tptc1clkctrl;
unsigned int tptc2clkctrl;
unsigned int tptc3clkctrl;
#if defined(CONFIG_TI814X)
unsigned int resv6[4];
unsigned int dcan01clkctrl;
unsigned int mmchs0clkctrl;
unsigned int mmchs1clkctrl;
unsigned int mmchs2clkctrl;
unsigned int custefuseclkctrl;
#elif defined(CONFIG_TI816X)
#if defined(CONFIG_TI816X)
unsigned int sr0clkctrl;
unsigned int sr1clkctrl;
#endif

2
arch/arm/include/asm/arch-am33xx/hardware.h
View File

@@ -16,8 +16,6 @@
#include <asm/arch/hardware_am33xx.h>
#elif defined(CONFIG_TI816X)
#include <asm/arch/hardware_ti816x.h>
#elif defined(CONFIG_TI814X)
#include <asm/arch/hardware_ti814x.h>
#elif defined(CONFIG_AM43XX)
#include <asm/arch/hardware_am43xx.h>
#endif

60
arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
View File

@@ -1,60 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* hardware_ti814x.h
*
* TI814x hardware specific header
*
* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
*/
#ifndef __AM33XX_HARDWARE_TI814X_H
#define __AM33XX_HARDWARE_TI814X_H
/* Module base addresses */
/* UART Base Address */
#define UART0_BASE 0x48020000
/* Watchdog Timer */
#define WDT_BASE 0x481C7000
/* Control Module Base Address */
#define CTRL_BASE 0x48140000
#define CTRL_DEVICE_BASE 0x48140600
/* PRCM Base Address */
#define PRCM_BASE 0x48180000
#define CM_PER 0x44E00000
#define CM_WKUP 0x44E00400
#define PRM_RSTCTRL (PRCM_BASE + 0x00A0)
#define PRM_RSTST (PRM_RSTCTRL + 8)
/* PLL Subsystem Base Address */
#define PLL_SUBSYS_BASE 0x481C5000
/* VTP Base address */
#define VTP0_CTRL_ADDR 0x48140E0C
#define VTP1_CTRL_ADDR 0x48140E10
/* DDR Base address */
#define DDR_PHY_CMD_ADDR 0x47C0C400
#define DDR_PHY_DATA_ADDR 0x47C0C4C8
#define DDR_PHY_CMD_ADDR2 0x47C0C800
#define DDR_PHY_DATA_ADDR2 0x47C0C8C8
#define DDR_DATA_REGS_NR 4
#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
/* CPSW Config space */
#define CPSW_MDIO_BASE 0x4A100800
/* RTC base address */
#define RTC_BASE 0x480C0000
/* OTG */
#define USB0_OTG_BASE 0x47401000
#define USB1_OTG_BASE 0x47401800
#endif /* __AM33XX_HARDWARE_TI814X_H */

5
arch/arm/include/asm/arch-am33xx/mmc_host_def.h
View File

@@ -24,10 +24,7 @@
#define OMAP_HSMMC1_BASE 0x48060000
#define OMAP_HSMMC2_BASE 0x481D8000
#if defined(CONFIG_TI814X)
#undef MMC_CLOCK_REFERENCE
#define MMC_CLOCK_REFERENCE 192 /* MHz */
#elif defined(CONFIG_TI816X)
#if defined(CONFIG_TI816X)
#undef MMC_CLOCK_REFERENCE
#define MMC_CLOCK_REFERENCE 48 /* MHz */
#endif

2
arch/arm/include/asm/arch-am33xx/mux.h
View File

@@ -20,8 +20,6 @@
#ifdef CONFIG_AM33XX
#include <asm/arch/mux_am33xx.h>
#elif defined(CONFIG_TI814X)
#include <asm/arch/mux_ti814x.h>
#elif defined(CONFIG_TI816X)
#include <asm/arch/mux_ti816x.h>
#elif defined(CONFIG_AM43XX)

311
arch/arm/include/asm/arch-am33xx/mux_ti814x.h
View File

@@ -1,311 +0,0 @@
/*
* mux_ti814x.h
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _MUX_TI814X_H_
#define _MUX_TI814X_H_
/* PAD Control Fields */
#define PINCNTL_RSV_MSK (0x3 << 18) /* Reserved bitmask */
#define PULLUP_EN (0x1 << 17) /* Pull UP Selection */
#define PULLUDEN (0x0 << 16) /* Pull up enabled */
#define PULLUDDIS (0x1 << 16) /* Pull up disabled */
#define MODE(val) val /* used for Readability */
#define MUX_CFG(value, offset) \
{ \
int tmp; \
tmp = __raw_readl(CTRL_BASE + offset); \
tmp &= PINCNTL_RSV_MSK; \
__raw_writel(tmp | value, (CTRL_BASE + offset));\
}
/*
* PAD CONTROL OFFSETS
* Field names corresponds to the pad signal name
*/
struct pad_signals {
int pincntl1;
int pincntl2;
int pincntl3;
int pincntl4;
int pincntl5;
int pincntl6;
int pincntl7;
int pincntl8;
int pincntl9;
int pincntl10;
int pincntl11;
int pincntl12;
int pincntl13;
int pincntl14;
int pincntl15;
int pincntl16;
int pincntl17;
int pincntl18;
int pincntl19;
int pincntl20;
int pincntl21;
int pincntl22;
int pincntl23;
int pincntl24;
int pincntl25;
int pincntl26;
int pincntl27;
int pincntl28;
int pincntl29;
int pincntl30;
int pincntl31;
int pincntl32;
int pincntl33;
int pincntl34;
int pincntl35;
int pincntl36;
int pincntl37;
int pincntl38;
int pincntl39;
int pincntl40;
int pincntl41;
int pincntl42;
int pincntl43;
int pincntl44;
int pincntl45;
int pincntl46;
int pincntl47;
int pincntl48;
int pincntl49;
int pincntl50;
int pincntl51;
int pincntl52;
int pincntl53;
int pincntl54;
int pincntl55;
int pincntl56;
int pincntl57;
int pincntl58;
int pincntl59;
int pincntl60;
int pincntl61;
int pincntl62;
int pincntl63;
int pincntl64;
int pincntl65;
int pincntl66;
int pincntl67;
int pincntl68;
int pincntl69;
int pincntl70;
int pincntl71;
int pincntl72;
int pincntl73;
int pincntl74;
int pincntl75;
int pincntl76;
int pincntl77;
int pincntl78;
int pincntl79;
int pincntl80;
int pincntl81;
int pincntl82;
int pincntl83;
int pincntl84;
int pincntl85;
int pincntl86;
int pincntl87;
int pincntl88;
int pincntl89;
int pincntl90;
int pincntl91;
int pincntl92;
int pincntl93;
int pincntl94;
int pincntl95;
int pincntl96;
int pincntl97;
int pincntl98;
int pincntl99;
int pincntl100;
int pincntl101;
int pincntl102;
int pincntl103;
int pincntl104;
int pincntl105;
int pincntl106;
int pincntl107;
int pincntl108;
int pincntl109;
int pincntl110;
int pincntl111;
int pincntl112;
int pincntl113;
int pincntl114;
int pincntl115;
int pincntl116;
int pincntl117;
int pincntl118;
int pincntl119;
int pincntl120;
int pincntl121;
int pincntl122;
int pincntl123;
int pincntl124;
int pincntl125;
int pincntl126;
int pincntl127;
int pincntl128;
int pincntl129;
int pincntl130;
int pincntl131;
int pincntl132;
int pincntl133;
int pincntl134;
int pincntl135;
int pincntl136;
int pincntl137;
int pincntl138;
int pincntl139;
int pincntl140;
int pincntl141;
int pincntl142;
int pincntl143;
int pincntl144;
int pincntl145;
int pincntl146;
int pincntl147;
int pincntl148;
int pincntl149;
int pincntl150;
int pincntl151;
int pincntl152;
int pincntl153;
int pincntl154;
int pincntl155;
int pincntl156;
int pincntl157;
int pincntl158;
int pincntl159;
int pincntl160;
int pincntl161;
int pincntl162;
int pincntl163;
int pincntl164;
int pincntl165;
int pincntl166;
int pincntl167;
int pincntl168;
int pincntl169;
int pincntl170;
int pincntl171;
int pincntl172;
int pincntl173;
int pincntl174;
int pincntl175;
int pincntl176;
int pincntl177;
int pincntl178;
int pincntl179;
int pincntl180;
int pincntl181;
int pincntl182;
int pincntl183;
int pincntl184;
int pincntl185;
int pincntl186;
int pincntl187;
int pincntl188;
int pincntl189;
int pincntl190;
int pincntl191;
int pincntl192;
int pincntl193;
int pincntl194;
int pincntl195;
int pincntl196;
int pincntl197;
int pincntl198;
int pincntl199;
int pincntl200;
int pincntl201;
int pincntl202;
int pincntl203;
int pincntl204;
int pincntl205;
int pincntl206;
int pincntl207;
int pincntl208;
int pincntl209;
int pincntl210;
int pincntl211;
int pincntl212;
int pincntl213;
int pincntl214;
int pincntl215;
int pincntl216;
int pincntl217;
int pincntl218;
int pincntl219;
int pincntl220;
int pincntl221;
int pincntl222;
int pincntl223;
int pincntl224;
int pincntl225;
int pincntl226;
int pincntl227;
int pincntl228;
int pincntl229;
int pincntl230;
int pincntl231;
int pincntl232;
int pincntl233;
int pincntl234;
int pincntl235;
int pincntl236;
int pincntl237;
int pincntl238;
int pincntl239;
int pincntl240;
int pincntl241;
int pincntl242;
int pincntl243;
int pincntl244;
int pincntl245;
int pincntl246;
int pincntl247;
int pincntl248;
int pincntl249;
int pincntl250;
int pincntl251;
int pincntl252;
int pincntl253;
int pincntl254;
int pincntl255;
int pincntl256;
int pincntl257;
int pincntl258;
int pincntl259;
int pincntl260;
int pincntl261;
int pincntl262;
int pincntl263;
int pincntl264;
int pincntl265;
int pincntl266;
int pincntl267;
int pincntl268;
int pincntl269;
int pincntl270;
};
#endif /* endif _MUX_TI814X_H_ */

2
arch/arm/include/asm/arch-am33xx/omap.h
View File

@@ -20,7 +20,7 @@
#define NON_SECURE_SRAM_START 0x402F0400
#define NON_SECURE_SRAM_END 0x40310000
#define NON_SECURE_SRAM_IMG_END 0x4030B800
#elif defined(CONFIG_TI816X) || defined(CONFIG_TI814X)
#elif defined(CONFIG_TI816X)
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40320000
#define NON_SECURE_SRAM_IMG_END 0x4031B800

16
arch/arm/include/asm/arch-am33xx/spl.h
View File

@@ -9,21 +9,7 @@
#define BOOT_DEVICE_NONE 0x00
#define BOOT_DEVICE_MMC2_2 0xFF
#if defined(CONFIG_TI814X)
#define BOOT_DEVICE_XIP 0x01
#define BOOT_DEVICE_XIPWAIT 0x02
#define BOOT_DEVICE_NAND 0x05
#define BOOT_DEVICE_NAND_I2C 0x06
#define BOOT_DEVICE_MMC2 0x08 /* ROM only supports 2nd instance. */
#define BOOT_DEVICE_MMC1 0x09
#define BOOT_DEVICE_SPI 0x15
#define BOOT_DEVICE_UART 0x41
#define BOOT_DEVICE_USBETH 0x44
#define BOOT_DEVICE_CPGMAC 0x46
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1
#elif defined(CONFIG_TI816X)
#if defined(CONFIG_TI816X)
#define BOOT_DEVICE_XIP 0x01
#define BOOT_DEVICE_XIPWAIT 0x02
#define BOOT_DEVICE_NAND 0x03

10
arch/arm/include/asm/arch-bcmcygnus/configs.h
View File

@@ -11,12 +11,8 @@
/* uArchitecture specifics */
/* Serial Info */
/* Post pad 3 bytes after each reg addr */
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_NS16550_CLK 100000000
#define CONFIG_SYS_NS16550_CLK_DIV 54
#define CONFIG_SYS_NS16550_COM3 0x18023000
#define CFG_SYS_NS16550_CLK 100000000
#define CFG_SYS_NS16550_CLK_DIV 54
#define CFG_SYS_NS16550_COM3 0x18023000
#endif /* __ARCH_CONFIGS_H */

7
arch/arm/include/asm/arch-bcmnsp/configs.h
View File

@@ -11,10 +11,7 @@
/* uArchitecture specifics */
/* Serial Info */
/* no padding */
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK 0x03b9aca0
#define CONFIG_SYS_NS16550_COM1 0x18000300
#define CFG_SYS_NS16550_CLK 0x03b9aca0
#define CFG_SYS_NS16550_COM1 0x18000300
#endif /* __ARCH_CONFIGS_H */

51
arch/arm/include/asm/arch-fsl-layerscape/config.h
View File

@@ -14,19 +14,17 @@
#include <linux/bitops.h>
#endif
#define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
/*
* Reserve secure memory
* To be aligned with MMU block size
*/
#define CONFIG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */
#define CFG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */
#define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
#ifdef CONFIG_ARCH_LS2080A
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
#define SRDS_MAX_LANES 8
#define CONFIG_SYS_PAGE_SIZE 0x10000
#define CFG_SYS_PAGE_SIZE 0x10000
#ifndef L1_CACHE_BYTES
#define L1_CACHE_SHIFT 6
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
@@ -37,8 +35,8 @@
#define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
/* DDR */
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0x06000000
@@ -96,7 +94,7 @@
#elif defined(CONFIG_ARCH_LS1088A)
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
#define CONFIG_SYS_PAGE_SIZE 0x10000
#define CFG_SYS_PAGE_SIZE 0x10000
#define SRDS_MAX_LANES 4
#define SRDS_BITS_PER_LANE 4
@@ -122,8 +120,8 @@
#define SMMU_BASE 0x05000000 /* GR0 Base */
/* DDR */
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* DCFG - GUR */
#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
@@ -141,15 +139,15 @@
#endif
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 }
#define CONFIG_SYS_PAGE_SIZE 0x10000
#define CFG_SYS_PAGE_SIZE 0x10000
#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
#define CFG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
/* DDR */
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0x06000000
@@ -162,7 +160,6 @@
#elif defined(CONFIG_ARCH_LS1028A)
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
#define CONFIG_FSL_TZASC_400
/* TZ Protection Controller Definitions */
#define TZPC_BASE 0x02200000
@@ -192,8 +189,8 @@
#define SMMU_BASE 0x05000000 /* GR0 Base */
/* DDR */
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* SEC */
@@ -209,11 +206,11 @@
/* SoC related */
#ifdef CONFIG_ARCH_LS1043A
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 7
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FM1_DTSEC 7
#define CFG_SYS_NUM_FM1_10GEC 1
#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
@@ -251,15 +248,15 @@
#elif defined(CONFIG_ARCH_LS1012A)
#define GICD_BASE 0x01401000
#define GICC_BASE 0x01402000
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
#elif defined(CONFIG_ARCH_LS1046A)
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 8
#define CONFIG_SYS_NUM_FM1_10GEC 2
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FM1_DTSEC 8
#define CFG_SYS_NUM_FM1_10GEC 2
#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* SMMU Defintions */
#define SMMU_BASE 0x09000000

24
arch/arm/include/asm/arch-fsl-layerscape/cpu.h
View File

@@ -35,17 +35,17 @@
#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000
#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000
#ifdef CONFIG_ARCH_LS2080A
#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000
#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000
#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000
#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000
#define CFG_SYS_PCIE1_PHYS_SIZE 0x200000000
#define CFG_SYS_PCIE2_PHYS_SIZE 0x200000000
#define CFG_SYS_PCIE3_PHYS_SIZE 0x200000000
#define CFG_SYS_PCIE4_PHYS_SIZE 0x200000000
#else
#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000
#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000
#ifndef CONFIG_SYS_PCIE3_PHYS_SIZE
#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000
#define CFG_SYS_PCIE1_PHYS_SIZE 0x800000000
#define CFG_SYS_PCIE2_PHYS_SIZE 0x800000000
#ifndef CFG_SYS_PCIE3_PHYS_SIZE
#define CFG_SYS_PCIE3_PHYS_SIZE 0x800000000
#endif
#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000
#define CFG_SYS_PCIE4_PHYS_SIZE 0x800000000
#define SYS_PCIE5_PHYS_SIZE 0x800000000
#define SYS_PCIE6_PHYS_SIZE 0x800000000
#endif
@@ -83,9 +83,9 @@
#define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000
#define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000
#define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */
#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000
#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000
#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000
#define CFG_SYS_PCIE1_PHYS_SIZE 0x800000000
#define CFG_SYS_PCIE2_PHYS_SIZE 0x800000000
#define CFG_SYS_PCIE3_PHYS_SIZE 0x800000000
#define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000
#define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */
#endif

4
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
View File

@@ -75,7 +75,7 @@ void fdt_fixup_icid(void *blob);
#define SET_USB_ICID(usb_num, compat, streamid) \
SET_SCFG_ICID(compat, streamid, usb##usb_num##_icid,\
CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
CFG_SYS_XHCI_USB##usb_num##_ADDR)
#define SET_SATA_ICID(compat, streamid) \
SET_SCFG_ICID(compat, streamid, sata_icid,\
@@ -142,7 +142,7 @@ extern int fman_icid_tbl_sz;
#define SET_USB_ICID(usb_num, compat, streamid) \
SET_GUR_ICID(compat, streamid, usb##usb_num##_amqr,\
CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
CFG_SYS_XHCI_USB##usb_num##_ADDR)
#define SET_SATA_ICID(sata_num, compat, streamid) \
SET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \

101
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
View File

@@ -11,11 +11,11 @@
#include <linux/bitops.h>
#endif
#define CONFIG_SYS_DCSRBAR 0x20000000
#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)
#define CFG_SYS_DCSRBAR 0x20000000
#define CFG_SYS_DCSR_DCFG_ADDR (CFG_SYS_DCSRBAR + 0x00140000)
#define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
#define CFG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)
#define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
#define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
@@ -26,44 +26,41 @@
#define CFG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000)
#define CFG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
#define CFG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500)
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600)
#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
#define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000)
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)
#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500)
#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600)
#define CFG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
#define CFG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
#define CFG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CFG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
#define CFG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
#define CFG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000)
#define CFG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0x508000000
#define CONFIG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \
CONFIG_SYS_BMAN_MEM_BASE)
#define CONFIG_SYS_BMAN_MEM_SIZE 0x08000000
#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x10000
#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x10000
#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
CONFIG_SYS_BMAN_CENA_SIZE)
#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0x3E80
#define CONFIG_SYS_QMAN_NUM_PORTALS 10
#define CONFIG_SYS_QMAN_MEM_BASE 0x500000000
#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
#define CONFIG_SYS_QMAN_MEM_SIZE 0x08000000
#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x10000
#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x10000
#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
CONFIG_SYS_QMAN_CENA_SIZE)
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0x3680
#define CFG_SYS_BMAN_NUM_PORTALS 10
#define CFG_SYS_BMAN_MEM_BASE 0x508000000
#define CFG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \
CFG_SYS_BMAN_MEM_BASE)
#define CFG_SYS_BMAN_MEM_SIZE 0x08000000
#define CFG_SYS_BMAN_SP_CENA_SIZE 0x10000
#define CFG_SYS_BMAN_SP_CINH_SIZE 0x10000
#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
CFG_SYS_BMAN_CENA_SIZE)
#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
#define CFG_SYS_BMAN_SWP_ISDR_REG 0x3E80
#define CFG_SYS_QMAN_NUM_PORTALS 10
#define CFG_SYS_QMAN_MEM_BASE 0x500000000
#define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE
#define CFG_SYS_QMAN_MEM_SIZE 0x08000000
#define CFG_SYS_QMAN_SP_CINH_SIZE 0x10000
#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
CFG_SYS_QMAN_CENA_SIZE)
#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
#define CFG_SYS_QMAN_SWP_ISDR_REG 0x3680
#define CFG_SYS_FSL_TIMER_ADDR 0x02b00000
@@ -93,9 +90,9 @@
#define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000)
#define QMAN_CQSIDR_REG 0x20a80
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL
#define CFG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL
#define CFG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL
#define CFG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL
/* LUT registers */
#ifdef CONFIG_ARCH_LS1012A
#define PCIE_LUT_BASE 0xC0000
@@ -137,20 +134,20 @@
#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
#define TP_INIT_PER_CLUSTER 4
#ifndef CONFIG_SYS_CCSRBAR
#define CONFIG_SYS_CCSRBAR 0x01000000
#ifndef CFG_SYS_CCSRBAR
#define CFG_SYS_CCSRBAR 0x01000000
#endif
#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
#ifndef CFG_SYS_CCSRBAR_PHYS_HIGH
#define CFG_SYS_CCSRBAR_PHYS_HIGH 0
#endif
#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
#define CONFIG_SYS_CCSRBAR_PHYS_LOW 0x01000000
#ifndef CFG_SYS_CCSRBAR_PHYS_LOW
#define CFG_SYS_CCSRBAR_PHYS_LOW 0x01000000
#endif
#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
CONFIG_SYS_CCSRBAR_PHYS_LOW)
#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
CFG_SYS_CCSRBAR_PHYS_LOW)
struct sys_info {
unsigned long freq_processor[CONFIG_MAX_CPUS];
@@ -160,7 +157,7 @@ struct sys_info {
unsigned long freq_localbus;
unsigned long freq_cga_m2;
#ifdef CONFIG_SYS_DPAA_FMAN
unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
unsigned long freq_fman[CFG_SYS_NUM_FMAN];
#endif
unsigned long freq_qman;
};

52
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
View File

@@ -33,10 +33,10 @@
#define FSL_ESDHC1_BASE_ADDR CFG_SYS_FSL_ESDHC_ADDR
#define FSL_ESDHC2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01150000)
#ifndef CONFIG_NXP_LSCH3_2
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
#define CFG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
#endif
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
#define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000
#define CFG_SYS_FSL_TIMER_ADDR 0x023e0000
#define CFG_SYS_FSL_PMU_CLTBENR (CFG_SYS_FSL_PMU_ADDR + \
@@ -67,8 +67,8 @@
#define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0)
#define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8)
#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
#define CFG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CFG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
/* TZ Address Space Controller Definitions */
#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
@@ -105,7 +105,7 @@
#define GPU_BASE_ADDR (CONFIG_SYS_IMMR + 0x0e0c0000)
/* SFP */
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
#define CFG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
/* SEC */
#define CFG_SYS_FSL_SEC_OFFSET 0x07000000ull
@@ -173,7 +173,7 @@
#endif
/* Security Monitor */
#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
#define CFG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
/* MMU 500 */
#define SMMU_SCR0 (SMMU_BASE + 0x0)
@@ -192,37 +192,35 @@
/* PCIe */
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
#define CFG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
#define CFG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
#define SYS_PCIE5_ADDR (CONFIG_SYS_IMMR + 0x2800000)
#define SYS_PCIE6_ADDR (CONFIG_SYS_IMMR + 0x2900000)
#endif
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x9000000000ULL
#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x9800000000ULL
#define CFG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL
#define CFG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL
#define CFG_SYS_PCIE3_PHYS_ADDR 0x9000000000ULL
#define CFG_SYS_PCIE4_PHYS_ADDR 0x9800000000ULL
#define SYS_PCIE5_PHYS_ADDR 0xa000000000ULL
#define SYS_PCIE6_PHYS_ADDR 0xa800000000ULL
#elif CONFIG_ARCH_LS1088A
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL
#define CFG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL
#define CFG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL
#define CFG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL
#elif CONFIG_ARCH_LS1028A
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x01f0000000ULL
#define CFG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL
#define CFG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL
#define CFG_SYS_PCIE3_PHYS_ADDR 0x01f0000000ULL
/* this is used by integrated PCI on LS1028, includes ECAM and register space */
#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x0010000000ULL
#define CFG_SYS_PCIE3_PHYS_SIZE 0x0010000000ULL
#else
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
#define CFG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL
#define CFG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
#define CFG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
#define CFG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
#endif
/* Device Configuration */
@@ -306,7 +304,7 @@ struct sys_info {
unsigned long freq_localbus;
unsigned long freq_qe;
#ifdef CONFIG_SYS_DPAA_FMAN
unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
unsigned long freq_fman[CFG_SYS_NUM_FMAN];
#endif
#ifdef CONFIG_SYS_DPAA_QBMAN
unsigned long freq_qman;

24
arch/arm/include/asm/arch-lpc32xx/config.h
View File

@@ -11,19 +11,11 @@
/* Basic CPU architecture */
/* UART configuration */
#if (CONFIG_CONS_INDEX == 1) || (CONFIG_CONS_INDEX == 2) || \
(CONFIG_CONS_INDEX == 7)
#if !defined(CONFIG_LPC32XX_HSUART)
#define CONFIG_LPC32XX_HSUART
#endif
#if !defined(CFG_SYS_NS16550_CLK)
#define CFG_SYS_NS16550_CLK 13000000
#endif
#if !defined(CONFIG_SYS_NS16550_CLK)
#define CONFIG_SYS_NS16550_CLK 13000000
#endif
#define CONFIG_SYS_BAUDRATE_TABLE \
#define CFG_SYS_BAUDRATE_TABLE \
{ 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
/* NAND */
@@ -32,24 +24,24 @@
#define NAND_SMALL_BLOCK_PAGE_SIZE 0x200
#if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE)
#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
#elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE)
#define CONFIG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, }
#define CFG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, }
#else
#error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value"
#endif
#define CONFIG_SYS_NAND_ECCSIZE 0x100
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CFG_SYS_NAND_ECCSIZE 0x100
#define CFG_SYS_NAND_ECCBYTES 3
#endif /* CONFIG_NAND_LPC32XX_SLC */
/* NOR Flash */
/* USB OHCI */
#if defined(CONFIG_USB_OHCI_LPC32XX)
#define CONFIG_SYS_USB_OHCI_REGS_BASE USB_BASE
#define CFG_SYS_USB_OHCI_REGS_BASE USB_BASE
#endif
#endif /* _LPC32XX_CONFIG_H */

48
arch/arm/include/asm/arch-ls102xa/config.h
View File

@@ -11,36 +11,31 @@
#define OCRAM_BASE_S_ADDR 0x10010000
#define OCRAM_S_SIZE 0x00010000
#define CONFIG_SYS_DCSRBAR 0x20000000
#define CFG_SYS_DCSRBAR 0x20000000
#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000)
#define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000)
#define CFG_SYS_DCSR_DCFG_ADDR (CFG_SYS_DCSRBAR + 0x00220000)
#define SYS_FSL_DCSR_RCPM_ADDR (CFG_SYS_DCSRBAR + 0x00222000)
#define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000)
#define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
#define CFG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
#define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
#define CFG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
#define CFG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000)
#define CFG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)
#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
#define CFG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
#define CFG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
#define CFG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
#define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
#define CFG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
#define CFG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
#define CFG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CFG_SYS_FSL_SEC_OFFSET 0x00700000
#define CFG_SYS_FSL_JR0_OFFSET 0x00710000
#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
#define CONFIG_SYS_MDIO1_OFFSET 0x01d24000
#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
#define SCTR_BASE_ADDR (CONFIG_SYS_IMMR + 0x01b00000)
@@ -55,28 +50,27 @@
#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
#define CFG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
#define CFG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
#define CONFIG_SYS_PCIE1_PHYS_BASE 0x4000000000ULL
#define CONFIG_SYS_PCIE2_PHYS_BASE 0x4800000000ULL
#define CONFIG_SYS_PCIE1_VIRT_ADDR 0x24000000UL
#define CONFIG_SYS_PCIE2_VIRT_ADDR 0x34000000UL
#define CONFIG_SYS_PCIE_MMAP_SIZE (192 * 1024 * 1024) /* 192M */
#define CFG_SYS_PCIE1_PHYS_BASE 0x4000000000ULL
#define CFG_SYS_PCIE2_PHYS_BASE 0x4800000000ULL
#define CFG_SYS_PCIE1_VIRT_ADDR 0x24000000UL
#define CFG_SYS_PCIE2_VIRT_ADDR 0x34000000UL
#define CFG_SYS_PCIE_MMAP_SIZE (192 * 1024 * 1024) /* 192M */
/*
* TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR)
* So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr.
*/
#define CONFIG_SYS_PCIE1_PHYS_ADDR (CONFIG_SYS_PCIE1_PHYS_BASE + \
CONFIG_SYS_PCIE1_VIRT_ADDR)
#define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \
CONFIG_SYS_PCIE2_VIRT_ADDR)
#define CFG_SYS_PCIE1_PHYS_ADDR (CFG_SYS_PCIE1_PHYS_BASE + \
CFG_SYS_PCIE1_VIRT_ADDR)
#define CFG_SYS_PCIE2_PHYS_ADDR (CFG_SYS_PCIE2_PHYS_BASE + \
CFG_SYS_PCIE2_VIRT_ADDR)
/* SATA */
#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
#ifdef CONFIG_DDR_SPD
#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
#define CFG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
#endif
#define DCU_LAYER_MAX_NUM 16

18
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
View File

@@ -42,24 +42,24 @@
#define DCFG_DCSR_PORCR1 0
#ifndef CONFIG_SYS_CCSRBAR
#define CONFIG_SYS_CCSRBAR CONFIG_SYS_IMMR
#ifndef CFG_SYS_CCSRBAR
#define CFG_SYS_CCSRBAR CONFIG_SYS_IMMR
#endif
#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
#ifndef CFG_SYS_CCSRBAR_PHYS_HIGH
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf
#define CFG_SYS_CCSRBAR_PHYS_HIGH 0xf
#else
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
#define CFG_SYS_CCSRBAR_PHYS_HIGH 0
#endif
#endif
#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR
#ifndef CFG_SYS_CCSRBAR_PHYS_LOW
#define CFG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR
#endif
#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
CONFIG_SYS_CCSRBAR_PHYS_LOW)
#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
CFG_SYS_CCSRBAR_PHYS_LOW)
struct sys_info {
unsigned long freq_processor[CONFIG_MAX_CPUS];

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