Merge tag 'u-boot-amlogic-20190423' of git://git.denx.de/u-boot-amlogic
- Add support for Amlogic p200 & p201 Reference Designs - Add Amlogic SoC information display - Add support for the Libretech-AC AML-S805X-AC board - Add Amlogic AXG reset compatible - Add I2C support for Amlogic AXG - Fix AXG PIN and BANK pinctrl definitions - Fix regmap_read_poll_timeout warning about sandbox_timer_add_offset - Add initial support for Amlogic G12A SoC and U200 board - Enable PHY_REALTEK for selected boards - Fix Khadas VIM2 README
This commit is contained in:
Tom Rini
104
arch/arm/include/asm/arch-meson/clock-g12a.h
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arch/arm/include/asm/arch-meson/clock-g12a.h
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2016 - AmLogic, Inc.
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* Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
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* Copyright 2018 - BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#ifndef _ARCH_MESON_CLOCK_G12A_H_
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#define _ARCH_MESON_CLOCK_G12A_H_
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/*
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* Clock controller register offsets
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*
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* Register offsets from the data sheet are listed in comment blocks below.
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* Those offsets must be multiplied by 4 before adding them to the base address
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* to get the right value
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*/
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#define HHI_MIPI_CNTL0 0x000
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#define HHI_MIPI_CNTL1 0x004
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#define HHI_MIPI_CNTL2 0x008
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#define HHI_MIPI_STS 0x00C
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#define HHI_GP0_PLL_CNTL0 0x040
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#define HHI_GP0_PLL_CNTL1 0x044
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#define HHI_GP0_PLL_CNTL2 0x048
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#define HHI_GP0_PLL_CNTL3 0x04C
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#define HHI_GP0_PLL_CNTL4 0x050
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#define HHI_GP0_PLL_CNTL5 0x054
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#define HHI_GP0_PLL_CNTL6 0x058
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#define HHI_GP0_PLL_STS 0x05C
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#define HHI_PCIE_PLL_CNTL0 0x098
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#define HHI_PCIE_PLL_CNTL1 0x09C
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#define HHI_PCIE_PLL_CNTL2 0x0A0
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#define HHI_PCIE_PLL_CNTL3 0x0A4
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#define HHI_PCIE_PLL_CNTL4 0x0A8
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#define HHI_PCIE_PLL_CNTL5 0x0AC
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#define HHI_PCIE_PLL_STS 0x0B8
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#define HHI_HIFI_PLL_CNTL0 0x0D8
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#define HHI_HIFI_PLL_CNTL1 0x0DC
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#define HHI_HIFI_PLL_CNTL2 0x0E0
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#define HHI_HIFI_PLL_CNTL3 0x0E4
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#define HHI_HIFI_PLL_CNTL4 0x0E8
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#define HHI_HIFI_PLL_CNTL5 0x0EC
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#define HHI_HIFI_PLL_CNTL6 0x0F0
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#define HHI_VIID_CLK_DIV 0x128
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#define HHI_VIID_CLK_CNTL 0x12C
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#define HHI_GCLK_MPEG0 0x140
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#define HHI_GCLK_MPEG1 0x144
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#define HHI_GCLK_MPEG2 0x148
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#define HHI_GCLK_OTHER 0x150
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#define HHI_GCLK_OTHER2 0x154
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#define HHI_VID_CLK_DIV 0x164
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#define HHI_MPEG_CLK_CNTL 0x174
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#define HHI_AUD_CLK_CNTL 0x178
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#define HHI_VID_CLK_CNTL 0x17c
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#define HHI_TS_CLK_CNTL 0x190
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#define HHI_VID_CLK_CNTL2 0x194
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#define HHI_SYS_CPU_CLK_CNTL0 0x19c
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#define HHI_VID_PLL_CLK_DIV 0x1A0
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#define HHI_MALI_CLK_CNTL 0x1b0
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#define HHI_VPU_CLKC_CNTL 0x1b4
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#define HHI_VPU_CLK_CNTL 0x1bC
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#define HHI_HDMI_CLK_CNTL 0x1CC
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#define HHI_VDEC_CLK_CNTL 0x1E0
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#define HHI_VDEC2_CLK_CNTL 0x1E4
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#define HHI_VDEC3_CLK_CNTL 0x1E8
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#define HHI_VDEC4_CLK_CNTL 0x1EC
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#define HHI_HDCP22_CLK_CNTL 0x1F0
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#define HHI_VAPBCLK_CNTL 0x1F4
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#define HHI_VPU_CLKB_CNTL 0x20C
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#define HHI_GEN_CLK_CNTL 0x228
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#define HHI_VDIN_MEAS_CLK_CNTL 0x250
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#define HHI_MIPIDSI_PHY_CLK_CNTL 0x254
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#define HHI_NAND_CLK_CNTL 0x25C
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#define HHI_SD_EMMC_CLK_CNTL 0x264
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#define HHI_MPLL_CNTL0 0x278
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#define HHI_MPLL_CNTL1 0x27C
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#define HHI_MPLL_CNTL2 0x280
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#define HHI_MPLL_CNTL3 0x284
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#define HHI_MPLL_CNTL4 0x288
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#define HHI_MPLL_CNTL5 0x28c
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#define HHI_MPLL_CNTL6 0x290
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#define HHI_MPLL_CNTL7 0x294
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#define HHI_MPLL_CNTL8 0x298
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#define HHI_FIX_PLL_CNTL0 0x2A0
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#define HHI_FIX_PLL_CNTL1 0x2A4
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#define HHI_FIX_PLL_CNTL3 0x2AC
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#define HHI_SYS_PLL_CNTL0 0x2f4
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#define HHI_SYS_PLL_CNTL1 0x2f8
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#define HHI_SYS_PLL_CNTL2 0x2fc
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#define HHI_SYS_PLL_CNTL3 0x300
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#define HHI_SYS_PLL_CNTL4 0x304
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#define HHI_SYS_PLL_CNTL5 0x308
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#define HHI_SYS_PLL_CNTL6 0x30c
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#define HHI_HDMI_PLL_CNTL0 0x320
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#define HHI_HDMI_PLL_CNTL1 0x324
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#define HHI_HDMI_PLL_CNTL2 0x328
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#define HHI_HDMI_PLL_CNTL3 0x32c
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#define HHI_HDMI_PLL_CNTL4 0x330
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#define HHI_HDMI_PLL_CNTL5 0x334
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#define HHI_HDMI_PLL_CNTL6 0x338
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#define HHI_SPICC_CLK_CNTL 0x3dc
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#endif
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66
arch/arm/include/asm/arch-meson/g12a.h
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66
arch/arm/include/asm/arch-meson/g12a.h
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#ifndef __G12A_H__
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#define __G12A_H__
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#define G12A_AOBUS_BASE 0xff800000
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#define G12A_PERIPHS_BASE 0xff634400
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#define G12A_HIU_BASE 0xff63c000
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#define G12A_ETH_PHY_BASE 0xff64c000
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#define G12A_ETH_BASE 0xff3f0000
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/* Always-On Peripherals registers */
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#define G12A_AO_ADDR(off) (G12A_AOBUS_BASE + ((off) << 2))
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#define G12A_AO_SEC_GP_CFG0 G12A_AO_ADDR(0x90)
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#define G12A_AO_SEC_GP_CFG3 G12A_AO_ADDR(0x93)
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#define G12A_AO_SEC_GP_CFG4 G12A_AO_ADDR(0x94)
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#define G12A_AO_SEC_GP_CFG5 G12A_AO_ADDR(0x95)
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#define G12A_AO_BOOT_DEVICE 0xF
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#define G12A_AO_MEM_SIZE_MASK 0xFFFF0000
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#define G12A_AO_MEM_SIZE_SHIFT 16
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#define G12A_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000
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#define G12A_AO_BL31_RSVMEM_SIZE_SHIFT 16
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#define G12A_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF
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/* Peripherals registers */
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#define G12A_PERIPHS_ADDR(off) (G12A_PERIPHS_BASE + ((off) << 2))
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#define G12A_ETH_REG_0 G12A_PERIPHS_ADDR(0x50)
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#define G12A_ETH_REG_1 G12A_PERIPHS_ADDR(0x51)
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#define G12A_ETH_REG_0_PHY_INTF_RGMII BIT(0)
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#define G12A_ETH_REG_0_PHY_INTF_RMII BIT(2)
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#define G12A_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
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#define G12A_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
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#define G12A_ETH_REG_0_PHY_CLK_EN BIT(10)
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#define G12A_ETH_REG_0_INVERT_RMII_CLK BIT(11)
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#define G12A_ETH_REG_0_CLK_EN BIT(12)
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#define G12A_ETH_PHY_ADDR(off) (G12A_ETH_PHY_BASE + ((off) << 2))
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#define ETH_PLL_CNTL0 G12A_ETH_PHY_ADDR(0x11)
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#define ETH_PLL_CNTL1 G12A_ETH_PHY_ADDR(0x12)
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#define ETH_PLL_CNTL2 G12A_ETH_PHY_ADDR(0x13)
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#define ETH_PLL_CNTL3 G12A_ETH_PHY_ADDR(0x14)
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#define ETH_PLL_CNTL4 G12A_ETH_PHY_ADDR(0x15)
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#define ETH_PLL_CNTL5 G12A_ETH_PHY_ADDR(0x16)
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#define ETH_PLL_CNTL6 G12A_ETH_PHY_ADDR(0x17)
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#define ETH_PLL_CNTL7 G12A_ETH_PHY_ADDR(0x18)
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#define ETH_PHY_CNTL0 G12A_ETH_PHY_ADDR(0x20)
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#define ETH_PHY_CNTL1 G12A_ETH_PHY_ADDR(0x21)
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#define ETH_PHY_CNTL2 G12A_ETH_PHY_ADDR(0x22)
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/* HIU registers */
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#define G12A_HIU_ADDR(off) (G12A_HIU_BASE + ((off) << 2))
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#define G12A_MEM_PD_REG_0 G12A_HIU_ADDR(0x40)
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/* Ethernet memory power domain */
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#define G12A_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3))
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#endif /* __G12A_H__ */
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