Merge tag 'u-boot-amlogic-20190423' of git://git.denx.de/u-boot-amlogic
- Add support for Amlogic p200 & p201 Reference Designs - Add Amlogic SoC information display - Add support for the Libretech-AC AML-S805X-AC board - Add Amlogic AXG reset compatible - Add I2C support for Amlogic AXG - Fix AXG PIN and BANK pinctrl definitions - Fix regmap_read_poll_timeout warning about sandbox_timer_add_offset - Add initial support for Amlogic G12A SoC and U200 board - Enable PHY_REALTEK for selected boards - Fix Khadas VIM2 README
This commit is contained in:
Tom Rini
@@ -97,11 +97,15 @@ dtb-$(CONFIG_ARCH_MESON) += \
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meson-gxbb-nanopi-k2.dtb \
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meson-gxbb-odroidc2.dtb \
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meson-gxbb-nanopi-k2.dtb \
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meson-gxbb-p200.dtb \
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meson-gxbb-p201.dtb \
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meson-gxl-s905x-p212.dtb \
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meson-gxl-s805x-libretech-ac.dtb \
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meson-gxl-s905x-libretech-cc.dtb \
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meson-gxl-s905x-khadas-vim.dtb \
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meson-gxm-khadas-vim2.dtb \
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meson-axg-s400.dtb
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meson-axg-s400.dtb \
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meson-g12a-u200.dtb
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dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
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tegra20-medcom-wide.dtb \
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tegra20-paz00.dtb \
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29
arch/arm/dts/meson-g12a-u200.dts
Normal file
29
arch/arm/dts/meson-g12a-u200.dts
Normal file
@@ -0,0 +1,29 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
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*/
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/dts-v1/;
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#include "meson-g12a.dtsi"
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/ {
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compatible = "amlogic,u200", "amlogic,g12a";
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model = "Amlogic Meson G12A U200 Development Board";
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aliases {
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serial0 = &uart_AO;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x40000000>;
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};
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};
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&uart_AO {
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status = "okay";
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};
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192
arch/arm/dts/meson-g12a.dtsi
Normal file
192
arch/arm/dts/meson-g12a.dtsi
Normal file
@@ -0,0 +1,192 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "amlogic,g12a";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x1>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x2>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x3>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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l2: l2-cache0 {
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compatible = "cache";
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* 3 MiB reserved for ARM Trusted Firmware (BL31) */
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secmon_reserved: secmon@5000000 {
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reg = <0x0 0x05000000 0x0 0x300000>;
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no-map;
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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apb: bus@ff600000 {
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compatible = "simple-bus";
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reg = <0x0 0xff600000 0x0 0x200000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
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periphs: bus@34400 {
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compatible = "simple-bus";
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reg = <0x0 0x34400 0x0 0x400>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
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};
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hiu: bus@3c000 {
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compatible = "simple-bus";
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reg = <0x0 0x3c000 0x0 0x1400>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>;
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hhi: system-controller@0 {
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compatible = "amlogic,meson-gx-hhi-sysctrl",
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"simple-mfd", "syscon";
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reg = <0 0 0 0x400>;
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clkc: clock-controller {
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compatible = "amlogic,g12a-clkc";
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#clock-cells = <1>;
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clocks = <&xtal>;
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clock-names = "xtal";
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};
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};
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};
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};
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aobus: bus@ff800000 {
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compatible = "simple-bus";
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reg = <0x0 0xff800000 0x0 0x100000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
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uart_AO: serial@3000 {
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compatible = "amlogic,meson-gx-uart",
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"amlogic,meson-ao-uart";
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reg = <0x0 0x3000 0x0 0x18>;
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interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xtal>, <&xtal>, <&xtal>;
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clock-names = "xtal", "pclk", "baud";
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status = "disabled";
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};
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uart_AO_B: serial@4000 {
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compatible = "amlogic,meson-gx-uart",
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"amlogic,meson-ao-uart";
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reg = <0x0 0x4000 0x0 0x18>;
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interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xtal>, <&xtal>, <&xtal>;
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clock-names = "xtal", "pclk", "baud";
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status = "disabled";
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};
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};
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gic: interrupt-controller@ffc01000 {
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compatible = "arm,gic-400";
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reg = <0x0 0xffc01000 0 0x1000>,
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<0x0 0xffc02000 0 0x2000>,
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<0x0 0xffc04000 0 0x2000>,
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<0x0 0xffc06000 0 0x2000>;
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interrupt-controller;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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};
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cbus: bus@ffd00000 {
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compatible = "simple-bus";
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reg = <0x0 0xffd00000 0x0 0x100000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
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clk_msr: clock-measure@18000 {
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compatible = "amlogic,meson-g12a-clk-measure";
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reg = <0x0 0x18000 0x0 0x10>;
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};
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
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};
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xtal: xtal-clk {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "xtal";
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#clock-cells = <0>;
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};
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};
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7
arch/arm/dts/meson-gxbb-p200-u-boot.dtsi
Normal file
7
arch/arm/dts/meson-gxbb-p200-u-boot.dtsi
Normal file
@@ -0,0 +1,7 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include "meson-gx-u-boot.dtsi"
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99
arch/arm/dts/meson-gxbb-p200.dts
Normal file
99
arch/arm/dts/meson-gxbb-p200.dts
Normal file
@@ -0,0 +1,99 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2016 Andreas Färber
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* Copyright (c) 2016 BayLibre, Inc.
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* Author: Kevin Hilman <khilman@kernel.org>
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*/
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/dts-v1/;
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#include "meson-gxbb-p20x.dtsi"
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#include <dt-bindings/input/input.h>
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/ {
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compatible = "amlogic,p200", "amlogic,meson-gxbb";
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model = "Amlogic Meson GXBB P200 Development Board";
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avdd18_usb_adc: regulator-avdd18_usb_adc {
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compatible = "regulator-fixed";
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regulator-name = "AVDD18_USB_ADC";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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adc_keys {
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compatible = "adc-keys";
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io-channels = <&saradc 0>;
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io-channel-names = "buttons";
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keyup-threshold-microvolt = <1800000>;
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button-home {
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label = "Home";
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linux,code = <KEY_HOME>;
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press-threshold-microvolt = <900000>; /* 50% */
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||||
};
|
||||
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||||
button-esc {
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||||
label = "Esc";
|
||||
linux,code = <KEY_ESC>;
|
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press-threshold-microvolt = <684000>; /* 38% */
|
||||
};
|
||||
|
||||
button-up {
|
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label = "Volume Up";
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
press-threshold-microvolt = <468000>; /* 26% */
|
||||
};
|
||||
|
||||
button-down {
|
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label = "Volume Down";
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
press-threshold-microvolt = <252000>; /* 14% */
|
||||
};
|
||||
|
||||
button-menu {
|
||||
label = "Menu";
|
||||
linux,code = <KEY_MENU>;
|
||||
press-threshold-microvolt = <0>; /* 0% */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ðmac {
|
||||
status = "okay";
|
||||
pinctrl-0 = <ð_rgmii_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy-handle = <ð_phy0>;
|
||||
phy-mode = "rgmii";
|
||||
|
||||
amlogic,tx-delay-ns = <2>;
|
||||
|
||||
snps,reset-gpio = <&gpio GPIOZ_14 0>;
|
||||
snps,reset-delays-us = <0 10000 1000000>;
|
||||
snps,reset-active-low;
|
||||
|
||||
mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
eth_phy0: ethernet-phy@3 {
|
||||
/* Micrel KSZ9031 (0x00221620) */
|
||||
reg = <3>;
|
||||
interrupt-parent = <&gpio_intc>;
|
||||
/* MAC_INTR on GPIOZ_15 */
|
||||
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c_B {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&i2c_b_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
status = "okay";
|
||||
vref-supply = <&avdd18_usb_adc>;
|
||||
};
|
||||
7
arch/arm/dts/meson-gxbb-p201-u-boot.dtsi
Normal file
7
arch/arm/dts/meson-gxbb-p201-u-boot.dtsi
Normal file
@@ -0,0 +1,7 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 BayLibre, SAS.
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*/
|
||||
|
||||
#include "meson-gx-u-boot.dtsi"
|
||||
26
arch/arm/dts/meson-gxbb-p201.dts
Normal file
26
arch/arm/dts/meson-gxbb-p201.dts
Normal file
@@ -0,0 +1,26 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2016 Andreas Färber
|
||||
* Copyright (c) 2016 BayLibre, Inc.
|
||||
* Author: Kevin Hilman <khilman@kernel.org>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "meson-gxbb-p20x.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "amlogic,p201", "amlogic,meson-gxbb";
|
||||
model = "Amlogic Meson GXBB P201 Development Board";
|
||||
};
|
||||
|
||||
ðmac {
|
||||
status = "okay";
|
||||
pinctrl-0 = <ð_rmii_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy-mode = "rmii";
|
||||
|
||||
snps,reset-gpio = <&gpio GPIOZ_14 0>;
|
||||
snps,reset-delays-us = <0 10000 1000000>;
|
||||
snps,reset-active-low;
|
||||
};
|
||||
247
arch/arm/dts/meson-gxbb-p20x.dtsi
Normal file
247
arch/arm/dts/meson-gxbb-p20x.dtsi
Normal file
@@ -0,0 +1,247 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2016 Andreas Färber
|
||||
* Copyright (c) 2016 BayLibre, Inc.
|
||||
* Author: Kevin Hilman <khilman@kernel.org>
|
||||
*/
|
||||
|
||||
#include "meson-gxbb.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
serial0 = &uart_AO;
|
||||
ethernet0 = ðmac;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x40000000>;
|
||||
};
|
||||
|
||||
usb_pwr: regulator-usb-pwrs {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "USB_PWR";
|
||||
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
|
||||
/* signal name in schematic: USB_PWR_EN */
|
||||
gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vddio_card: gpio-regulator {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "VDDIO_CARD";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
|
||||
/* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */
|
||||
states = <1800000 0
|
||||
3300000 1>;
|
||||
|
||||
regulator-settling-time-up-us = <10000>;
|
||||
regulator-settling-time-down-us = <150000>;
|
||||
};
|
||||
|
||||
vddio_boot: regulator-vddio_boot {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VDDIO_BOOT";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
vddao_3v3: regulator-vddao_3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VDDAO_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vcc_3v3: regulator-vcc_3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
emmc_pwrseq: emmc-pwrseq {
|
||||
compatible = "mmc-pwrseq-emmc";
|
||||
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
wifi32k: wifi32k {
|
||||
compatible = "pwm-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
|
||||
};
|
||||
|
||||
sdio_pwrseq: sdio-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
|
||||
clocks = <&wifi32k>;
|
||||
clock-names = "ext_clock";
|
||||
};
|
||||
|
||||
cvbs_connector: cvbs-connector {
|
||||
compatible = "composite-video-connector";
|
||||
|
||||
port {
|
||||
cvbs_connector_in: endpoint {
|
||||
remote-endpoint = <&cvbs_vdac_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-connector {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_connector_in: endpoint {
|
||||
remote-endpoint = <&hdmi_tx_tmds_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cec_AO {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&ao_cec_pins>;
|
||||
pinctrl-names = "default";
|
||||
hdmi-phandle = <&hdmi_tx>;
|
||||
};
|
||||
|
||||
&cvbs_vdac_port {
|
||||
cvbs_vdac_out: endpoint {
|
||||
remote-endpoint = <&cvbs_connector_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_tx {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&hdmi_tx_tmds_port {
|
||||
hdmi_tx_tmds_out: endpoint {
|
||||
remote-endpoint = <&hdmi_connector_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&ir {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&remote_input_ao_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&pwm_ef {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&pwm_e_pins>;
|
||||
pinctrl-names = "default";
|
||||
clocks = <&clkc CLKID_FCLK_DIV4>;
|
||||
clock-names = "clkin0";
|
||||
};
|
||||
|
||||
/* Wireless SDIO Module */
|
||||
&sd_emmc_a {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&sdio_pins>;
|
||||
pinctrl-1 = <&sdio_clk_gate_pins>;
|
||||
pinctrl-names = "default", "clk-gate";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
max-frequency = <100000000>;
|
||||
|
||||
non-removable;
|
||||
disable-wp;
|
||||
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
|
||||
vmmc-supply = <&vddao_3v3>;
|
||||
vqmmc-supply = <&vddio_boot>;
|
||||
|
||||
brcmf: wifi@1 {
|
||||
reg = <1>;
|
||||
compatible = "brcm,bcm4329-fmac";
|
||||
};
|
||||
};
|
||||
|
||||
/* SD card */
|
||||
&sd_emmc_b {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&sdcard_pins>;
|
||||
pinctrl-1 = <&sdcard_clk_gate_pins>;
|
||||
pinctrl-names = "default", "clk-gate";
|
||||
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
max-frequency = <100000000>;
|
||||
disable-wp;
|
||||
|
||||
cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
|
||||
|
||||
vmmc-supply = <&vddao_3v3>;
|
||||
vqmmc-supply = <&vddio_card>;
|
||||
};
|
||||
|
||||
/* eMMC */
|
||||
&sd_emmc_c {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
|
||||
pinctrl-1 = <&emmc_clk_gate_pins>;
|
||||
pinctrl-names = "default", "clk-gate";
|
||||
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
disable-wp;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
|
||||
mmc-pwrseq = <&emmc_pwrseq>;
|
||||
vmmc-supply = <&vcc_3v3>;
|
||||
vqmmc-supply = <&vddio_boot>;
|
||||
};
|
||||
|
||||
/* This UART is brought out to the DB9 connector */
|
||||
&uart_AO {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&uart_ao_a_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&usb0_phy {
|
||||
status = "okay";
|
||||
phy-supply = <&usb_pwr>;
|
||||
};
|
||||
|
||||
&usb1_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
};
|
||||
248
arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
Normal file
248
arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
Normal file
@@ -0,0 +1,248 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2018 BayLibre, SAS.
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
* Author: Jerome Brunet <jbrunet@baylibre.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
#include "meson-gxl-s905x.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "libretech,aml-s805x-ac", "amlogic,s805x",
|
||||
"amlogic,meson-gxl";
|
||||
model = "Libre Computer Board AML-S805X-AC";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart_AO;
|
||||
ethernet0 = ðmac;
|
||||
spi0 = &spifc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
cvbs-connector {
|
||||
/*
|
||||
* The pads are present but no connector is soldered on
|
||||
* 2J2, so keep this off by default.
|
||||
*/
|
||||
status = "disabled";
|
||||
compatible = "composite-video-connector";
|
||||
|
||||
port {
|
||||
cvbs_connector_in: endpoint {
|
||||
remote-endpoint = <&cvbs_vdac_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dc_5v: regulator-dc_5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "DC_5V";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
emmc_pwrseq: emmc-pwrseq {
|
||||
compatible = "mmc-pwrseq-emmc";
|
||||
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
hdmi-connector {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_connector_in: endpoint {
|
||||
remote-endpoint = <&hdmi_tx_tmds_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x20000000>;
|
||||
};
|
||||
|
||||
vcck: regulator-vcck {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCCK";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&dc_5v>;
|
||||
|
||||
/*
|
||||
* This is controlled by GPIOAO_9 we reserve this but
|
||||
* claiming it as done below reset the board anyway
|
||||
* Need to investigate this
|
||||
*
|
||||
* gpio = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
|
||||
* enable-active-high;
|
||||
*/
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_3v3: regulator-vcc_3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&dc_5v>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vddio_boot: regulator-vddio_boot {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VDDIO_BOOT";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc_3v3>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&cec_AO {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&ao_cec_pins>;
|
||||
pinctrl-names = "default";
|
||||
hdmi-phandle = <&hdmi_tx>;
|
||||
};
|
||||
|
||||
&cvbs_vdac_port {
|
||||
cvbs_vdac_out: endpoint {
|
||||
remote-endpoint = <&cvbs_connector_in>;
|
||||
};
|
||||
};
|
||||
|
||||
ðmac {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&internal_phy {
|
||||
pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&ir {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&remote_input_ao_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&hdmi_tx {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&hdmi_tx_tmds_port {
|
||||
hdmi_tx_tmds_out: endpoint {
|
||||
remote-endpoint = <&hdmi_connector_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio_ao {
|
||||
gpio-line-names = "UART TX",
|
||||
"UART RX",
|
||||
"7J1 Header Pin31",
|
||||
"", "", "", "",
|
||||
"IR In",
|
||||
"HDMI CEC",
|
||||
"5V VCCK Regulator",
|
||||
/* GPIO_TEST_N */
|
||||
"";
|
||||
};
|
||||
|
||||
&gpio {
|
||||
gpio-line-names = /* Bank GPIOZ */
|
||||
"", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "",
|
||||
"Eth Link LED", "Eth Activity LED",
|
||||
/* Bank GPIOH */
|
||||
"HDMI HPD", "HDMI SDA", "HDMI SCL",
|
||||
"", "7J1 Header Pin13",
|
||||
"7J1 Header Pin15",
|
||||
"7J1 Header Pin7",
|
||||
"7J1 Header Pin12",
|
||||
"7J1 Header Pin16",
|
||||
"7J1 Header Pin18",
|
||||
/* Bank BOOT */
|
||||
"eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3",
|
||||
"eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7",
|
||||
"eMMC Clk", "eMMC Reset", "eMMC CMD",
|
||||
"SPI NOR MOSI", "SPI NOR MISO", "SPI NOR Clk",
|
||||
"", "SPI NOR Chip Select",
|
||||
/* Bank CARD */
|
||||
"", "", "", "", "", "", "",
|
||||
/* Bank GPIODV */
|
||||
"", "", "", "", "", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "", "", "", "", "",
|
||||
"7J1 Header Pin27", "7J1 Header Pin28", "",
|
||||
"7J1 Header Pin29",
|
||||
"VCCK Regulator", "VDDEE Regulator",
|
||||
/* Bank GPIOX */
|
||||
"7J1 Header Pin22", "7J1 Header Pin26",
|
||||
"7J1 Header Pin36", "7J1 Header Pin38",
|
||||
"7J1 Header Pin40", "7J1 Header Pin37",
|
||||
"7J1 Header Pin33", "7J1 Header Pin35",
|
||||
"7J1 Header Pin19", "7J1 Header Pin21",
|
||||
"7J1 Header Pin24", "7J1 Header Pin23",
|
||||
"7J1 Header Pin8", "7J1 Header Pin10",
|
||||
"", "", "7J1 Header Pin32", "", "",
|
||||
/* Bank GPIOCLK */
|
||||
"", "";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
status = "okay";
|
||||
vref-supply = <&vddio_boot>;
|
||||
};
|
||||
|
||||
/* eMMC */
|
||||
&sd_emmc_c {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&emmc_pins>;
|
||||
pinctrl-1 = <&emmc_clk_gate_pins>;
|
||||
pinctrl-names = "default", "clk-gate";
|
||||
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
max-frequency = <200000000>;
|
||||
disable-wp;
|
||||
|
||||
mmc-pwrseq = <&emmc_pwrseq>;
|
||||
vmmc-supply = <&vcc_3v3>;
|
||||
vqmmc-supply = <&vddio_boot>;
|
||||
};
|
||||
|
||||
&spifc {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&nor_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
w25q32: spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart_AO {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&uart_ao_a_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -75,6 +75,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
&efuse {
|
||||
clocks = <&clkc CLKID_EFUSE>;
|
||||
};
|
||||
|
||||
ðmac {
|
||||
reg = <0x0 0xc9410000 0x0 0x10000
|
||||
0x0 0xc8834540 0x0 0x4>;
|
||||
@@ -112,6 +116,7 @@
|
||||
mux {
|
||||
groups = "uart_tx_ao_a", "uart_rx_ao_a";
|
||||
function = "uart_ao";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -120,6 +125,7 @@
|
||||
groups = "uart_cts_ao_a",
|
||||
"uart_rts_ao_a";
|
||||
function = "uart_ao";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -127,6 +133,7 @@
|
||||
mux {
|
||||
groups = "uart_tx_ao_b", "uart_rx_ao_b";
|
||||
function = "uart_ao_b";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -134,6 +141,7 @@
|
||||
mux {
|
||||
groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
|
||||
function = "uart_ao_b";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -142,6 +150,7 @@
|
||||
groups = "uart_cts_ao_b",
|
||||
"uart_rts_ao_b";
|
||||
function = "uart_ao_b";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -149,6 +158,7 @@
|
||||
mux {
|
||||
groups = "remote_input_ao";
|
||||
function = "remote_input_ao";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -157,6 +167,7 @@
|
||||
groups = "i2c_sck_ao",
|
||||
"i2c_sda_ao";
|
||||
function = "i2c_ao";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -164,6 +175,7 @@
|
||||
mux {
|
||||
groups = "pwm_ao_a_3";
|
||||
function = "pwm_ao_a";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -171,6 +183,7 @@
|
||||
mux {
|
||||
groups = "pwm_ao_a_8";
|
||||
function = "pwm_ao_a";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -178,6 +191,7 @@
|
||||
mux {
|
||||
groups = "pwm_ao_b";
|
||||
function = "pwm_ao_b";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -185,6 +199,7 @@
|
||||
mux {
|
||||
groups = "pwm_ao_b_6";
|
||||
function = "pwm_ao_b";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -192,6 +207,7 @@
|
||||
mux {
|
||||
groups = "i2s_out_ch23_ao";
|
||||
function = "i2s_out_ao";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -199,6 +215,7 @@
|
||||
mux {
|
||||
groups = "i2s_out_ch45_ao";
|
||||
function = "i2s_out_ao";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -206,6 +223,7 @@
|
||||
mux {
|
||||
groups = "spdif_out_ao_6";
|
||||
function = "spdif_out_ao";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -213,6 +231,7 @@
|
||||
mux {
|
||||
groups = "spdif_out_ao_9";
|
||||
function = "spdif_out_ao";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -220,6 +239,7 @@
|
||||
mux {
|
||||
groups = "ao_cec";
|
||||
function = "cec_ao";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -227,6 +247,7 @@
|
||||
mux {
|
||||
groups = "ee_cec";
|
||||
function = "cec_ao";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -239,6 +260,8 @@
|
||||
|
||||
&clkc_AO {
|
||||
compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
|
||||
clocks = <&xtal>, <&clkc CLKID_CLK81>;
|
||||
clock-names = "xtal", "mpeg-clk";
|
||||
};
|
||||
|
||||
&gpio_intc {
|
||||
@@ -263,6 +286,8 @@
|
||||
clkc: clock-controller {
|
||||
compatible = "amlogic,gxl-clkc";
|
||||
#clock-cells = <1>;
|
||||
clocks = <&xtal>;
|
||||
clock-names = "xtal";
|
||||
};
|
||||
};
|
||||
|
||||
@@ -306,6 +331,7 @@
|
||||
"emmc_cmd",
|
||||
"emmc_clk";
|
||||
function = "emmc";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -313,6 +339,7 @@
|
||||
mux {
|
||||
groups = "emmc_ds";
|
||||
function = "emmc";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -320,9 +347,6 @@
|
||||
mux {
|
||||
groups = "BOOT_8";
|
||||
function = "gpio_periphs";
|
||||
};
|
||||
cfg-pull-down {
|
||||
pins = "BOOT_8";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
@@ -334,6 +358,7 @@
|
||||
"nor_c",
|
||||
"nor_cs";
|
||||
function = "nor";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -343,6 +368,7 @@
|
||||
"spi_mosi",
|
||||
"spi_sclk";
|
||||
function = "spi";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -350,6 +376,7 @@
|
||||
mux {
|
||||
groups = "spi_ss0";
|
||||
function = "spi";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -362,6 +389,7 @@
|
||||
"sdcard_cmd",
|
||||
"sdcard_clk";
|
||||
function = "sdcard";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -369,9 +397,6 @@
|
||||
mux {
|
||||
groups = "CARD_2";
|
||||
function = "gpio_periphs";
|
||||
};
|
||||
cfg-pull-down {
|
||||
pins = "CARD_2";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
@@ -385,6 +410,7 @@
|
||||
"sdio_cmd",
|
||||
"sdio_clk";
|
||||
function = "sdio";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -392,9 +418,6 @@
|
||||
mux {
|
||||
groups = "GPIOX_4";
|
||||
function = "gpio_periphs";
|
||||
};
|
||||
cfg-pull-down {
|
||||
pins = "GPIOX_4";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
@@ -403,6 +426,7 @@
|
||||
mux {
|
||||
groups = "sdio_irq";
|
||||
function = "sdio";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -411,6 +435,7 @@
|
||||
groups = "uart_tx_a",
|
||||
"uart_rx_a";
|
||||
function = "uart_a";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -419,6 +444,7 @@
|
||||
groups = "uart_cts_a",
|
||||
"uart_rts_a";
|
||||
function = "uart_a";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -427,6 +453,7 @@
|
||||
groups = "uart_tx_b",
|
||||
"uart_rx_b";
|
||||
function = "uart_b";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -435,6 +462,7 @@
|
||||
groups = "uart_cts_b",
|
||||
"uart_rts_b";
|
||||
function = "uart_b";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -443,6 +471,7 @@
|
||||
groups = "uart_tx_c",
|
||||
"uart_rx_c";
|
||||
function = "uart_c";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -451,6 +480,7 @@
|
||||
groups = "uart_cts_c",
|
||||
"uart_rts_c";
|
||||
function = "uart_c";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -459,6 +489,7 @@
|
||||
groups = "i2c_sck_a",
|
||||
"i2c_sda_a";
|
||||
function = "i2c_a";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -467,6 +498,7 @@
|
||||
groups = "i2c_sck_b",
|
||||
"i2c_sda_b";
|
||||
function = "i2c_b";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -475,6 +507,7 @@
|
||||
groups = "i2c_sck_c",
|
||||
"i2c_sda_c";
|
||||
function = "i2c_c";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -495,6 +528,7 @@
|
||||
"eth_txd2",
|
||||
"eth_txd3";
|
||||
function = "eth";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -502,6 +536,7 @@
|
||||
mux {
|
||||
groups = "eth_link_led";
|
||||
function = "eth_led";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -516,6 +551,7 @@
|
||||
mux {
|
||||
groups = "pwm_a";
|
||||
function = "pwm_a";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -523,6 +559,7 @@
|
||||
mux {
|
||||
groups = "pwm_b";
|
||||
function = "pwm_b";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -530,6 +567,7 @@
|
||||
mux {
|
||||
groups = "pwm_c";
|
||||
function = "pwm_c";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -537,6 +575,7 @@
|
||||
mux {
|
||||
groups = "pwm_d";
|
||||
function = "pwm_d";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -544,6 +583,7 @@
|
||||
mux {
|
||||
groups = "pwm_e";
|
||||
function = "pwm_e";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -551,6 +591,7 @@
|
||||
mux {
|
||||
groups = "pwm_f_clk";
|
||||
function = "pwm_f";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -558,6 +599,7 @@
|
||||
mux {
|
||||
groups = "pwm_f_x";
|
||||
function = "pwm_f";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -565,6 +607,7 @@
|
||||
mux {
|
||||
groups = "hdmi_hpd";
|
||||
function = "hdmi_hpd";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -572,6 +615,7 @@
|
||||
mux {
|
||||
groups = "hdmi_sda", "hdmi_scl";
|
||||
function = "hdmi_i2c";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -579,6 +623,7 @@
|
||||
mux {
|
||||
groups = "i2s_am_clk";
|
||||
function = "i2s_out";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -586,6 +631,7 @@
|
||||
mux {
|
||||
groups = "i2s_out_ao_clk";
|
||||
function = "i2s_out";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -593,6 +639,7 @@
|
||||
mux {
|
||||
groups = "i2s_out_lr_clk";
|
||||
function = "i2s_out";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -600,12 +647,14 @@
|
||||
mux {
|
||||
groups = "i2s_out_ch01";
|
||||
function = "i2s_out";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
i2sout_ch23_z_pins: i2sout_ch23_z {
|
||||
mux {
|
||||
groups = "i2sout_ch23_z";
|
||||
function = "i2s_out";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -613,6 +662,7 @@
|
||||
mux {
|
||||
groups = "i2sout_ch45_z";
|
||||
function = "i2s_out";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -620,6 +670,7 @@
|
||||
mux {
|
||||
groups = "i2sout_ch67_z";
|
||||
function = "i2s_out";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -627,6 +678,7 @@
|
||||
mux {
|
||||
groups = "spdif_out_h";
|
||||
function = "spdif_out";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
104
arch/arm/include/asm/arch-meson/clock-g12a.h
Normal file
104
arch/arm/include/asm/arch-meson/clock-g12a.h
Normal file
@@ -0,0 +1,104 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2016 - AmLogic, Inc.
|
||||
* Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
|
||||
* Copyright 2018 - BayLibre, SAS
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*/
|
||||
#ifndef _ARCH_MESON_CLOCK_G12A_H_
|
||||
#define _ARCH_MESON_CLOCK_G12A_H_
|
||||
|
||||
/*
|
||||
* Clock controller register offsets
|
||||
*
|
||||
* Register offsets from the data sheet are listed in comment blocks below.
|
||||
* Those offsets must be multiplied by 4 before adding them to the base address
|
||||
* to get the right value
|
||||
*/
|
||||
|
||||
#define HHI_MIPI_CNTL0 0x000
|
||||
#define HHI_MIPI_CNTL1 0x004
|
||||
#define HHI_MIPI_CNTL2 0x008
|
||||
#define HHI_MIPI_STS 0x00C
|
||||
#define HHI_GP0_PLL_CNTL0 0x040
|
||||
#define HHI_GP0_PLL_CNTL1 0x044
|
||||
#define HHI_GP0_PLL_CNTL2 0x048
|
||||
#define HHI_GP0_PLL_CNTL3 0x04C
|
||||
#define HHI_GP0_PLL_CNTL4 0x050
|
||||
#define HHI_GP0_PLL_CNTL5 0x054
|
||||
#define HHI_GP0_PLL_CNTL6 0x058
|
||||
#define HHI_GP0_PLL_STS 0x05C
|
||||
#define HHI_PCIE_PLL_CNTL0 0x098
|
||||
#define HHI_PCIE_PLL_CNTL1 0x09C
|
||||
#define HHI_PCIE_PLL_CNTL2 0x0A0
|
||||
#define HHI_PCIE_PLL_CNTL3 0x0A4
|
||||
#define HHI_PCIE_PLL_CNTL4 0x0A8
|
||||
#define HHI_PCIE_PLL_CNTL5 0x0AC
|
||||
#define HHI_PCIE_PLL_STS 0x0B8
|
||||
#define HHI_HIFI_PLL_CNTL0 0x0D8
|
||||
#define HHI_HIFI_PLL_CNTL1 0x0DC
|
||||
#define HHI_HIFI_PLL_CNTL2 0x0E0
|
||||
#define HHI_HIFI_PLL_CNTL3 0x0E4
|
||||
#define HHI_HIFI_PLL_CNTL4 0x0E8
|
||||
#define HHI_HIFI_PLL_CNTL5 0x0EC
|
||||
#define HHI_HIFI_PLL_CNTL6 0x0F0
|
||||
#define HHI_VIID_CLK_DIV 0x128
|
||||
#define HHI_VIID_CLK_CNTL 0x12C
|
||||
#define HHI_GCLK_MPEG0 0x140
|
||||
#define HHI_GCLK_MPEG1 0x144
|
||||
#define HHI_GCLK_MPEG2 0x148
|
||||
#define HHI_GCLK_OTHER 0x150
|
||||
#define HHI_GCLK_OTHER2 0x154
|
||||
#define HHI_VID_CLK_DIV 0x164
|
||||
#define HHI_MPEG_CLK_CNTL 0x174
|
||||
#define HHI_AUD_CLK_CNTL 0x178
|
||||
#define HHI_VID_CLK_CNTL 0x17c
|
||||
#define HHI_TS_CLK_CNTL 0x190
|
||||
#define HHI_VID_CLK_CNTL2 0x194
|
||||
#define HHI_SYS_CPU_CLK_CNTL0 0x19c
|
||||
#define HHI_VID_PLL_CLK_DIV 0x1A0
|
||||
#define HHI_MALI_CLK_CNTL 0x1b0
|
||||
#define HHI_VPU_CLKC_CNTL 0x1b4
|
||||
#define HHI_VPU_CLK_CNTL 0x1bC
|
||||
#define HHI_HDMI_CLK_CNTL 0x1CC
|
||||
#define HHI_VDEC_CLK_CNTL 0x1E0
|
||||
#define HHI_VDEC2_CLK_CNTL 0x1E4
|
||||
#define HHI_VDEC3_CLK_CNTL 0x1E8
|
||||
#define HHI_VDEC4_CLK_CNTL 0x1EC
|
||||
#define HHI_HDCP22_CLK_CNTL 0x1F0
|
||||
#define HHI_VAPBCLK_CNTL 0x1F4
|
||||
#define HHI_VPU_CLKB_CNTL 0x20C
|
||||
#define HHI_GEN_CLK_CNTL 0x228
|
||||
#define HHI_VDIN_MEAS_CLK_CNTL 0x250
|
||||
#define HHI_MIPIDSI_PHY_CLK_CNTL 0x254
|
||||
#define HHI_NAND_CLK_CNTL 0x25C
|
||||
#define HHI_SD_EMMC_CLK_CNTL 0x264
|
||||
#define HHI_MPLL_CNTL0 0x278
|
||||
#define HHI_MPLL_CNTL1 0x27C
|
||||
#define HHI_MPLL_CNTL2 0x280
|
||||
#define HHI_MPLL_CNTL3 0x284
|
||||
#define HHI_MPLL_CNTL4 0x288
|
||||
#define HHI_MPLL_CNTL5 0x28c
|
||||
#define HHI_MPLL_CNTL6 0x290
|
||||
#define HHI_MPLL_CNTL7 0x294
|
||||
#define HHI_MPLL_CNTL8 0x298
|
||||
#define HHI_FIX_PLL_CNTL0 0x2A0
|
||||
#define HHI_FIX_PLL_CNTL1 0x2A4
|
||||
#define HHI_FIX_PLL_CNTL3 0x2AC
|
||||
#define HHI_SYS_PLL_CNTL0 0x2f4
|
||||
#define HHI_SYS_PLL_CNTL1 0x2f8
|
||||
#define HHI_SYS_PLL_CNTL2 0x2fc
|
||||
#define HHI_SYS_PLL_CNTL3 0x300
|
||||
#define HHI_SYS_PLL_CNTL4 0x304
|
||||
#define HHI_SYS_PLL_CNTL5 0x308
|
||||
#define HHI_SYS_PLL_CNTL6 0x30c
|
||||
#define HHI_HDMI_PLL_CNTL0 0x320
|
||||
#define HHI_HDMI_PLL_CNTL1 0x324
|
||||
#define HHI_HDMI_PLL_CNTL2 0x328
|
||||
#define HHI_HDMI_PLL_CNTL3 0x32c
|
||||
#define HHI_HDMI_PLL_CNTL4 0x330
|
||||
#define HHI_HDMI_PLL_CNTL5 0x334
|
||||
#define HHI_HDMI_PLL_CNTL6 0x338
|
||||
#define HHI_SPICC_CLK_CNTL 0x3dc
|
||||
|
||||
#endif
|
||||
66
arch/arm/include/asm/arch-meson/g12a.h
Normal file
66
arch/arm/include/asm/arch-meson/g12a.h
Normal file
@@ -0,0 +1,66 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2018 BayLibre, SAS
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*/
|
||||
|
||||
#ifndef __G12A_H__
|
||||
#define __G12A_H__
|
||||
|
||||
#define G12A_AOBUS_BASE 0xff800000
|
||||
#define G12A_PERIPHS_BASE 0xff634400
|
||||
#define G12A_HIU_BASE 0xff63c000
|
||||
#define G12A_ETH_PHY_BASE 0xff64c000
|
||||
#define G12A_ETH_BASE 0xff3f0000
|
||||
|
||||
/* Always-On Peripherals registers */
|
||||
#define G12A_AO_ADDR(off) (G12A_AOBUS_BASE + ((off) << 2))
|
||||
|
||||
#define G12A_AO_SEC_GP_CFG0 G12A_AO_ADDR(0x90)
|
||||
#define G12A_AO_SEC_GP_CFG3 G12A_AO_ADDR(0x93)
|
||||
#define G12A_AO_SEC_GP_CFG4 G12A_AO_ADDR(0x94)
|
||||
#define G12A_AO_SEC_GP_CFG5 G12A_AO_ADDR(0x95)
|
||||
|
||||
#define G12A_AO_BOOT_DEVICE 0xF
|
||||
#define G12A_AO_MEM_SIZE_MASK 0xFFFF0000
|
||||
#define G12A_AO_MEM_SIZE_SHIFT 16
|
||||
#define G12A_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000
|
||||
#define G12A_AO_BL31_RSVMEM_SIZE_SHIFT 16
|
||||
#define G12A_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF
|
||||
|
||||
/* Peripherals registers */
|
||||
#define G12A_PERIPHS_ADDR(off) (G12A_PERIPHS_BASE + ((off) << 2))
|
||||
|
||||
#define G12A_ETH_REG_0 G12A_PERIPHS_ADDR(0x50)
|
||||
#define G12A_ETH_REG_1 G12A_PERIPHS_ADDR(0x51)
|
||||
|
||||
#define G12A_ETH_REG_0_PHY_INTF_RGMII BIT(0)
|
||||
#define G12A_ETH_REG_0_PHY_INTF_RMII BIT(2)
|
||||
#define G12A_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
|
||||
#define G12A_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
|
||||
#define G12A_ETH_REG_0_PHY_CLK_EN BIT(10)
|
||||
#define G12A_ETH_REG_0_INVERT_RMII_CLK BIT(11)
|
||||
#define G12A_ETH_REG_0_CLK_EN BIT(12)
|
||||
|
||||
#define G12A_ETH_PHY_ADDR(off) (G12A_ETH_PHY_BASE + ((off) << 2))
|
||||
#define ETH_PLL_CNTL0 G12A_ETH_PHY_ADDR(0x11)
|
||||
#define ETH_PLL_CNTL1 G12A_ETH_PHY_ADDR(0x12)
|
||||
#define ETH_PLL_CNTL2 G12A_ETH_PHY_ADDR(0x13)
|
||||
#define ETH_PLL_CNTL3 G12A_ETH_PHY_ADDR(0x14)
|
||||
#define ETH_PLL_CNTL4 G12A_ETH_PHY_ADDR(0x15)
|
||||
#define ETH_PLL_CNTL5 G12A_ETH_PHY_ADDR(0x16)
|
||||
#define ETH_PLL_CNTL6 G12A_ETH_PHY_ADDR(0x17)
|
||||
#define ETH_PLL_CNTL7 G12A_ETH_PHY_ADDR(0x18)
|
||||
#define ETH_PHY_CNTL0 G12A_ETH_PHY_ADDR(0x20)
|
||||
#define ETH_PHY_CNTL1 G12A_ETH_PHY_ADDR(0x21)
|
||||
#define ETH_PHY_CNTL2 G12A_ETH_PHY_ADDR(0x22)
|
||||
|
||||
/* HIU registers */
|
||||
#define G12A_HIU_ADDR(off) (G12A_HIU_BASE + ((off) << 2))
|
||||
|
||||
#define G12A_MEM_PD_REG_0 G12A_HIU_ADDR(0x40)
|
||||
|
||||
/* Ethernet memory power domain */
|
||||
#define G12A_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3))
|
||||
|
||||
#endif /* __G12A_H__ */
|
||||
@@ -41,7 +41,13 @@ config MESON_AXG
|
||||
bool "AXG"
|
||||
select MESON64_COMMON
|
||||
help
|
||||
Select this if your SoC is an A113X/D
|
||||
Select this if your SoC is an A113X/D
|
||||
|
||||
config MESON_G12A
|
||||
bool "G12A"
|
||||
select MESON64_COMMON
|
||||
help
|
||||
Select this if your SoC is an S905X/D2
|
||||
|
||||
endchoice
|
||||
|
||||
@@ -61,10 +67,11 @@ config SYS_VENDOR
|
||||
|
||||
config SYS_BOARD
|
||||
string "Board name"
|
||||
default "odroid-c2" if MESON_GXBB
|
||||
default "p200" if MESON_GXBB
|
||||
default "p212" if MESON_GXL
|
||||
default "q200" if MESON_GXM
|
||||
default "s400" if MESON_AXG
|
||||
default "u200" if MESON_G12A
|
||||
default ""
|
||||
help
|
||||
This option contains information about board name.
|
||||
|
||||
@@ -2,6 +2,7 @@
|
||||
#
|
||||
# Copyright (c) 2016 Beniamino Galvani <b.galvani@gmail.com>
|
||||
|
||||
obj-y += board-common.o sm.o
|
||||
obj-y += board-common.o sm.o board-info.o
|
||||
obj-$(CONFIG_MESON_GX) += board-gx.o
|
||||
obj-$(CONFIG_MESON_AXG) += board-axg.o
|
||||
obj-$(CONFIG_MESON_G12A) += board-g12a.o
|
||||
|
||||
150
arch/arm/mach-meson/board-g12a.c
Normal file
150
arch/arm/mach-meson/board-g12a.c
Normal file
@@ -0,0 +1,150 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
|
||||
* (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/boot.h>
|
||||
#include <asm/arch/eth.h>
|
||||
#include <asm/arch/g12a.h>
|
||||
#include <asm/arch/mem.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/armv8/mmu.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <phy.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int meson_get_boot_device(void)
|
||||
{
|
||||
return readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_BOOT_DEVICE;
|
||||
}
|
||||
|
||||
/* Configure the reserved memory zones exported by the secure registers
|
||||
* into EFI and DTB reserved memory entries.
|
||||
*/
|
||||
void meson_init_reserved_memory(void *fdt)
|
||||
{
|
||||
u64 bl31_size, bl31_start;
|
||||
u64 bl32_size, bl32_start;
|
||||
u32 reg;
|
||||
|
||||
/*
|
||||
* Get ARM Trusted Firmware reserved memory zones in :
|
||||
* - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
|
||||
* - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
|
||||
* - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
|
||||
*/
|
||||
reg = readl(G12A_AO_SEC_GP_CFG3);
|
||||
|
||||
bl31_size = ((reg & G12A_AO_BL31_RSVMEM_SIZE_MASK)
|
||||
>> G12A_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
|
||||
bl32_size = (reg & G12A_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
|
||||
|
||||
bl31_start = readl(G12A_AO_SEC_GP_CFG5);
|
||||
bl32_start = readl(G12A_AO_SEC_GP_CFG4);
|
||||
|
||||
/* Add BL31 reserved zone */
|
||||
if (bl31_start && bl31_size)
|
||||
meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
|
||||
|
||||
/* Add BL32 reserved zone */
|
||||
if (bl32_start && bl32_size)
|
||||
meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
|
||||
}
|
||||
|
||||
phys_size_t get_effective_memsize(void)
|
||||
{
|
||||
/* Size is reported in MiB, convert it in bytes */
|
||||
return ((readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_MEM_SIZE_MASK)
|
||||
>> G12A_AO_MEM_SIZE_SHIFT) * SZ_1M;
|
||||
}
|
||||
|
||||
static struct mm_region g12a_mem_map[] = {
|
||||
{
|
||||
.virt = 0x0UL,
|
||||
.phys = 0x0UL,
|
||||
.size = 0x80000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_INNER_SHARE
|
||||
}, {
|
||||
.virt = 0xf0000000UL,
|
||||
.phys = 0xf0000000UL,
|
||||
.size = 0x10000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE |
|
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
}, {
|
||||
/* List terminator */
|
||||
0,
|
||||
}
|
||||
};
|
||||
|
||||
struct mm_region *mem_map = g12a_mem_map;
|
||||
|
||||
static void g12a_enable_external_mdio(void)
|
||||
{
|
||||
writel(0x0, ETH_PHY_CNTL2);
|
||||
}
|
||||
|
||||
static void g12a_enable_internal_mdio(void)
|
||||
{
|
||||
/* Fire up the PHY PLL */
|
||||
writel(0x29c0040a, ETH_PLL_CNTL0);
|
||||
writel(0x927e0000, ETH_PLL_CNTL1);
|
||||
writel(0xac5f49e5, ETH_PLL_CNTL2);
|
||||
writel(0x00000000, ETH_PLL_CNTL3);
|
||||
writel(0x00000000, ETH_PLL_CNTL4);
|
||||
writel(0x20200000, ETH_PLL_CNTL5);
|
||||
writel(0x0000c002, ETH_PLL_CNTL6);
|
||||
writel(0x00000023, ETH_PLL_CNTL7);
|
||||
writel(0x39c0040a, ETH_PLL_CNTL0);
|
||||
writel(0x19c0040a, ETH_PLL_CNTL0);
|
||||
|
||||
/* Select the internal MDIO */
|
||||
writel(0x33000180, ETH_PHY_CNTL0);
|
||||
writel(0x00074043, ETH_PHY_CNTL1);
|
||||
writel(0x00000260, ETH_PHY_CNTL2);
|
||||
}
|
||||
|
||||
/* Configure the Ethernet MAC with the requested interface mode
|
||||
* with some optional flags.
|
||||
*/
|
||||
void meson_eth_init(phy_interface_t mode, unsigned int flags)
|
||||
{
|
||||
switch (mode) {
|
||||
case PHY_INTERFACE_MODE_RGMII:
|
||||
case PHY_INTERFACE_MODE_RGMII_ID:
|
||||
case PHY_INTERFACE_MODE_RGMII_RXID:
|
||||
case PHY_INTERFACE_MODE_RGMII_TXID:
|
||||
/* Set RGMII mode */
|
||||
setbits_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RGMII |
|
||||
G12A_ETH_REG_0_TX_PHASE(1) |
|
||||
G12A_ETH_REG_0_TX_RATIO(4) |
|
||||
G12A_ETH_REG_0_PHY_CLK_EN |
|
||||
G12A_ETH_REG_0_CLK_EN);
|
||||
break;
|
||||
|
||||
case PHY_INTERFACE_MODE_RMII:
|
||||
/* Set RMII mode */
|
||||
out_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RMII |
|
||||
G12A_ETH_REG_0_INVERT_RMII_CLK |
|
||||
G12A_ETH_REG_0_CLK_EN);
|
||||
|
||||
/* Use G12A RMII Internal PHY */
|
||||
if (flags & MESON_USE_INTERNAL_RMII_PHY)
|
||||
g12a_enable_internal_mdio();
|
||||
else
|
||||
g12a_enable_external_mdio();
|
||||
|
||||
break;
|
||||
|
||||
default:
|
||||
printf("Invalid Ethernet interface mode\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Enable power gate */
|
||||
clrbits_le32(G12A_MEM_PD_REG_0, G12A_MEM_PD_REG_0_ETH_MASK);
|
||||
}
|
||||
166
arch/arm/mach-meson/board-info.c
Normal file
166
arch/arm/mach-meson/board-info.c
Normal file
@@ -0,0 +1,166 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2019 Julien Masson <jmasson@baylibre.com>
|
||||
* (C) Copyright 2019 Neil Armstrong <narmstrong@baylibre.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <dm.h>
|
||||
#include <linux/bitfield.h>
|
||||
#include <regmap.h>
|
||||
#include <syscon.h>
|
||||
|
||||
#define AO_SEC_SD_CFG8 0xe0
|
||||
#define AO_SEC_SOCINFO_OFFSET AO_SEC_SD_CFG8
|
||||
|
||||
#define SOCINFO_MAJOR GENMASK(31, 24)
|
||||
#define SOCINFO_PACK GENMASK(23, 16)
|
||||
#define SOCINFO_MINOR GENMASK(15, 8)
|
||||
#define SOCINFO_MISC GENMASK(7, 0)
|
||||
|
||||
static const struct meson_gx_soc_id {
|
||||
const char *name;
|
||||
unsigned int id;
|
||||
} soc_ids[] = {
|
||||
{ "GXBB", 0x1f },
|
||||
{ "GXTVBB", 0x20 },
|
||||
{ "GXL", 0x21 },
|
||||
{ "GXM", 0x22 },
|
||||
{ "TXL", 0x23 },
|
||||
{ "TXLX", 0x24 },
|
||||
{ "AXG", 0x25 },
|
||||
{ "GXLX", 0x26 },
|
||||
{ "TXHD", 0x27 },
|
||||
{ "G12A", 0x28 },
|
||||
{ "G12B", 0x29 },
|
||||
};
|
||||
|
||||
static const struct meson_gx_package_id {
|
||||
const char *name;
|
||||
unsigned int major_id;
|
||||
unsigned int pack_id;
|
||||
unsigned int pack_mask;
|
||||
} soc_packages[] = {
|
||||
{ "S905", 0x1f, 0, 0x20 }, /* pack_id != 0x20 */
|
||||
{ "S905H", 0x1f, 0x3, 0xf }, /* pack_id & 0xf == 0x3 */
|
||||
{ "S905M", 0x1f, 0x20, 0xf0 }, /* pack_id == 0x20 */
|
||||
{ "S905D", 0x21, 0, 0xf0 },
|
||||
{ "S905X", 0x21, 0x80, 0xf0 },
|
||||
{ "S905W", 0x21, 0xa0, 0xf0 },
|
||||
{ "S905L", 0x21, 0xc0, 0xf0 },
|
||||
{ "S905M2", 0x21, 0xe0, 0xf0 },
|
||||
{ "S805X", 0x21, 0x30, 0xf0 },
|
||||
{ "S805Y", 0x21, 0xb0, 0xf0 },
|
||||
{ "S912", 0x22, 0, 0x0 }, /* Only S912 is known for GXM */
|
||||
{ "962X", 0x24, 0x10, 0xf0 },
|
||||
{ "962E", 0x24, 0x20, 0xf0 },
|
||||
{ "A113X", 0x25, 0x37, 0xff },
|
||||
{ "A113D", 0x25, 0x22, 0xff },
|
||||
{ "S905D2", 0x28, 0x10, 0xf0 },
|
||||
{ "S905X2", 0x28, 0x40, 0xf0 },
|
||||
{ "S922X", 0x29, 0x40, 0xf0 },
|
||||
};
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static inline unsigned int socinfo_to_major(u32 socinfo)
|
||||
{
|
||||
return FIELD_GET(SOCINFO_MAJOR, socinfo);
|
||||
}
|
||||
|
||||
static inline unsigned int socinfo_to_minor(u32 socinfo)
|
||||
{
|
||||
return FIELD_GET(SOCINFO_MINOR, socinfo);
|
||||
}
|
||||
|
||||
static inline unsigned int socinfo_to_pack(u32 socinfo)
|
||||
{
|
||||
return FIELD_GET(SOCINFO_PACK, socinfo);
|
||||
}
|
||||
|
||||
static inline unsigned int socinfo_to_misc(u32 socinfo)
|
||||
{
|
||||
return FIELD_GET(SOCINFO_MISC, socinfo);
|
||||
}
|
||||
|
||||
static const char *socinfo_to_package_id(u32 socinfo)
|
||||
{
|
||||
unsigned int pack = socinfo_to_pack(socinfo);
|
||||
unsigned int major = socinfo_to_major(socinfo);
|
||||
int i;
|
||||
|
||||
for (i = 0 ; i < ARRAY_SIZE(soc_packages) ; ++i) {
|
||||
if (soc_packages[i].major_id == major &&
|
||||
soc_packages[i].pack_id ==
|
||||
(pack & soc_packages[i].pack_mask))
|
||||
return soc_packages[i].name;
|
||||
}
|
||||
|
||||
return "Unknown";
|
||||
}
|
||||
|
||||
static const char *socinfo_to_soc_id(u32 socinfo)
|
||||
{
|
||||
unsigned int id = socinfo_to_major(socinfo);
|
||||
int i;
|
||||
|
||||
for (i = 0 ; i < ARRAY_SIZE(soc_ids) ; ++i) {
|
||||
if (soc_ids[i].id == id)
|
||||
return soc_ids[i].name;
|
||||
}
|
||||
|
||||
return "Unknown";
|
||||
}
|
||||
|
||||
static void print_board_model(void)
|
||||
{
|
||||
const char *model;
|
||||
model = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
|
||||
printf("Model: %s\n", model ? model : "Unknown");
|
||||
}
|
||||
|
||||
int show_board_info(void)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
int nodeoffset, ret;
|
||||
ofnode node;
|
||||
unsigned int socinfo;
|
||||
|
||||
/* find the offset of compatible node */
|
||||
nodeoffset = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
|
||||
"amlogic,meson-gx-ao-secure");
|
||||
if (nodeoffset < 0)
|
||||
return 0;
|
||||
|
||||
/* check if chip-id is available */
|
||||
if (!fdt_getprop(gd->fdt_blob, nodeoffset, "amlogic,has-chip-id", NULL))
|
||||
return 0;
|
||||
|
||||
/* get regmap from the syscon node */
|
||||
node = offset_to_ofnode(nodeoffset);
|
||||
regmap = syscon_node_to_regmap(node);
|
||||
if (IS_ERR(regmap)) {
|
||||
printf("%s: failed to get regmap\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* read soc info */
|
||||
ret = regmap_read(regmap, AO_SEC_SOCINFO_OFFSET, &socinfo);
|
||||
if (ret && !socinfo) {
|
||||
printf("%s: invalid chipid value\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* print board information */
|
||||
print_board_model();
|
||||
printf("Soc: Amlogic Meson %s (%s) Revision %x:%x (%x:%x)\n",
|
||||
socinfo_to_soc_id(socinfo),
|
||||
socinfo_to_package_id(socinfo),
|
||||
socinfo_to_major(socinfo),
|
||||
socinfo_to_minor(socinfo),
|
||||
socinfo_to_pack(socinfo),
|
||||
socinfo_to_misc(socinfo));
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -59,14 +59,6 @@ void sandbox_i2c_eeprom_set_test_mode(struct udevice *dev,
|
||||
|
||||
void sandbox_i2c_eeprom_set_offset_len(struct udevice *dev, int offset_len);
|
||||
|
||||
/*
|
||||
* sandbox_timer_add_offset()
|
||||
*
|
||||
* Allow tests to add to the time reported through lib/time.c functions
|
||||
* offset: number of milliseconds to advance the system time
|
||||
*/
|
||||
void sandbox_timer_add_offset(unsigned long offset);
|
||||
|
||||
/**
|
||||
* sandbox_i2c_rtc_set_offset() - set the time offset from system/base time
|
||||
*
|
||||
|
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Reference in New Issue
Block a user