ARM: dts: suniv: Add device tree files and bindings for F1C100s
Add device tree files for suniv and Lichee Pi Nano it is a board based on F1C100s. dt-bindings/dts are synced with 5.16.0 Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Icenowy Zheng
Andre Przywara
parent
cfe673cda7
commit
ce2b6c4481
@ -504,6 +504,8 @@ dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \
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stm32h743i-eval.dtb \
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stm32h750i-art-pi.dtb
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dtb-$(CONFIG_MACH_SUNIV) += \
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suniv-f1c100s-licheepi-nano.dtb
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dtb-$(CONFIG_MACH_SUN4I) += \
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sun4i-a10-a1000.dtb \
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sun4i-a10-ba10-tvbox.dtb \
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26
arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
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26
arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
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@ -0,0 +1,26 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR X11)
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/*
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* Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
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*/
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/dts-v1/;
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#include "suniv-f1c100s.dtsi"
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/ {
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model = "Lichee Pi Nano";
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compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s";
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pe_pins>;
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status = "okay";
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};
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144
arch/arm/dts/suniv-f1c100s.dtsi
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144
arch/arm/dts/suniv-f1c100s.dtsi
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@ -0,0 +1,144 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR X11)
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/*
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* Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
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* Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com>
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*/
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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clocks {
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osc24M: clk-24M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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osc32k: clk-32k {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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};
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};
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cpus {
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cpu {
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compatible = "arm,arm926ej-s";
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device_type = "cpu";
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sram-controller@1c00000 {
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compatible = "allwinner,suniv-f1c100s-system-control",
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"allwinner,sun4i-a10-system-control";
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reg = <0x01c00000 0x30>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sram_d: sram@10000 {
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compatible = "mmio-sram";
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reg = <0x00010000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x00010000 0x1000>;
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otg_sram: sram-section@0 {
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compatible = "allwinner,suniv-f1c100s-sram-d",
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"allwinner,sun4i-a10-sram-d";
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reg = <0x0000 0x1000>;
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status = "disabled";
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};
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};
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};
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ccu: clock@1c20000 {
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compatible = "allwinner,suniv-f1c100s-ccu";
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reg = <0x01c20000 0x400>;
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clocks = <&osc24M>, <&osc32k>;
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clock-names = "hosc", "losc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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intc: interrupt-controller@1c20400 {
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compatible = "allwinner,suniv-f1c100s-ic";
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reg = <0x01c20400 0x400>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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pio: pinctrl@1c20800 {
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compatible = "allwinner,suniv-f1c100s-pinctrl";
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reg = <0x01c20800 0x400>;
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interrupts = <38>, <39>, <40>;
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clocks = <&ccu 37>, <&osc24M>, <&osc32k>;
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clock-names = "apb", "hosc", "losc";
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <3>;
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#gpio-cells = <3>;
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uart0_pe_pins: uart0-pe-pins {
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pins = "PE0", "PE1";
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function = "uart0";
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};
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};
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timer@1c20c00 {
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compatible = "allwinner,suniv-f1c100s-timer";
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reg = <0x01c20c00 0x90>;
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interrupts = <13>;
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clocks = <&osc24M>;
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};
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wdt: watchdog@1c20ca0 {
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compatible = "allwinner,suniv-f1c100s-wdt",
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"allwinner,sun4i-a10-wdt";
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reg = <0x01c20ca0 0x20>;
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};
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uart0: serial@1c25000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c25000 0x400>;
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interrupts = <1>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu 38>;
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resets = <&ccu 24>;
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status = "disabled";
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};
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uart1: serial@1c25400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c25400 0x400>;
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interrupts = <2>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu 39>;
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resets = <&ccu 25>;
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status = "disabled";
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};
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uart2: serial@1c25800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c25800 0x400>;
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interrupts = <3>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu 40>;
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resets = <&ccu 26>;
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status = "disabled";
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};
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};
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};
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@ -12,7 +12,9 @@
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/ {
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aliases {
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#ifndef CONFIG_MACH_SUNIV
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mmc0 = &mmc0;
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#endif
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#if CONFIG_MMC_SUNXI_SLOT_EXTRA == 2
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mmc1 = &mmc2;
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#endif
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70
include/dt-bindings/clock/suniv-ccu-f1c100s.h
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70
include/dt-bindings/clock/suniv-ccu-f1c100s.h
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@ -0,0 +1,70 @@
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/* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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*
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* Copyright (c) 2018 Icenowy Zheng <icenowy@aosc.xyz>
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*
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*/
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#ifndef _DT_BINDINGS_CLK_SUNIV_F1C100S_H_
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#define _DT_BINDINGS_CLK_SUNIV_F1C100S_H_
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#define CLK_CPU 11
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#define CLK_BUS_DMA 14
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#define CLK_BUS_MMC0 15
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#define CLK_BUS_MMC1 16
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#define CLK_BUS_DRAM 17
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#define CLK_BUS_SPI0 18
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#define CLK_BUS_SPI1 19
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#define CLK_BUS_OTG 20
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#define CLK_BUS_VE 21
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#define CLK_BUS_LCD 22
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#define CLK_BUS_DEINTERLACE 23
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#define CLK_BUS_CSI 24
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#define CLK_BUS_TVD 25
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#define CLK_BUS_TVE 26
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#define CLK_BUS_DE_BE 27
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#define CLK_BUS_DE_FE 28
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#define CLK_BUS_CODEC 29
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#define CLK_BUS_SPDIF 30
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#define CLK_BUS_IR 31
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#define CLK_BUS_RSB 32
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#define CLK_BUS_I2S0 33
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#define CLK_BUS_I2C0 34
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#define CLK_BUS_I2C1 35
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#define CLK_BUS_I2C2 36
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#define CLK_BUS_PIO 37
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#define CLK_BUS_UART0 38
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#define CLK_BUS_UART1 39
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#define CLK_BUS_UART2 40
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#define CLK_MMC0 41
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#define CLK_MMC0_SAMPLE 42
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#define CLK_MMC0_OUTPUT 43
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#define CLK_MMC1 44
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#define CLK_MMC1_SAMPLE 45
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#define CLK_MMC1_OUTPUT 46
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#define CLK_I2S 47
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#define CLK_SPDIF 48
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#define CLK_USB_PHY0 49
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#define CLK_DRAM_VE 50
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#define CLK_DRAM_CSI 51
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#define CLK_DRAM_DEINTERLACE 52
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#define CLK_DRAM_TVD 53
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#define CLK_DRAM_DE_FE 54
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#define CLK_DRAM_DE_BE 55
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#define CLK_DE_BE 56
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#define CLK_DE_FE 57
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#define CLK_TCON 58
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#define CLK_DEINTERLACE 59
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#define CLK_TVE2_CLK 60
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#define CLK_TVE1_CLK 61
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#define CLK_TVD 62
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#define CLK_CSI 63
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#define CLK_VE 64
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#define CLK_CODEC 65
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#define CLK_AVS 66
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#endif
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38
include/dt-bindings/reset/suniv-ccu-f1c100s.h
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38
include/dt-bindings/reset/suniv-ccu-f1c100s.h
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@ -0,0 +1,38 @@
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/* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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*
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* Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.xyz>
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*
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*/
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#ifndef _DT_BINDINGS_RST_SUNIV_F1C100S_H_
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#define _DT_BINDINGS_RST_SUNIV_F1C100S_H_
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#define RST_USB_PHY0 0
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#define RST_BUS_DMA 1
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#define RST_BUS_MMC0 2
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#define RST_BUS_MMC1 3
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#define RST_BUS_DRAM 4
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#define RST_BUS_SPI0 5
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#define RST_BUS_SPI1 6
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#define RST_BUS_OTG 7
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#define RST_BUS_VE 8
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#define RST_BUS_LCD 9
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#define RST_BUS_DEINTERLACE 10
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#define RST_BUS_CSI 11
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#define RST_BUS_TVD 12
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#define RST_BUS_TVE 13
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#define RST_BUS_DE_BE 14
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#define RST_BUS_DE_FE 15
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#define RST_BUS_CODEC 16
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#define RST_BUS_SPDIF 17
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#define RST_BUS_IR 18
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#define RST_BUS_RSB 19
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#define RST_BUS_I2S0 20
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#define RST_BUS_I2C0 21
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#define RST_BUS_I2C1 22
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#define RST_BUS_I2C2 23
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#define RST_BUS_UART0 24
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#define RST_BUS_UART1 25
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#define RST_BUS_UART2 26
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#endif /* _DT_BINDINGS_RST_SUNIV_F1C100S_H_ */
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