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omap3: overo: Use software BCH8 ECC for NAND

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Overo COMs have NAND flash that requires 4-bit ECC or better except for
the first sector which can use 1-bit ECC.  The boot ROM expects to load
a payload from NAND written using 1-bit hardware-based ECC.  In short,
write SPL to NAND something like this (4 times for redundancy):
 #> nandecc hw
 #> nand write ${loadaddr} 0x0 ${filesize}
 #> nand write ${loadaddr} 0x20000 ${filesize}
 #> nand write ${loadaddr} 0x40000 ${filesize}
 #> nand write ${loadaddr} 0x60000 ${filesize}

Then, switch back to software-based BCH8 for everything else:
 #> nandecc sw bch8

After [1], enlarge the max size of the SPL so the BCH code can fit.

[1] https://www.mail-archive.com/u-boot@lists.denx.de/msg163912.html

Signed-off-by: Ash Charles <ashcharles@gmail.com>
This commit is contained in:
Ash Charles 2015-04-28 16:17:53 -07:00 committed by Tom Rini
parent 2ed43b549b
commit ce170a1c3d
1 changed files with 15 additions and 4 deletions
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19
include/configs/omap3_overo.h
View File

@ -11,6 +11,12 @@
#define CONFIG_NAND
#include <configs/ti_omap3_common.h>
#undef CONFIG_SPL_MAX_SIZE
#define CONFIG_SPL_MAX_SIZE (64*1024)
#undef CONFIG_SPL_TEXT_BASE
#define CONFIG_SPL_TEXT_BASE 0x40200000
#define CONFIG_BCH
/* Display CPU and Board information */
#define CONFIG_DISPLAY_CPUINFO
@ -212,17 +218,22 @@
/* NAND boot config */
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
#define CONFIG_SYS_NAND_MAX_ECCPOS 56
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
13, 14, 16, 17, 18, 19, 20, 21, 22, \
23, 24, 25, 26, 27, 28, 30, 31, 32, \
33, 34, 35, 36, 37, 38, 39, 40, 41, \
42, 44, 45, 46, 47, 48, 49, 50, 51, \
52, 53, 54, 55, 56}
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
#define CONFIG_SYS_NAND_ECCBYTES 13
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
/* NAND: SPL falcon mode configs */