* Patch by Laurent Mohin, 10 Feb 2004:
Fix buffer overflow in common/usb.c * Patch by Tolunay Orkun, 10 Feb 2004: Add support for Cogent CSB272 board * Code cleanup
This commit is contained in:
wdenk
51
board/csb272/Makefile
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51
board/csb272/Makefile
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@@ -0,0 +1,51 @@
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#
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# (C) Copyright 2000-2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
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||||
#
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# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
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||||
#
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||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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#OBJS = $(BOARD).o flash.o
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#OBJS = $(BOARD).o strataflash.o
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OBJS = $(BOARD).o
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SOBJS = init.o
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$(LIB): $(OBJS) $(SOBJS)
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$(AR) crv $@ $^
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
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$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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sinclude .depend
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#########################################################################
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36
board/csb272/config.mk
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36
board/csb272/config.mk
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@@ -0,0 +1,36 @@
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#
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# (C) Copyright 2000-2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2004
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# Tolunay Orkun, NextIO Inc., torkun@nextio.com.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
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||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# Cogent CSB272 board
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#
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LDFLAGS += $(LINKER_UNDEFS)
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TEXT_BASE := 0xFFFC0000
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#TEXT_BASE := 0x00100000
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PLATFORM_RELFLAGS := $(PLATFORM_RELFLAGS)
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174
board/csb272/csb272.c
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174
board/csb272/csb272.c
Normal file
@@ -0,0 +1,174 @@
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/*
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* (C) Copyright 2004
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* Tolunay Orkun, Nextio Inc., torkun@nextio.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/u-boot.h>
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#include <asm/processor.h>
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#include <common.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <405gp_enet.h>
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/*
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* Configuration data for AMIS FS6377-01 Programmable 3-PLL Clock Generator
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*
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* CLKA output => Epson LCD Controller
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* CLKB output => Not Connected
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* CLKC output => Ethernet
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* CLKD output => UART external clock
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*
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* Note: these values are obtained from device after init by micromonitor
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*/
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uchar pll_fs6377_regs[16] = {
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0x28, 0xef, 0x53, 0x03, 0x4b, 0x80, 0x32, 0x80,
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0x94, 0x32, 0x80, 0xd4, 0x56, 0xf6, 0xf6, 0xe0 };
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/*
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* pll_init: Initialize AMIS IC FS6377-01 PLL
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*
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* PLL supplies Epson LCD Clock, Ethernet Clock and UART external clock
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*
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*/
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int pll_init(void)
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{
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i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
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return i2c_write(CFG_I2C_PLL_ADDR, 0, 1,
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(uchar *) pll_fs6377_regs, sizeof(pll_fs6377_regs));
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}
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/*
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* board_pre_init: do any preliminary board initialization
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*
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*/
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int board_pre_init(void)
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{
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/* initialize PLL so UART, LCD, Ethernet clocked at correctly */
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(void) get_clocks();
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pll_init();
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/*-------------------------------------------------------------------------+
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| Interrupt controller setup for the Walnut board.
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| Note: IRQ 0-15 405GP internally generated; active high; level sensitive
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| IRQ 16 405GP internally generated; active low; level sensitive
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| IRQ 17-24 RESERVED
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| IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
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| IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
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| IRQ 27 (EXT IRQ 2) Not Used
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| IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
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| IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
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| IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
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| IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
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| Note for Walnut board:
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| An interrupt taken for the FPGA (IRQ 25) indicates that either
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| the Mouse, Keyboard, IRDA, or External Expansion caused the
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| interrupt. The FPGA must be read to determine which device
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| caused the interrupt. The default setting of the FPGA clears
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|
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+-------------------------------------------------------------------------*/
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mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr (uicer, 0x00000000); /* disable all ints */
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mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
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mtdcr (uicpr, 0xFFFFFF83); /* set int polarities */
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mtdcr (uictr, 0x10000000); /* set int trigger levels */
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mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
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mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
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mtebc (epcr, 0xa8400000); /* EBC always driven */
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return 0; /* success */
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}
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/*
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* checkboard: identify/verify the board we are running
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*
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* Remark: we just assume it is correct board here!
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*
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*/
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int checkboard(void)
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{
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printf("BOARD: Cogent CSB272\n");
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return 0; /* success */
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}
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/*
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* initram: Determine the size of mounted DRAM
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*
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* Size is determined by reading SDRAM configuration registers as
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* configured by initialization code
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*
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*/
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long initdram (int board_type)
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{
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ulong tot_size;
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ulong bank_size;
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ulong tmp;
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tot_size = 0;
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mtdcr (memcfga, mem_mb0cf);
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tmp = mfdcr (memcfgd);
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if (tmp & 0x00000001) {
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bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
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tot_size += bank_size;
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}
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mtdcr (memcfga, mem_mb1cf);
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tmp = mfdcr (memcfgd);
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if (tmp & 0x00000001) {
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bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
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tot_size += bank_size;
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}
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mtdcr (memcfga, mem_mb2cf);
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tmp = mfdcr (memcfgd);
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if (tmp & 0x00000001) {
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bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
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tot_size += bank_size;
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}
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mtdcr (memcfga, mem_mb3cf);
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tmp = mfdcr (memcfgd);
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if (tmp & 0x00000001) {
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bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
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tot_size += bank_size;
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}
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return tot_size;
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}
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/*
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* last_stage_init: final configurations (such as PHY etc)
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*
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*/
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int last_stage_init(void)
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{
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/* initialize the PHY */
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miiphy_reset(CONFIG_PHY_ADDR);
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miiphy_write(CONFIG_PHY_ADDR, PHY_BMCR,
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PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); /* AUTO neg */
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miiphy_write(CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08); /* LEDs */
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return 0; /* success */
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}
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216
board/csb272/init.S
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216
board/csb272/init.S
Normal file
@@ -0,0 +1,216 @@
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/******************************************************************************
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*
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* This source code has been made available to you by IBM on an AS-IS
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* basis. Anyone receiving this source is licensed under IBM
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* copyrights to use it in any way he or she deems fit, including
|
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* copying it, modifying it, compiling it, and redistributing it either
|
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* with or without modifications. No license under IBM patents or
|
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* patent applications is to be implied by the copyright license.
|
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*
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* Any user of this software should understand that IBM cannot provide
|
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* technical support for this software and will not be responsible for
|
||||
* any consequences resulting from the use of this software.
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*
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* Any person who transfers this source code or any derivative work
|
||||
* must include the IBM copyright notice, this paragraph, and the
|
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* preceding two paragraphs in the transferred software.
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*
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* COPYRIGHT I B M CORPORATION 1995
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* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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*
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*****************************************************************************/
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#include <config.h>
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#include <ppc4xx.h>
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#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#define LI32(reg,val) \
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addis reg,0,val@h;\
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ori reg,reg,val@l
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#define WDCR_EBC(reg,val) \
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addi r4,0,reg;\
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mtdcr ebccfga,r4;\
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addis r4,0,val@h;\
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ori r4,r4,val@l;\
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mtdcr ebccfgd,r4
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#define WDCR_SDRAM(reg,val) \
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addi r4,0,reg;\
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mtdcr memcfga,r4;\
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addis r4,0,val@h;\
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ori r4,r4,val@l;\
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mtdcr memcfgd,r4
|
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|
||||
/******************************************************************************
|
||||
* Function: ext_bus_cntlr_init
|
||||
*
|
||||
* Description: Configures EBC Controller and a few basic chip selects.
|
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*
|
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* CS0 is setup to get the Boot Flash out of the addresss range
|
||||
* so that we may setup a stack. CS7 is setup so that we can
|
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* access and reset the hardware watchdog.
|
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*
|
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* IMPORTANT: For pass1 this code must run from
|
||||
* cache since you can not reliably change a peripheral banks
|
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* timing register (pbxap) while running code from that bank.
|
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* For ex., since we are running from ROM on bank 0, we can NOT
|
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* execute the code that modifies bank 0 timings from ROM, so
|
||||
* we run it from cache.
|
||||
*
|
||||
* Notes: Does NOT use the stack.
|
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*****************************************************************************/
|
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.section ".text"
|
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.align 2
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.globl ext_bus_cntlr_init
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.type ext_bus_cntlr_init, @function
|
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ext_bus_cntlr_init:
|
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mflr r0
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||||
/********************************************************************
|
||||
* Prefetch entire ext_bus_cntrl_init function into the icache.
|
||||
* This is necessary because we are going to change the same CS we
|
||||
* are executing from. Otherwise a CPU lockup may occur.
|
||||
*******************************************************************/
|
||||
bl ..getAddr
|
||||
..getAddr:
|
||||
mflr r3 /* get address of ..getAddr */
|
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|
||||
/* Calculate number of cache lines for this function */
|
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addi r4, 0, (((.Lfe0 - ..getAddr) / CFG_CACHELINE_SIZE) + 2)
|
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mtctr r4
|
||||
..ebcloop:
|
||||
icbt r0, r3 /* prefetch cache line for addr in r3*/
|
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addi r3, r3, CFG_CACHELINE_SIZE /* move to next cache line */
|
||||
bdnz ..ebcloop /* continue for $CTR cache lines */
|
||||
|
||||
/********************************************************************
|
||||
* Delay to ensure all accesses to ROM are complete before changing
|
||||
* bank 0 timings. 200usec should be enough.
|
||||
* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
|
||||
*******************************************************************/
|
||||
addis r3, 0, 0x0
|
||||
ori r3, r3, 0xA000 /* wait 200us from reset */
|
||||
mtctr r3
|
||||
..spinlp:
|
||||
bdnz ..spinlp /* spin loop */
|
||||
|
||||
/********************************************************************
|
||||
* SETUP CPC0_CR0
|
||||
*******************************************************************/
|
||||
LI32(r4, 0x007000c0)
|
||||
mtdcr cntrl0, r4
|
||||
|
||||
/********************************************************************
|
||||
* Setup CPC0_CR1: Change PCIINT signal to PerWE
|
||||
*******************************************************************/
|
||||
mfdcr r4, cntrl1
|
||||
ori r4, r4, 0x4000
|
||||
mtdcr cntrl1, r4
|
||||
|
||||
/********************************************************************
|
||||
* Setup External Bus Controller (EBC).
|
||||
*******************************************************************/
|
||||
WDCR_EBC(epcr, 0xd84c0000)
|
||||
/********************************************************************
|
||||
* Memory Bank 0 (Intel 28F128J3 Flash) initialization
|
||||
*******************************************************************/
|
||||
/*WDCR_EBC(pb0ap, 0x02869200)*/
|
||||
WDCR_EBC(pb0ap, 0x07869200)
|
||||
WDCR_EBC(pb0cr, 0xfe0bc000)
|
||||
/********************************************************************
|
||||
* Memory Bank 1 (Holtek HT6542B PS/2) initialization
|
||||
*******************************************************************/
|
||||
WDCR_EBC(pb1ap, 0x1f869200)
|
||||
WDCR_EBC(pb1cr, 0xf0818000)
|
||||
/********************************************************************
|
||||
* Memory Bank 2 (Epson S1D13506) initialization
|
||||
*******************************************************************/
|
||||
WDCR_EBC(pb2ap, 0x05860300)
|
||||
WDCR_EBC(pb2cr, 0xf045a000)
|
||||
/********************************************************************
|
||||
* Memory Bank 3 (Philips SJA1000 CAN Controllers) initialization
|
||||
*******************************************************************/
|
||||
WDCR_EBC(pb3ap, 0x0387d200)
|
||||
WDCR_EBC(pb3cr, 0xf021c000)
|
||||
/********************************************************************
|
||||
* Memory Bank 4-7 (Unused) initialization
|
||||
*******************************************************************/
|
||||
WDCR_EBC(pb4ap, 0)
|
||||
WDCR_EBC(pb4cr, 0)
|
||||
WDCR_EBC(pb5ap, 0)
|
||||
WDCR_EBC(pb5cr, 0)
|
||||
WDCR_EBC(pb6ap, 0)
|
||||
WDCR_EBC(pb6cr, 0)
|
||||
WDCR_EBC(pb7ap, 0)
|
||||
WDCR_EBC(pb7cr, 0)
|
||||
|
||||
/* We are all done */
|
||||
mtlr r0 /* Restore link register */
|
||||
blr /* Return to calling function */
|
||||
.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
|
||||
/* end ext_bus_cntlr_init() */
|
||||
|
||||
/******************************************************************************
|
||||
* Function: sdram_init
|
||||
*
|
||||
* Description: Configures SDRAM memory banks.
|
||||
*
|
||||
* Notes: Does NOT use the stack.
|
||||
*****************************************************************************/
|
||||
.section ".text"
|
||||
.align 2
|
||||
.globl sdram_init
|
||||
.type sdram_init, @function
|
||||
sdram_init:
|
||||
|
||||
/*
|
||||
* Disable memory controller to allow
|
||||
* values to be changed.
|
||||
*/
|
||||
WDCR_SDRAM(mem_mcopt1, 0x00000000)
|
||||
|
||||
/*
|
||||
* Configure Memory Banks
|
||||
*/
|
||||
WDCR_SDRAM(mem_mb0cf, 0x00084001)
|
||||
WDCR_SDRAM(mem_mb1cf, 0x00000000)
|
||||
WDCR_SDRAM(mem_mb2cf, 0x00000000)
|
||||
WDCR_SDRAM(mem_mb3cf, 0x00000000)
|
||||
|
||||
/*
|
||||
* Set up SDTR1 (SDRAM Timing Register)
|
||||
*/
|
||||
WDCR_SDRAM(mem_sdtr1, 0x00854009)
|
||||
|
||||
/*
|
||||
* Set RTR (Refresh Timing Register)
|
||||
*/
|
||||
WDCR_SDRAM(mem_rtr, 0x10000000)
|
||||
/* WDCR_SDRAM(mem_rtr, 0x05f00000) */
|
||||
|
||||
/********************************************************************
|
||||
* Delay to ensure 200usec have elapsed since reset. Assume worst
|
||||
* case that the core is running 200Mhz:
|
||||
* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
|
||||
*******************************************************************/
|
||||
addis r3, 0, 0x0000
|
||||
ori r3, r3, 0xA000 /* Wait >200us from reset */
|
||||
mtctr r3
|
||||
..spinlp2:
|
||||
bdnz ..spinlp2 /* spin loop */
|
||||
|
||||
/********************************************************************
|
||||
* Set memory controller options reg, MCOPT1.
|
||||
*******************************************************************/
|
||||
WDCR_SDRAM(mem_mcopt1,0x80800000)
|
||||
|
||||
..sdri_done:
|
||||
blr /* Return to calling function */
|
||||
.Lfe1: .size sdram_init,.Lfe1-sdram_init
|
||||
/* end sdram_init() */
|
||||
151
board/csb272/u-boot.lds
Normal file
151
board/csb272/u-boot.lds
Normal file
@@ -0,0 +1,151 @@
|
||||
/*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
.resetvec 0xFFFFFFFC :
|
||||
{
|
||||
*(.resetvec)
|
||||
} = 0xffff
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
board/csb272/init.o (.text)
|
||||
cpu/ppc4xx/kgdb.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
cpu/ppc4xx/405gp_enet.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
|
||||
lib_ppc/extable.o (.text)
|
||||
lib_ppc/board.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
/* . = env_offset;*/
|
||||
/* common/environment.o(.text)*/
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
@@ -312,7 +312,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
|
||||
case (FLASH_AM160LV | FLASH_AM160B):
|
||||
setup_offset = UNLOCK_ADDR1; /* just the adress for setup_cmd differs */
|
||||
case FLASH_AMDL323B:
|
||||
/*
|
||||
/*
|
||||
* Disable interrupts which might cause a timeout
|
||||
* here. Remember that our exception vectors are
|
||||
* at address 0 in the flash, and we don't want a
|
||||
@@ -416,7 +416,7 @@ static int write_word (flash_info_t * info, ulong dest, ushort data)
|
||||
if ((*(__u16 *) (dest) & data) != data)
|
||||
return ERR_NOT_ERASED;
|
||||
|
||||
/*
|
||||
/*
|
||||
* Disable interrupts which might cause a timeout
|
||||
* here. Remember that our exception vectors are
|
||||
* at address 0 in the flash, and we don't want a
|
||||
|
||||
@@ -12,7 +12,7 @@
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
@@ -29,7 +29,7 @@ SECTIONS
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
.text :
|
||||
{
|
||||
cpu/arm720t/start.o (.text)
|
||||
*(.text)
|
||||
@@ -52,17 +52,17 @@ SECTIONS
|
||||
__bss_start = .;
|
||||
.bss : { *(.bss) }
|
||||
_end = .;
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_info 0 : { *(.debug_info) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_info 0 : { *(.debug_info) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user