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x86: minnowmax: Add access to GPIOs E0, E1, E2

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These GPIOs are accessible on the pin header. Add pinctrl settings for them
so that we they can be adjusted using the 'gpio' command.

Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass 2015-08-22 15:58:53 -06:00
parent bccdf1de75
commit cce7e0fa2b
1 changed files with 27 additions and 0 deletions
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27
arch/x86/dts/minnowmax.dts
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@ -30,6 +30,33 @@
compatible = "intel,x86-pinctrl";
io-base = <0x4c>;
/* GPIO E0 */
soc_gpio_s5_0@0 {
gpio-offset = <0x80 0>;
pad-offset = <0x1d0>;
mode-gpio;
output-value = <0>;
direction = <PIN_OUTPUT>;
};
/* GPIO E1 */
soc_gpio_s5_1@0 {
gpio-offset = <0x80 1>;
pad-offset = <0x210>;
mode-gpio;
output-value = <0>;
direction = <PIN_OUTPUT>;
};
/* GPIO E2 */
soc_gpio_s5_2@0 {
gpio-offset = <0x80 2>;
pad-offset = <0x1e0>;
mode-gpio;
output-value = <0>;
direction = <PIN_OUTPUT>;
};
pin_usb_host_en0@0 {
gpio-offset = <0x80 8>;
pad-offset = <0x260>;