Merge branch 'master' of git://git.denx.de/u-boot-tegra
This commit is contained in:
Tom Rini
75
include/configs/p2571.h
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75
include/configs/p2571.h
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/*
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* (C) Copyright 2013-2015
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _P2571_H
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#define _P2571_H
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#include <linux/sizes.h>
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/* enable PMIC */
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#define CONFIG_MAX77620_POWER
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#include "tegra210-common.h"
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/* High-level configuration options */
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#define V_PROMPT "Tegra210 (P2571) # "
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#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2571"
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/* Board-specific serial config */
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#define CONFIG_SERIAL_MULTI
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#define CONFIG_TEGRA_ENABLE_UARTA
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#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
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/* I2C */
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#define CONFIG_SYS_I2C_TEGRA
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#define CONFIG_CMD_I2C
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/* SD/MMC */
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#define CONFIG_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_TEGRA_MMC
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#define CONFIG_CMD_MMC
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/* Environment in eMMC, at the end of 2nd "boot sector" */
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#define CONFIG_ENV_IS_IN_MMC
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_SYS_MMC_ENV_PART 2
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#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
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/* SPI */
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#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */
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#define CONFIG_TEGRA114_SPI_CTRLS 6
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#define CONFIG_SPI_FLASH_WINBOND
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
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#define CONFIG_SF_DEFAULT_SPEED 24000000
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#define CONFIG_CMD_SPI
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#define CONFIG_CMD_SF
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#define CONFIG_SPI_FLASH_SIZE (4 << 20)
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/* USB2.0 Host support */
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#define CONFIG_USB_EHCI
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#define CONFIG_USB_EHCI_TEGRA
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#define CONFIG_USB_STORAGE
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#define CONFIG_CMD_USB
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/* USB networking support */
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#define CONFIG_USB_HOST_ETHER
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#define CONFIG_USB_ETHER_ASIX
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/* General networking support */
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#define CONFIG_CMD_DHCP
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/*
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* TODO(twarren@nvidia.com) - add tegra-common-usb-gadget.h back
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* breaks 64-bit build in ci_udc.c
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*/
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#include "tegra-common-post.h"
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#define COUNTER_FREQUENCY 38400000
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#endif /* _P2571_H */
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@@ -62,11 +62,19 @@
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#define CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
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#endif
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#ifdef CONFIG_ARM64
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#define FDT_HIGH "ffffffffffffffff"
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#define INITRD_HIGH "ffffffffffffffff"
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#else
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#define FDT_HIGH "ffffffff"
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#define INITRD_HIGH "ffffffff"
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#endif
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#define CONFIG_EXTRA_ENV_SETTINGS \
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TEGRA_DEVICE_SETTINGS \
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MEM_LAYOUT_ENV_SETTINGS \
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"fdt_high=ffffffff\0" \
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"initrd_high=ffffffff\0" \
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"fdt_high=" FDT_HIGH "\0" \
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"initrd_high=" INITRD_HIGH "\0" \
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BOOTENV \
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BOARD_EXTRA_ENV_SETTINGS \
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CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
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@@ -18,8 +18,11 @@
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#include <asm/arch/tegra.h> /* get chip and board defs */
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/* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */
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#ifndef CONFIG_ARM64
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#define CONFIG_SYS_TIMER_RATE 1000000
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#define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE
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#endif
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/*
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* Display CPU and Board information
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@@ -43,7 +46,9 @@
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#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
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#endif
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#ifndef CONFIG_ARM64
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#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */
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#endif
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/*
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* NS16550 Configuration
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@@ -101,9 +106,11 @@
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#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
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#ifndef CONFIG_ARM64
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_USE_ARCH_MEMCPY
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#endif
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#endif
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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@@ -26,7 +26,7 @@
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_SYS_TEXT_BASE 0x8010E000
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#define CONFIG_SYS_TEXT_BASE 0x80110000
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/*
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* Memory layout for where various images get loaded by boot scripts:
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76
include/configs/tegra210-common.h
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76
include/configs/tegra210-common.h
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@@ -0,0 +1,76 @@
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/*
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* (C) Copyright 2013-2015
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _TEGRA210_COMMON_H_
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#define _TEGRA210_COMMON_H_
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#include "tegra-common.h"
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/* Cortex-A57 uses a cache line size of 64 bytes */
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#define CONFIG_SYS_CACHELINE_SIZE 64
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/*
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* NS16550 Configuration
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*/
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#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_STACKBASE 0x82800000 /* 40MB */
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_SYS_TEXT_BASE 0x8010E000
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/* Generic Interrupt Controller */
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#define CONFIG_GICV2
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/*
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* Memory layout for where various images get loaded by boot scripts:
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*
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* scriptaddr can be pretty much anywhere that doesn't conflict with something
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* else. Put it above BOOTMAPSZ to eliminate conflicts.
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*
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* pxefile_addr_r can be pretty much anywhere that doesn't conflict with
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* something else. Put it above BOOTMAPSZ to eliminate conflicts.
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*
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* kernel_addr_r must be within the first 128M of RAM in order for the
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* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
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* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
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* should not overlap that area, or the kernel will have to copy itself
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* somewhere else before decompression. Similarly, the address of any other
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* data passed to the kernel shouldn't overlap the start of RAM. Pushing
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* this up to 16M allows for a sizable kernel to be decompressed below the
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* compressed load address.
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*
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* fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
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* the compressed kernel to be up to 16M too.
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*
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* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
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* for the FDT/DTB to be up to 1M, which is hopefully plenty.
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*/
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#define CONFIG_LOADADDR 0x81000000
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#define MEM_LAYOUT_ENV_SETTINGS \
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"scriptaddr=0x90000000\0" \
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"pxefile_addr_r=0x90100000\0" \
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"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
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"fdt_addr_r=0x82000000\0" \
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"ramdisk_addr_r=0x82100000\0"
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/* Defines for SPL */
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#define CONFIG_SPL_TEXT_BASE 0x80108000
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#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
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#define CONFIG_SPL_STACK 0x800ffffc
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/* For USB EHCI controller */
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#define CONFIG_EHCI_IS_TDI
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#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
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#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
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#endif /* _TEGRA210_COMMON_H_ */
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