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Merge branch 'master' of git://git.denx.de/u-boot-tegra

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This commit is contained in:
Tom Rini
2015-07-29 18:58:39 -04:00
parent 488d19cbca 873e3ef90b
commit cc35734358
64 changed files with 4638 additions and 102 deletions
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11
arch/arm/Kconfig
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@@ -687,17 +687,6 @@ config ARCH_ZYNQMP
config TEGRA
bool "NVIDIA Tegra"
select SUPPORT_SPL
select SPL
select OF_CONTROL
select SPL_DISABLE_OF_CONTROL
select CPU_V7
select DM
select DM_SPI_FLASH
select DM_SERIAL
select DM_I2C
select DM_SPI
select DM_GPIO
config TARGET_VEXPRESS64_AEMV8A
bool "Support vexpress_aemv8a"

4
arch/arm/cpu/armv8/cache_v8.c
View File

@@ -25,9 +25,9 @@ void set_pgtable_section(u64 *page_table, u64 index, u64 section,
/* to activate the MMU we need to set up virtual memory */
static void mmu_setup(void)
{
int i, j, el;
bd_t *bd = gd->bd;
u64 *page_table = (u64 *)gd->arch.tlb_addr;
u64 *page_table = (u64 *)gd->arch.tlb_addr, i, j;
int el;
/* Setup an identity-mapping for all spaces */
for (i = 0; i < (PGTABLE_SIZE >> 3); i++) {

3
arch/arm/dts/Makefile
View File

@@ -32,7 +32,8 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra114-dalmore.dtb \
tegra124-jetson-tk1.dtb \
tegra124-nyan-big.dtb \
tegra124-venice2.dtb
tegra124-venice2.dtb \
tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ph1-sld3-ref.dtb \
uniphier-ph1-pro4-ref.dtb \

106
arch/arm/dts/tegra210-p2571.dts Normal file
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@@ -0,0 +1,106 @@
/dts-v1/;
#include "tegra210.dtsi"
/ {
model = "NVIDIA P2571";
compatible = "nvidia,p2571", "nvidia,tegra210";
chosen {
stdout-path = &uarta;
};
aliases {
i2c0 = "/i2c@0,7000d000";
i2c1 = "/i2c@0,7000c000";
i2c2 = "/i2c@0,7000c400";
i2c3 = "/i2c@0,7000c500";
i2c4 = "/i2c@0,7000c700";
i2c5 = "/i2c@0,7000d100";
sdhci0 = "/sdhci@0,700b0600";
sdhci1 = "/sdhci@0,700b0000";
spi0 = "/spi@0,7000d400";
spi1 = "/spi@0,7000da00";
spi2 = "/spi@0,70410000";
usb0 = "/usb@0,7d000000";
};
memory {
reg = <0x0 0x80000000 0x0 0xc0000000>;
};
i2c@0,7000c000 {
status = "okay";
clock-frequency = <100000>;
};
i2c@0,7000c400 {
status = "okay";
clock-frequency = <100000>;
};
i2c@0,7000c500 {
status = "okay";
clock-frequency = <100000>;
};
i2c@0,7000c700 {
status = "okay";
clock-frequency = <100000>;
};
i2c@0,7000d000 {
status = "okay";
clock-frequency = <400000>;
};
i2c@0,7000d100 {
status = "okay";
clock-frequency = <400000>;
};
spi@0,7000d400 {
status = "okay";
spi-max-frequency = <25000000>;
};
spi@0,7000da00 {
status = "okay";
spi-max-frequency = <25000000>;
};
spi@0,70410000 {
status = "okay";
spi-max-frequency = <24000000>;
};
sdhci@0,700b0000 {
status = "okay";
cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
power-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
sdhci@0,700b0600 {
status = "okay";
bus-width = <8>;
};
usb@0,7d000000 {
status = "okay";
dr_mode = "otg";
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock@0 {
compatible = "fixed-clock";
reg = <0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
};

283
arch/arm/dts/tegra210.dtsi Normal file
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@@ -0,0 +1,283 @@
#include <dt-bindings/clock/tegra210-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
#include "skeleton.dtsi"
/ {
compatible = "nvidia,tegra210";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
gic: interrupt-controller@0,50041000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0x50041000 0x0 0x1000>,
<0x0 0x50042000 0x0 0x2000>,
<0x0 0x50044000 0x0 0x2000>,
<0x0 0x50046000 0x0 0x2000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
interrupt-parent = <&gic>;
};
tegra_car: clock@0,60006000 {
compatible = "nvidia,tegra210-car";
reg = <0x0 0x60006000 0x0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
gpio: gpio@0,6000d000 {
compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";
reg = <0x0 0x6000d000 0x0 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
};
i2c@0,7000c000 {
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x7000c000 0x0 0x100>;
interrupts = <0 38 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 12>;
status = "disabled";
};
i2c@0,7000c400 {
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x7000c400 0x0 0x100>;
interrupts = <0 84 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 54>;
status = "disabled";
};
i2c@0,7000c500 {
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x7000c500 0x0 0x100>;
interrupts = <0 92 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 67>;
status = "disabled";
};
i2c@0,7000c700 {
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x7000c700 0x0 0x100>;
interrupts = <0 120 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 103>;
status = "disabled";
};
i2c@0,7000d000 {
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x7000d000 0x0 0x100>;
interrupts = <0 53 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 47>;
status = "disabled";
};
i2c@0,7000d100 {
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x7000d100 0x0 0x100>;
interrupts = <0 53 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 47>;
status = "disabled";
};
uarta: serial@0,70006000 {
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
reg = <0x0 0x70006000 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_UARTA>;
resets = <&tegra_car 6>;
reset-names = "serial";
status = "disabled";
};
uartb: serial@0,70006040 {
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
reg = <0x0 0x70006040 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_UARTB>;
resets = <&tegra_car 7>;
reset-names = "serial";
status = "disabled";
};
uartc: serial@0,70006200 {
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
reg = <0x0 0x70006200 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_UARTC>;
resets = <&tegra_car 55>;
reset-names = "serial";
status = "disabled";
};
uartd: serial@0,70006300 {
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
reg = <0x0 0x70006300 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_UARTD>;
resets = <&tegra_car 65>;
reset-names = "serial";
status = "disabled";
};
spi@0,7000d400 {
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
reg = <0x0 0x7000d400 0x0 0x200>;
interrupts = <0 59 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA210_CLK_SBC1>;
resets = <&tegra_car 41>;
reset-names = "spi";
status = "disabled";
};
spi@0,7000d600 {
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
reg = <0x0 0x7000d600 0x0 0x200>;
interrupts = <0 82 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA210_CLK_SBC2>;
resets = <&tegra_car 44>;
reset-names = "spi";
status = "disabled";
};
spi@0,7000d800 {
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
reg = <0x0 0x7000d800 0x0 0x200>;
interrupts = <0 83 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA210_CLK_SBC3>;
resets = <&tegra_car 46>;
reset-names = "spi";
status = "disabled";
};
spi@0,7000da00 {
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
reg = <0x0 0x7000da00 0x0 0x200>;
interrupts = <0 93 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA210_CLK_SBC4>;
resets = <&tegra_car 68>;
reset-names = "spi";
status = "disabled";
};
spi@0,70410000 {
compatible = "nvidia,tegra210-qspi";
reg = <0x0 0x70410000 0x0 0x1000>;
interrupts = <0 10 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 211>;
status = "disabled";
};
padctl: padctl@0,7009f000 {
compatible = "nvidia,tegra210-xusb-padctl";
reg = <0x0 0x7009f000 0x0 0x1000>;
resets = <&tegra_car 142>;
reset-names = "padctl";
#phy-cells = <1>;
};
sdhci@0,700b0000 {
compatible = "nvidia,tegra210-sdhci";
reg = <0x0 0x700b0000 0x0 0x200>;
interrupts = <0 14 0x04>;
clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
resets = <&tegra_car 14>;
reset-names = "sdhci";
status = "disabled";
};
sdhci@0,700b0200 {
compatible = "nvidia,tegra210-sdhci";
reg = <0x0 0x700b0200 0x0 0x200>;
interrupts = <0 15 0x04>;
clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
resets = <&tegra_car 9>;
reset-names = "sdhci";
status = "disabled";
};
sdhci@0,700b0400 {
compatible = "nvidia,tegra210-sdhci";
reg = <0x0 0x700b0400 0x0 0x200>;
interrupts = <0 19 0x04>;
clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;
resets = <&tegra_car 69>;
reset-names = "sdhci";
status = "disabled";
};
sdhci@0,700b0600 {
compatible = "nvidia,tegra210-sdhci";
reg = <0x0 0x700b0600 0x0 0x200>;
interrupts = <0 31 0x04>;
clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
resets = <&tegra_car 15>;
reset-names = "sdhci";
status = "disabled";
};
usb@0,7d000000 {
compatible = "nvidia,tegra210-ehci";
reg = <0x0 0x7d000000 0x0 0x4000>;
interrupts = <0 20 0x04>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA210_CLK_USBD>;
resets = <&tegra_car 22>;
reset-names = "usb";
status = "disabled";
};
usb@0,7d004000 {
compatible = "nvidia,tegra210-ehci";
reg = <0x0 0x7d004000 0x0 0x4000>;
interrupts = < 53 >;
phy_type = "utmi";
clocks = <&tegra_car TEGRA210_CLK_USB2>;
resets = <&tegra_car 58>;
reset-names = "usb";
status = "disabled";
};
};

6
arch/arm/include/asm/arch-tegra/ap.h
View File

@@ -1,5 +1,5 @@
/*
* (C) Copyright 2010-2011
* (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -24,8 +24,6 @@
#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
#define PG_UP_TAG_0 0x0
#define CORESIGHT_UNLOCK 0xC5ACCE55;
/* AP base physical address of internal SRAM */
#define NV_PA_BASE_SRAM 0x40000000
@@ -66,7 +64,7 @@ int tegra_get_sku_info(void);
/* Do any chip-specific cache config */
void config_cache(void);
#if defined(CONFIG_TEGRA124)
#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
/* Do chip-specific vpr config */
void config_vpr(void);
#else

36
arch/arm/include/asm/arch-tegra/clk_rst.h
View File

@@ -48,6 +48,7 @@ enum {
TEGRA_CLK_REGS_VW = 2, /* Number of clock enable regs V/W */
TEGRA_CLK_SOURCES_VW = 32, /* Number of ppl clock sources V/W */
TEGRA_CLK_SOURCES_X = 32, /* Number of ppl clock sources X */
TEGRA_CLK_SOURCES_Y = 18, /* Number of ppl clock sources Y */
};
/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
@@ -94,7 +95,15 @@ struct clk_rst_ctlr {
uint crc_rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */
uint crc_rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */
uint crc_reserved21[23]; /* _reserved_21, 0x298-2f0 */
uint crc_clk_out_enb_y; /* _CLK_OUT_ENB_Y_0, 0x298 */
uint crc_clk_enb_y_set; /* _CLK_ENB_Y_SET_0, 0x29c */
uint crc_clk_enb_y_clr; /* _CLK_ENB_Y_CLR_0, 0x2a0 */
uint crc_rst_devices_y; /* _RST_DEVICES_Y_0, 0x2a4 */
uint crc_rst_dev_y_set; /* _RST_DEV_Y_SET_0, 0x2a8 */
uint crc_rst_dev_y_clr; /* _RST_DEV_Y_CLR_0, 0x2ac */
uint crc_reserved21[17]; /* _reserved_21, 0x2b0-2f0 */
uint crc_dfll_base; /* _DFLL_BASE_0, 0x2f4 */
@@ -136,7 +145,7 @@ struct clk_rst_ctlr {
struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW];
/* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */
struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW];
/* Additional (T114) registers */
/* Additional (T114+) registers */
uint crc_rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET_0, 0x450 */
uint crc_rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR_0, 0x454 */
uint crc_rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET_0, 0x458 */
@@ -207,9 +216,18 @@ struct clk_rst_ctlr {
u32 _rsv32_1[7]; /* 0x574-58c */
struct clk_pll_simple plldp; /* _PLLDP_BASE, 0x590 _PLLDP_MISC */
u32 crc_plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */
u32 _rsrv32_2[25];
/* Tegra124 */
uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x678 */
/* Tegra124+ - skip to 0x600 here for new CLK_SOURCE_ regs */
uint _rsrv32_2[25]; /* _0x59C - 0x5FC */
uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x67C */
/* Tegra210 - skip to 0x694 here for new CLK_SOURCE_ regs */
uint crc_reserved61[5]; /* _reserved_61, 0x680 - 0x690 */
/*
* NOTE: PLLA1 regs are in the middle of this Y region. Break this in
* two later if PLLA1 is needed, but for now this is cleaner.
*/
uint crc_clk_src_y[TEGRA_CLK_SOURCES_Y]; /* SPARE1, etc, 0x694-0x6D8 */
};
/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
@@ -233,6 +251,8 @@ struct clk_rst_ctlr {
#define PLL_DIVP_SHIFT 20
#define PLL_DIVP_MASK (7U << PLL_DIVP_SHIFT)
/* Special case for T210 PLLU DIVP */
#define PLLU_DIVP_SHIFT 16
#define PLL_DIVN_SHIFT 8
#define PLL_DIVN_MASK (0x3ffU << PLL_DIVN_SHIFT)
@@ -261,6 +281,12 @@ struct clk_rst_ctlr {
#define PLL_LFCON_SHIFT 4
#define PLL_LFCON_MASK (15U << PLL_LFCON_SHIFT)
/* CPCON/LFCON replaced by KCP/KVCO in T210 PLLU */
#define PLLU_KVCO_SHIFT 24
#define PLLU_KVCO_MASK (3U << PLLU_KVCO_SHIFT)
#define PLLU_KCP_SHIFT 25
#define PLLU_KCP_MASK (1U << PLLU_KCP_SHIFT)
#define PLLU_VCO_FREQ_SHIFT 20
#define PLLU_VCO_FREQ_MASK (1U << PLLU_VCO_FREQ_SHIFT)

3
arch/arm/include/asm/arch-tegra/gp_padctrl.h
View File

@@ -1,5 +1,5 @@
/*
* (C) Copyright 2010-2012
* (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -21,5 +21,6 @@
#define CHIPID_TEGRA30 0x30
#define CHIPID_TEGRA114 0x35
#define CHIPID_TEGRA124 0x40
#define CHIPID_TEGRA210 0x21
#endif /* _TEGRA_GP_PADCTRL_H_ */

7
arch/arm/include/asm/arch-tegra/pmc.h
View File

@@ -1,5 +1,5 @@
/*
* (C) Copyright 2010,2011,2014
* (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -294,6 +294,7 @@ struct pmc_ctlr {
#define CRAIL 0
#define CE0 14
#define C0NC 15
#define SOR 17
#define PMC_XOFS_SHIFT 1
#define PMC_XOFS_MASK (0x3F << PMC_XOFS_SHIFT)
@@ -303,7 +304,7 @@ struct pmc_ctlr {
#define TIMER_MULT_MASK (3 << TIMER_MULT_SHIFT)
#define TIMER_MULT_CPU_SHIFT 2
#define TIMER_MULT_CPU_MASK (3 << TIMER_MULT_CPU_SHIFT)
#elif defined(CONFIG_TEGRA124)
#elif defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
#define TIMER_MULT_SHIFT 0
#define TIMER_MULT_MASK (7 << TIMER_MULT_SHIFT)
#define TIMER_MULT_CPU_SHIFT 3
@@ -314,7 +315,7 @@ struct pmc_ctlr {
#define MULT_2 1
#define MULT_4 2
#define MULT_8 3
#if defined(CONFIG_TEGRA124)
#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
#define MULT_16 4
#endif

4
arch/arm/include/asm/arch-tegra/tegra.h
View File

@@ -1,5 +1,5 @@
/*
* (C) Copyright 2010,2011
* (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -74,6 +74,7 @@ enum {
SKU_ID_T114_ENG = 0x00, /* Dalmore value, unfused */
SKU_ID_T114_1 = 0x01,
SKU_ID_T124_ENG = 0x00, /* Venice2 value, unfused */
SKU_ID_T210_ENG = 0x00, /* unfused value TBD */
};
/*
@@ -88,6 +89,7 @@ enum {
TEGRA_SOC_T30,
TEGRA_SOC_T114,
TEGRA_SOC_T124,
TEGRA_SOC_T210,
TEGRA_SOC_CNT,
TEGRA_SOC_UNKNOWN = -1,

3
arch/arm/include/asm/arch-tegra/usb.h
View File

@@ -266,6 +266,9 @@ struct usb_ctlr {
/* USBx_UTMIP_BIAS_CFG1_0 */
#define UTMIP_FORCE_PDTRK_POWERDOWN 1
#define UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT 8
#define UTMIP_BIAS_DEBOUNCE_TIMESCALE_MASK \
(0x3f << UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT)
#define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3
#define UTMIP_BIAS_PDTRK_COUNT_MASK \
(0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)

91
arch/arm/include/asm/arch-tegra210/ahb.h Normal file
View File

@@ -0,0 +1,91 @@
/*
* (C) Copyright 2013-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA210_AHB_H_
#define _TEGRA210_AHB_H_
struct ahb_ctlr {
u32 reserved0; /* 00h */
u32 arbitration_disable; /* _ARBITRATION_DISABLE_0, 04h */
u32 arbitration_priority_ctrl; /* _ARBITRATION_PRIORITY_CTRL_0,08h */
u32 arbitration_usr_protect; /* _ARBITRATION_USR_PROTECT_0, 0ch */
u32 gizmo_ahb_mem; /* _GIZMO_AHB_MEM_0, 10h */
u32 gizmo_apb_dma; /* _GIZMO_APB_DMA_0, 14h */
u32 reserved6[2]; /* 18h, 1ch */
u32 gizmo_usb; /* _GIZMO_USB_0, 20h */
u32 gizmo_ahb_xbar_bridge; /* _GIZMO_AHB_XBAR_BRIDGE_0, 24h */
u32 gizmo_cpu_ahb_bridge; /* _GIZMO_CPU_AHB_BRIDGE_0, 28h */
u32 gizmo_cop_ahb_bridge; /* _GIZMO_COP_AHB_BRIDGE_0, 2ch */
u32 gizmo_xbar_apb_ctlr; /* _GIZMO_XBAR_APB_CTLR_0, 30h */
u32 gizmo_vcp_ahb_bridge; /* _GIZMO_VCP_AHB_BRIDGE_0, 34h */
u32 reserved13[2]; /* 38h, 3ch */
u32 gizmo_nand; /* _GIZMO_NAND_0, 40h */
u32 reserved15; /* 44h */
u32 gizmo_sdmmc4; /* _GIZMO_SDMMC4_0, 48h */
u32 reserved17; /* 4ch */
u32 gizmo_se; /* _GIZMO_SE_0, 50h */
u32 gizmo_tzram; /* _GIZMO_TZRAM_0, 54h */
u32 reserved20[3]; /* 58h, 5ch, 60h */
u32 gizmo_bsev; /* _GIZMO_BSEV_0, 64h */
u32 reserved22[3]; /* 68h, 6ch, 70h */
u32 gizmo_bsea; /* _GIZMO_BSEA_0, 74h */
u32 gizmo_nor; /* _GIZMO_NOR_0, 78h */
u32 gizmo_usb2; /* _GIZMO_USB2_0, 7ch */
u32 gizmo_usb3; /* _GIZMO_USB3_0, 80h */
u32 gizmo_sdmmc1; /* _GIZMO_SDMMC1_0, 84h */
u32 gizmo_sdmmc2; /* _GIZMO_SDMMC2_0, 88h */
u32 gizmo_sdmmc3; /* _GIZMO_SDMMC3_0, 8ch */
u32 reserved30[13]; /* 90h ~ c0h */
u32 ahb_wrq_empty; /* _AHB_WRQ_EMPTY_0, c4h */
u32 reserved32[5]; /* c8h ~ d8h */
u32 ahb_mem_prefetch_cfg_x; /* _AHB_MEM_PREFETCH_CFG_X_0, dch */
u32 arbitration_xbar_ctrl; /* _ARBITRATION_XBAR_CTRL_0, e0h */
u32 ahb_mem_prefetch_cfg3; /* _AHB_MEM_PREFETCH_CFG3_0, e4h */
u32 ahb_mem_prefetch_cfg4; /* _AHB_MEM_PREFETCH_CFG3_0, e8h */
u32 avp_ppcs_rd_coh_status; /* _AVP_PPCS_RD_COH_STATUS_0, ech */
u32 ahb_mem_prefetch_cfg1; /* _AHB_MEM_PREFETCH_CFG1_0, f0h */
u32 ahb_mem_prefetch_cfg2; /* _AHB_MEM_PREFETCH_CFG2_0, f4h */
u32 ahbslvmem_status; /* _AHBSLVMEM_STATUS_0, f8h */
/* _ARBITRATION_AHB_MEM_WRQUE_MST_ID_0, fch */
u32 arbitration_ahb_mem_wrque_mst_id;
u32 arbitration_cpu_abort_addr; /* _ARBITRATION_CPU_ABORT_ADDR_0,100h */
u32 arbitration_cpu_abort_info; /* _ARBITRATION_CPU_ABORT_INFO_0,104h */
u32 arbitration_cop_abort_addr; /* _ARBITRATION_COP_ABORT_ADDR_0,108h */
u32 arbitration_cop_abort_info; /* _ARBITRATION_COP_ABORT_INFO_0,10ch */
u32 reserved46[4]; /* 110h ~ 11ch */
u32 avpc_mccif_fifoctrl; /* _AVPC_MCCIF_FIFOCTRL_0, 120h */
u32 timeout_wcoal_avpc; /* _TIMEOUT_WCOAL_AVPC_0, 124h */
u32 mpcorelp_mccif_fifoctrl; /* _MPCORELP_MCCIF_FIFOCTRL_0, 128h */
u32 mpcore_mccif_fifoctrl; /* _MPCORE_MCCIF_FIFOCTRL_0, 12ch */
u32 axicif_fastsync_ctrl; /* AXICIF_FASTSYNC_CTRL_0, 130h */
u32 axicif_fastsync_statistics; /* _AXICIF_FASTSYNC_STATISTICS_0,134h */
/* _AXICIF_FASTSYNC0_CPUCLK_TO_MCCLK_0, 138h */
u32 axicif_fastsync0_cpuclk_to_mcclk;
/* _AXICIF_FASTSYNC1_CPUCLK_TO_MCCLK_0, 13ch */
u32 axicif_fastsync1_cpuclk_to_mcclk;
/* _AXICIF_FASTSYNC2_CPUCLK_TO_MCCLK_0, 140h */
u32 axicif_fastsync2_cpuclk_to_mcclk;
/* _AXICIF_FASTSYNC0_MCCLK_TO_CPUCLK_0, 144h */
u32 axicif_fastsync0_mcclk_to_cpuclk;
/* _AXICIF_FASTSYNC1_MCCLK_TO_CPUCLK_0, 148h */
u32 axicif_fastsync1_mcclk_to_cpuclk;
/* _AXICIF_FASTSYNC2_MCCLK_TO_CPUCLK_0, 14ch */
u32 axicif_fastsync2_mcclk_to_cpuclk;
};
#define PPSB_STOPCLK_ENABLE (1 << 2)
#define GIZ_ENABLE_SPLIT (1 << 0)
#define GIZ_ENB_FAST_REARB (1 << 2)
#define GIZ_DONT_SPLIT_AHB_WR (1 << 7)
#define GIZ_USB_IMMEDIATE (1 << 18)
/* AHB_ARBITRATION_XBAR_CTRL_0 0xe0 */
#define ARBITRATION_XBAR_CTRL_PPSB_ENABLE (1 << 2)
#endif /* _TEGRA210_AHB_H_ */

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/*
* (C) Copyright 2013-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* Tegra210 clock PLL tables */
#ifndef _TEGRA210_CLOCK_TABLES_H_
#define _TEGRA210_CLOCK_TABLES_H_
/* The PLLs supported by the hardware */
enum clock_id {
CLOCK_ID_FIRST,
CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
CLOCK_ID_MEMORY,
CLOCK_ID_PERIPH,
CLOCK_ID_AUDIO,
CLOCK_ID_USB,
CLOCK_ID_DISPLAY,
/* now the simple ones */
CLOCK_ID_FIRST_SIMPLE,
CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
CLOCK_ID_EPCI,
CLOCK_ID_SFROM32KHZ,
/* These are the base clocks (inputs to the Tegra SoC) */
CLOCK_ID_32KHZ,
CLOCK_ID_OSC,
CLOCK_ID_COUNT, /* number of PLLs */
/*
* These are clock IDs that are used in table clock_source[][]
* but will not be assigned as a clock source for any peripheral.
*/
CLOCK_ID_DISPLAY2,
CLOCK_ID_CGENERAL_0,
CLOCK_ID_CGENERAL_1,
CLOCK_ID_CGENERAL2,
CLOCK_ID_CGENERAL3,
CLOCK_ID_CGENERAL4_0,
CLOCK_ID_CGENERAL4_1,
CLOCK_ID_CGENERAL4_2,
CLOCK_ID_MEMORY2,
CLOCK_ID_SRC2,
CLOCK_ID_NONE = -1,
};
/* The clocks supported by the hardware */
enum periph_id {
PERIPH_ID_FIRST,
/* Low word: 31:0 (DEVICES_L) */
PERIPH_ID_CPU = PERIPH_ID_FIRST,
PERIPH_ID_COP,
PERIPH_ID_TRIGSYS,
PERIPH_ID_ISPB,
PERIPH_ID_RESERVED4,
PERIPH_ID_TMR,
PERIPH_ID_UART1,
PERIPH_ID_UART2,
/* 8 */
PERIPH_ID_GPIO,
PERIPH_ID_SDMMC2,
PERIPH_ID_SPDIF,
PERIPH_ID_I2S2,
PERIPH_ID_I2C1,
PERIPH_ID_RESERVED13,
PERIPH_ID_SDMMC1,
PERIPH_ID_SDMMC4,
/* 16 */
PERIPH_ID_TCW,
PERIPH_ID_PWM,
PERIPH_ID_I2S3,
PERIPH_ID_RESERVED19,
PERIPH_ID_VI,
PERIPH_ID_RESERVED21,
PERIPH_ID_USBD,
PERIPH_ID_ISP,
/* 24 */
PERIPH_ID_RESERVED24,
PERIPH_ID_RESERVED25,
PERIPH_ID_DISP2,
PERIPH_ID_DISP1,
PERIPH_ID_HOST1X,
PERIPH_ID_VCP,
PERIPH_ID_I2S1,
PERIPH_ID_CACHE2,
/* Middle word: 63:32 (DEVICES_H) */
PERIPH_ID_MEM,
PERIPH_ID_AHBDMA,
PERIPH_ID_APBDMA,
PERIPH_ID_RESERVED35,
PERIPH_ID_RESERVED36,
PERIPH_ID_STAT_MON,
PERIPH_ID_RESERVED38,
PERIPH_ID_FUSE,
/* 40 */
PERIPH_ID_KFUSE,
PERIPH_ID_SBC1,
PERIPH_ID_SNOR,
PERIPH_ID_RESERVED43,
PERIPH_ID_SBC2,
PERIPH_ID_XIO,
PERIPH_ID_SBC3,
PERIPH_ID_I2C5,
/* 48 */
PERIPH_ID_DSI,
PERIPH_ID_RESERVED49,
PERIPH_ID_HSI,
PERIPH_ID_HDMI,
PERIPH_ID_CSI,
PERIPH_ID_RESERVED53,
PERIPH_ID_I2C2,
PERIPH_ID_UART3,
/* 56 */
PERIPH_ID_MIPI_CAL,
PERIPH_ID_EMC,
PERIPH_ID_USB2,
PERIPH_ID_USB3,
PERIPH_ID_RESERVED60,
PERIPH_ID_VDE,
PERIPH_ID_BSEA,
PERIPH_ID_BSEV,
/* Upper word 95:64 (DEVICES_U) */
PERIPH_ID_RESERVED64,
PERIPH_ID_UART4,
PERIPH_ID_UART5,
PERIPH_ID_I2C3,
PERIPH_ID_SBC4,
PERIPH_ID_SDMMC3,
PERIPH_ID_PCIE,
PERIPH_ID_OWR,
/* 72 */
PERIPH_ID_AFI,
PERIPH_ID_CORESIGHT,
PERIPH_ID_PCIEXCLK,
PERIPH_ID_AVPUCQ,
PERIPH_ID_LA,
PERIPH_ID_TRACECLKIN,
PERIPH_ID_SOC_THERM,
PERIPH_ID_DTV,
/* 80 */
PERIPH_ID_RESERVED80,
PERIPH_ID_I2CSLOW,
PERIPH_ID_DSIB,
PERIPH_ID_TSEC,
PERIPH_ID_RESERVED84,
PERIPH_ID_RESERVED85,
PERIPH_ID_RESERVED86,
PERIPH_ID_EMUCIF,
/* 88 */
PERIPH_ID_RESERVED88,
PERIPH_ID_XUSB_HOST,
PERIPH_ID_RESERVED90,
PERIPH_ID_MSENC,
PERIPH_ID_RESERVED92,
PERIPH_ID_RESERVED93,
PERIPH_ID_RESERVED94,
PERIPH_ID_XUSB_DEV,
PERIPH_ID_VW_FIRST,
/* V word: 31:0 */
PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
PERIPH_ID_CPULP,
PERIPH_ID_V_RESERVED2,
PERIPH_ID_MSELECT,
PERIPH_ID_V_RESERVED4,
PERIPH_ID_I2S4,
PERIPH_ID_I2S5,
PERIPH_ID_I2C4,
/* 104 */
PERIPH_ID_SBC5,
PERIPH_ID_SBC6,
PERIPH_ID_AHUB,
PERIPH_ID_APB2APE,
PERIPH_ID_V_RESERVED12,
PERIPH_ID_V_RESERVED13,
PERIPH_ID_V_RESERVED14,
PERIPH_ID_HDA2CODEC2X,
/* 112 */
PERIPH_ID_ATOMICS,
PERIPH_ID_V_RESERVED17,
PERIPH_ID_V_RESERVED18,
PERIPH_ID_V_RESERVED19,
PERIPH_ID_V_RESERVED20,
PERIPH_ID_V_RESERVED21,
PERIPH_ID_V_RESERVED22,
PERIPH_ID_ACTMON,
/* 120 */
PERIPH_ID_EXTPERIPH1,
PERIPH_ID_EXTPERIPH2,
PERIPH_ID_EXTPERIPH3,
PERIPH_ID_OOB,
PERIPH_ID_SATA,
PERIPH_ID_HDA,
PERIPH_ID_V_RESERVED30,
PERIPH_ID_V_RESERVED31,
/* W word: 31:0 */
PERIPH_ID_HDA2HDMICODEC,
PERIPH_ID_SATACOLD,
PERIPH_ID_W_RESERVED2,
PERIPH_ID_W_RESERVED3,
PERIPH_ID_W_RESERVED4,
PERIPH_ID_W_RESERVED5,
PERIPH_ID_W_RESERVED6,
PERIPH_ID_W_RESERVED7,
/* 136 */
PERIPH_ID_CEC,
PERIPH_ID_W_RESERVED9,
PERIPH_ID_W_RESERVED10,
PERIPH_ID_W_RESERVED11,
PERIPH_ID_W_RESERVED12,
PERIPH_ID_W_RESERVED13,
PERIPH_ID_XUSB_PADCTL,
PERIPH_ID_W_RESERVED15,
/* 144 */
PERIPH_ID_W_RESERVED16,
PERIPH_ID_W_RESERVED17,
PERIPH_ID_W_RESERVED18,
PERIPH_ID_W_RESERVED19,
PERIPH_ID_W_RESERVED20,
PERIPH_ID_ENTROPY,
PERIPH_ID_DDS,
PERIPH_ID_W_RESERVED23,
/* 152 */
PERIPH_ID_W_RESERVED24,
PERIPH_ID_W_RESERVED25,
PERIPH_ID_W_RESERVED26,
PERIPH_ID_DVFS,
PERIPH_ID_XUSB_SS,
PERIPH_ID_W_RESERVED29,
PERIPH_ID_W_RESERVED30,
PERIPH_ID_W_RESERVED31,
PERIPH_ID_X_FIRST,
/* X word: 31:0 */
PERIPH_ID_SPARE = PERIPH_ID_X_FIRST,
PERIPH_ID_X_RESERVED1,
PERIPH_ID_X_RESERVED2,
PERIPH_ID_X_RESERVED3,
PERIPH_ID_CAM_MCLK,
PERIPH_ID_CAM_MCLK2,
PERIPH_ID_I2C6,
PERIPH_ID_X_RESERVED7,
/* 168 */
PERIPH_ID_X_RESERVED8,
PERIPH_ID_X_RESERVED9,
PERIPH_ID_X_RESERVED10,
PERIPH_ID_VIM2_CLK,
PERIPH_ID_X_RESERVED12,
PERIPH_ID_X_RESERVED13,
PERIPH_ID_EMC_DLL,
PERIPH_ID_X_RESERVED15,
/* 176 */
PERIPH_ID_HDMI_AUDIO,
PERIPH_ID_CLK72MHZ,
PERIPH_ID_VIC,
PERIPH_ID_X_RESERVED19,
PERIPH_ID_X_RESERVED20,
PERIPH_ID_DPAUX,
PERIPH_ID_SOR0,
PERIPH_ID_X_RESERVED23,
/* 184 */
PERIPH_ID_GPU,
PERIPH_ID_X_RESERVED25,
PERIPH_ID_X_RESERVED26,
PERIPH_ID_X_RESERVED27,
PERIPH_ID_X_RESERVED28,
PERIPH_ID_X_RESERVED29,
PERIPH_ID_X_RESERVED30,
PERIPH_ID_X_RESERVED31,
PERIPH_ID_Y_FIRST,
/* Y word: 31:0 (192:223) */
PERIPH_ID_SPARE1 = PERIPH_ID_Y_FIRST,
PERIPH_ID_Y_RESERVED1,
PERIPH_ID_Y_RESERVED2,
PERIPH_ID_Y_RESERVED3,
PERIPH_ID_Y_RESERVED4,
PERIPH_ID_Y_RESERVED5,
PERIPH_ID_APE,
PERIPH_ID_Y_RESERVED7,
/* 200 */
PERIPH_ID_MC_CDPA,
PERIPH_ID_Y_RESERVED9,
PERIPH_ID_Y_RESERVED10,
PERIPH_ID_Y_RESERVED11,
PERIPH_ID_Y_RESERVED12,
PERIPH_ID_PEX_USB_UPHY,
PERIPH_ID_Y_RESERVED14,
PERIPH_ID_Y_RESERVED15,
/* 208 */
PERIPH_ID_VI_I2C,
PERIPH_ID_Y_RESERVED17,
PERIPH_ID_Y_RESERVED18,
PERIPH_ID_QSPI,
PERIPH_ID_Y_RESERVED20,
PERIPH_ID_Y_RESERVED21,
PERIPH_ID_Y_RESERVED22,
PERIPH_ID_Y_RESERVED23,
/* 216 */
PERIPH_ID_Y_RESERVED24,
PERIPH_ID_Y_RESERVED25,
PERIPH_ID_Y_RESERVED26,
PERIPH_ID_Y_RESERVED27,
PERIPH_ID_Y_RESERVED28,
PERIPH_ID_Y_RESERVED29,
PERIPH_ID_Y_RESERVED30,
PERIPH_ID_Y_RESERVED31,
PERIPH_ID_COUNT,
PERIPH_ID_NONE = -1,
};
enum pll_out_id {
PLL_OUT1,
PLL_OUT2,
PLL_OUT3,
PLL_OUT4
};
/*
* Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
* callers to use the PERIPH_ID for all access to peripheral clocks to avoid
* confusion bewteen PERIPH_ID_... and PERIPHC_...
*
* We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
* confusing.
*/
enum periphc_internal_id {
/* 0x00 */
PERIPHC_I2S2,
PERIPHC_I2S3,
PERIPHC_SPDIF_OUT,
PERIPHC_SPDIF_IN,
PERIPHC_PWM,
PERIPHC_05h,
PERIPHC_SBC2,
PERIPHC_SBC3,
/* 0x08 */
PERIPHC_08h,
PERIPHC_I2C1,
PERIPHC_I2C5,
PERIPHC_0bh,
PERIPHC_0ch,
PERIPHC_SBC1,
PERIPHC_DISP1,
PERIPHC_DISP2,
/* 0x10 */
PERIPHC_10h,
PERIPHC_11h,
PERIPHC_VI,
PERIPHC_13h,
PERIPHC_SDMMC1,
PERIPHC_SDMMC2,
PERIPHC_G3D,
PERIPHC_G2D,
/* 0x18 */
PERIPHC_18h,
PERIPHC_SDMMC4,
PERIPHC_VFIR,
PERIPHC_1Bh,
PERIPHC_1Ch,
PERIPHC_HSI,
PERIPHC_UART1,
PERIPHC_UART2,
/* 0x20 */
PERIPHC_HOST1X,
PERIPHC_21h,
PERIPHC_22h,
PERIPHC_HDMI,
PERIPHC_24h,
PERIPHC_25h,
PERIPHC_I2C2,
PERIPHC_EMC,
/* 0x28 */
PERIPHC_UART3,
PERIPHC_29h,
PERIPHC_VI_SENSOR,
PERIPHC_2bh,
PERIPHC_2ch,
PERIPHC_SBC4,
PERIPHC_I2C3,
PERIPHC_SDMMC3,
/* 0x30 */
PERIPHC_UART4,
PERIPHC_UART5,
PERIPHC_VDE,
PERIPHC_OWR,
PERIPHC_NOR,
PERIPHC_CSITE,
PERIPHC_I2S1,
PERIPHC_DTV,
/* 0x38 */
PERIPHC_38h,
PERIPHC_39h,
PERIPHC_3ah,
PERIPHC_3bh,
PERIPHC_MSENC,
PERIPHC_TSEC,
PERIPHC_3eh,
PERIPHC_OSC,
PERIPHC_VW_FIRST,
/* 0x40 */
PERIPHC_40h = PERIPHC_VW_FIRST,
PERIPHC_MSELECT,
PERIPHC_TSENSOR,
PERIPHC_I2S4,
PERIPHC_I2S5,
PERIPHC_I2C4,
PERIPHC_SBC5,
PERIPHC_SBC6,
/* 0x48 */
PERIPHC_AUDIO,
PERIPHC_49h,
PERIPHC_4ah,
PERIPHC_4bh,
PERIPHC_4ch,
PERIPHC_HDA2CODEC2X,
PERIPHC_ACTMON,
PERIPHC_EXTPERIPH1,
/* 0x50 */
PERIPHC_EXTPERIPH2,
PERIPHC_EXTPERIPH3,
PERIPHC_52h,
PERIPHC_I2CSLOW,
PERIPHC_SYS,
PERIPHC_55h,
PERIPHC_56h,
PERIPHC_57h,
/* 0x58 */
PERIPHC_58h,
PERIPHC_59h,
PERIPHC_5ah,
PERIPHC_5bh,
PERIPHC_SATAOOB,
PERIPHC_SATA,
PERIPHC_HDA, /* 0x428 */
PERIPHC_5fh,
PERIPHC_X_FIRST,
/* 0x60 */
PERIPHC_XUSB_CORE_HOST = PERIPHC_X_FIRST, /* 0x600 */
PERIPHC_XUSB_FALCON,
PERIPHC_XUSB_FS,
PERIPHC_XUSB_CORE_DEV,
PERIPHC_XUSB_SS,
PERIPHC_CILAB,
PERIPHC_CILCD,
PERIPHC_CILE,
/* 0x68 */
PERIPHC_DSIA_LP,
PERIPHC_DSIB_LP,
PERIPHC_ENTROPY,
PERIPHC_DVFS_REF,
PERIPHC_DVFS_SOC,
PERIPHC_TRACECLKIN,
PERIPHC_6Eh,
PERIPHC_6Fh,
/* 0x70 */
PERIPHC_EMC_LATENCY,
PERIPHC_SOC_THERM,
PERIPHC_72h,
PERIPHC_73h,
PERIPHC_74h,
PERIPHC_75h,
PERIPHC_VI_SENSOR2,
PERIPHC_I2C6,
/* 0x78 */
PERIPHC_78h,
PERIPHC_EMC_DLL,
PERIPHC_7ah,
PERIPHC_CLK72MHZ,
PERIPHC_7ch,
PERIPHC_7dh,
PERIPHC_VIC,
PERIPHC_7fh,
PERIPHC_Y_FIRST,
/* 0x80 */
PERIPHC_SDMMC_LEGACY_TM = PERIPHC_Y_FIRST, /* 0x694 */
PERIPHC_NVDEC, /* 0x698 */
PERIPHC_NVJPG, /* 0x69c */
PERIPHC_NVENC, /* 0x6a0 */
PERIPHC_84h,
PERIPHC_85h,
PERIPHC_86h,
PERIPHC_87h,
/* 0x88 */
PERIPHC_88h,
PERIPHC_89h,
PERIPHC_DMIC3, /* 0x6bc: */
PERIPHC_APE, /* 0x6c0: */
PERIPHC_QSPI, /* 0x6c4: */
PERIPHC_VI_I2C, /* 0x6c8: */
PERIPHC_USB2_HSIC_TRK, /* 0x6cc: */
PERIPHC_PEX_SATA_USB_RX_BYP, /* 0x6d0: */
/* 0x90 */
PERIPHC_MAUD, /* 0x6d4: */
PERIPHC_TSECB, /* 0x6d8: */
PERIPHC_COUNT,
PERIPHC_NONE = -1,
};
/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
#define PERIPH_REG(id) \
(id < PERIPH_ID_VW_FIRST) ? \
((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
/* Mask value for a clock (within PERIPH_REG(id)) */
#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
/* return 1 if a PLL ID is in range */
#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
/* return 1 if a peripheral ID is in range */
#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
(id) < PERIPH_ID_COUNT)
#endif /* _TEGRA210_CLOCK_TABLES_H_ */

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/*
* (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* Tegra210 clock control definitions */
#ifndef _TEGRA210_CLOCK_H_
#define _TEGRA210_CLOCK_H_
#include <asm/arch-tegra/clock.h>
/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
#define OSC_FREQ_SHIFT 28
#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT)
/* PLL bits that differ from generic clk_rst.h */
#define PLLC_RESET 30
#define PLLC_IDDQ 27
#define PLLD_ENABLE_CLK 21
#define PLLD_EN_LCKDET 28
int tegra_plle_enable(void);
#endif /* _TEGRA210_CLOCK_H_ */

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/*
* (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA210_FLOW_H_
#define _TEGRA210_FLOW_H_
struct flow_ctlr {
u32 halt_cpu_events; /* offset 0x00 */
u32 halt_cop_events; /* offset 0x04 */
u32 cpu_csr; /* offset 0x08 */
u32 cop_csr; /* offset 0x0c */
u32 xrq_events; /* offset 0x10 */
u32 halt_cpu1_events; /* offset 0x14 */
u32 cpu1_csr; /* offset 0x18 */
u32 halt_cpu2_events; /* offset 0x1c */
u32 cpu2_csr; /* offset 0x20 */
u32 halt_cpu3_events; /* offset 0x24 */
u32 cpu3_csr; /* offset 0x28 */
u32 cluster_control; /* offset 0x2c */
u32 halt_cop1_events; /* offset 0x30 */
u32 halt_cop1_csr; /* offset 0x34 */
u32 cpu_pwr_csr; /* offset 0x38 */
u32 mpid; /* offset 0x3c */
u32 ram_repair; /* offset 0x40 */
};
/* HALT_COP_EVENTS_0, 0x04 */
#define EVENT_MSEC (1 << 24)
#define EVENT_USEC (1 << 25)
#define EVENT_JTAG (1 << 28)
#define EVENT_MODE_STOP (2 << 29)
/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */
#define ACTIVE_LP (1 << 0)
/* CPUn_CSR_0 */
#define CSR_ENABLE (1 << 0)
#define CSR_IMMEDIATE_WAKE (1 << 3)
#define CSR_WAIT_WFI_SHIFT 8
#endif /* _TEGRA210_FLOW_H_ */

23
arch/arm/include/asm/arch-tegra210/funcmux.h Normal file
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@@ -0,0 +1,23 @@
/*
* (C) Copyright 2013-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* Tegra210 high-level function multiplexing */
#ifndef _TEGRA210_FUNCMUX_H_
#define _TEGRA210_FUNCMUX_H_
#include <asm/arch-tegra/funcmux.h>
/* Configs supported by the func mux */
enum {
FUNCMUX_DEFAULT = 0, /* default config */
/* UART configs */
FUNCMUX_UART1_UART1 = 0,
FUNCMUX_UART4_UART4 = 0,
};
#endif /* _TEGRA210_FUNCMUX_H_ */

74
arch/arm/include/asm/arch-tegra210/gp_padctrl.h Normal file
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/*
* (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA210_GP_PADCTRL_H_
#define _TEGRA210_GP_PADCTRL_H_
#include <asm/arch-tegra/gp_padctrl.h>
/* APB_MISC_GP and padctrl registers */
struct apb_misc_gp_ctlr {
u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
u32 reserved0[22]; /* 0x08 - 0x5C: */
u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
u32 reserved1; /* 0x8C: */
u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
u32 reserved2[3]; /* 0xA4 - 0xAC: */
u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
u32 reserved3[9]; /* 0xC8-0xE8: */
u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
u32 reserved4[3]; /* 0xF0-0xF8: */
u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */
u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */
u32 reserved5[3]; /* 0x104-0x10C: */
u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */
u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */
u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */
u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */
u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */
u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */
u32 reserved6; /* 0x128: */
u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */
u32 reserved7[2]; /* 0x130 - 0x134: */
u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */
u32 reserved8[22]; /* 0x13C - 0x190: */
u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */
u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */
u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */
u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */
u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */
u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */
u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */
};
/* SDMMC1/3 settings from section 27.5 of T114 TRM */
#define SDIOCFG_DRVUP_SLWF 0
#define SDIOCFG_DRVDN_SLWR 0
#define SDIOCFG_DRVUP 0x24
#define SDIOCFG_DRVDN 0x14
#endif /* _TEGRA210_GP_PADCTRL_H_ */

303
arch/arm/include/asm/arch-tegra210/gpio.h Normal file
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@@ -0,0 +1,303 @@
/*
* (C) Copyright 2013-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA210_GPIO_H_
#define _TEGRA210_GPIO_H_
/*
* The Tegra210 GPIO controller has 256 GPIOS in 8 banks of 4 ports,
* each with 8 GPIOs.
*/
#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */
#define TEGRA_GPIO_BANKS 8 /* number of banks */
#include <asm/arch-tegra/gpio.h>
/* GPIO Controller registers for a single bank */
struct gpio_ctlr_bank {
uint gpio_config[TEGRA_GPIO_PORTS];
uint gpio_dir_out[TEGRA_GPIO_PORTS];
uint gpio_out[TEGRA_GPIO_PORTS];
uint gpio_in[TEGRA_GPIO_PORTS];
uint gpio_int_status[TEGRA_GPIO_PORTS];
uint gpio_int_enable[TEGRA_GPIO_PORTS];
uint gpio_int_level[TEGRA_GPIO_PORTS];
uint gpio_int_clear[TEGRA_GPIO_PORTS];
uint gpio_masked_config[TEGRA_GPIO_PORTS];
uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];
uint gpio_masked_out[TEGRA_GPIO_PORTS];
uint gpio_masked_in[TEGRA_GPIO_PORTS];
uint gpio_masked_int_status[TEGRA_GPIO_PORTS];
uint gpio_masked_int_enable[TEGRA_GPIO_PORTS];
uint gpio_masked_int_level[TEGRA_GPIO_PORTS];
uint gpio_masked_int_clear[TEGRA_GPIO_PORTS];
};
struct gpio_ctlr {
struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
};
enum gpio_pin {
GPIO_PA0 = 0, /* pin 0 */
GPIO_PA1,
GPIO_PA2,
GPIO_PA3,
GPIO_PA4,
GPIO_PA5,
GPIO_PA6,
GPIO_PA7,
GPIO_PB0, /* pin 8 */
GPIO_PB1,
GPIO_PB2,
GPIO_PB3,
GPIO_PB4,
GPIO_PB5,
GPIO_PB6,
GPIO_PB7,
GPIO_PC0, /* pin 16 */
GPIO_PC1,
GPIO_PC2,
GPIO_PC3,
GPIO_PC4,
GPIO_PC5,
GPIO_PC6,
GPIO_PC7,
GPIO_PD0, /* pin 24 */
GPIO_PD1,
GPIO_PD2,
GPIO_PD3,
GPIO_PD4,
GPIO_PD5,
GPIO_PD6,
GPIO_PD7,
GPIO_PE0, /* pin 32 */
GPIO_PE1,
GPIO_PE2,
GPIO_PE3,
GPIO_PE4,
GPIO_PE5,
GPIO_PE6,
GPIO_PE7,
GPIO_PF0, /* pin 40 */
GPIO_PF1,
GPIO_PF2,
GPIO_PF3,
GPIO_PF4,
GPIO_PF5,
GPIO_PF6,
GPIO_PF7,
GPIO_PG0, /* pin 48 */
GPIO_PG1,
GPIO_PG2,
GPIO_PG3,
GPIO_PG4,
GPIO_PG5,
GPIO_PG6,
GPIO_PG7,
GPIO_PH0, /* pin 56 */
GPIO_PH1,
GPIO_PH2,
GPIO_PH3,
GPIO_PH4,
GPIO_PH5,
GPIO_PH6,
GPIO_PH7,
GPIO_PI0, /* pin 64 */
GPIO_PI1,
GPIO_PI2,
GPIO_PI3,
GPIO_PI4,
GPIO_PI5,
GPIO_PI6,
GPIO_PI7,
GPIO_PJ0, /* pin 72 */
GPIO_PJ1,
GPIO_PJ2,
GPIO_PJ3,
GPIO_PJ4,
GPIO_PJ5,
GPIO_PJ6,
GPIO_PJ7,
GPIO_PK0, /* pin 80 */
GPIO_PK1,
GPIO_PK2,
GPIO_PK3,
GPIO_PK4,
GPIO_PK5,
GPIO_PK6,
GPIO_PK7,
GPIO_PL0, /* pin 88 */
GPIO_PL1,
GPIO_PL2,
GPIO_PL3,
GPIO_PL4,
GPIO_PL5,
GPIO_PL6,
GPIO_PL7,
GPIO_PM0, /* pin 96 */
GPIO_PM1,
GPIO_PM2,
GPIO_PM3,
GPIO_PM4,
GPIO_PM5,
GPIO_PM6,
GPIO_PM7,
GPIO_PN0, /* pin 104 */
GPIO_PN1,
GPIO_PN2,
GPIO_PN3,
GPIO_PN4,
GPIO_PN5,
GPIO_PN6,
GPIO_PN7,
GPIO_PO0, /* pin 112 */
GPIO_PO1,
GPIO_PO2,
GPIO_PO3,
GPIO_PO4,
GPIO_PO5,
GPIO_PO6,
GPIO_PO7,
GPIO_PP0, /* pin 120 */
GPIO_PP1,
GPIO_PP2,
GPIO_PP3,
GPIO_PP4,
GPIO_PP5,
GPIO_PP6,
GPIO_PP7,
GPIO_PQ0, /* pin 128 */
GPIO_PQ1,
GPIO_PQ2,
GPIO_PQ3,
GPIO_PQ4,
GPIO_PQ5,
GPIO_PQ6,
GPIO_PQ7,
GPIO_PR0, /* pin 136 */
GPIO_PR1,
GPIO_PR2,
GPIO_PR3,
GPIO_PR4,
GPIO_PR5,
GPIO_PR6,
GPIO_PR7,
GPIO_PS0, /* pin 144 */
GPIO_PS1,
GPIO_PS2,
GPIO_PS3,
GPIO_PS4,
GPIO_PS5,
GPIO_PS6,
GPIO_PS7,
GPIO_PT0, /* pin 152 */
GPIO_PT1,
GPIO_PT2,
GPIO_PT3,
GPIO_PT4,
GPIO_PT5,
GPIO_PT6,
GPIO_PT7,
GPIO_PU0, /* pin 160 */
GPIO_PU1,
GPIO_PU2,
GPIO_PU3,
GPIO_PU4,
GPIO_PU5,
GPIO_PU6,
GPIO_PU7,
GPIO_PV0, /* pin 168 */
GPIO_PV1,
GPIO_PV2,
GPIO_PV3,
GPIO_PV4,
GPIO_PV5,
GPIO_PV6,
GPIO_PV7,
GPIO_PW0, /* pin 176 */
GPIO_PW1,
GPIO_PW2,
GPIO_PW3,
GPIO_PW4,
GPIO_PW5,
GPIO_PW6,
GPIO_PW7,
GPIO_PX0, /* pin 184 */
GPIO_PX1,
GPIO_PX2,
GPIO_PX3,
GPIO_PX4,
GPIO_PX5,
GPIO_PX6,
GPIO_PX7,
GPIO_PY0, /* pin 192 */
GPIO_PY1,
GPIO_PY2,
GPIO_PY3,
GPIO_PY4,
GPIO_PY5,
GPIO_PY6,
GPIO_PY7,
GPIO_PZ0, /* pin 200 */
GPIO_PZ1,
GPIO_PZ2,
GPIO_PZ3,
GPIO_PZ4,
GPIO_PZ5,
GPIO_PZ6,
GPIO_PZ7,
GPIO_PAA0, /* pin 208 */
GPIO_PAA1,
GPIO_PAA2,
GPIO_PAA3,
GPIO_PAA4,
GPIO_PAA5,
GPIO_PAA6,
GPIO_PAA7,
GPIO_PBB0, /* pin 216 */
GPIO_PBB1,
GPIO_PBB2,
GPIO_PBB3,
GPIO_PBB4,
GPIO_PBB5,
GPIO_PBB6,
GPIO_PBB7,
GPIO_PCC0, /* pin 224 */
GPIO_PCC1,
GPIO_PCC2,
GPIO_PCC3,
GPIO_PCC4,
GPIO_PCC5,
GPIO_PCC6,
GPIO_PCC7,
GPIO_PDD0, /* pin 232 */
GPIO_PDD1,
GPIO_PDD2,
GPIO_PDD3,
GPIO_PDD4,
GPIO_PDD5,
GPIO_PDD6,
GPIO_PDD7,
GPIO_PEE0, /* pin 240 */
GPIO_PEE1,
GPIO_PEE2,
GPIO_PEE3,
GPIO_PEE4,
GPIO_PEE5,
GPIO_PEE6,
GPIO_PEE7,
GPIO_PFF0, /* pin 248 */
GPIO_PFF1,
GPIO_PFF2,
GPIO_PFF3,
GPIO_PFF4,
GPIO_PFF5,
GPIO_PFF6,
GPIO_PFF7, /* pin 255 */
};
#endif /* _TEGRA210_GPIO_H_ */

72
arch/arm/include/asm/arch-tegra210/mc.h Normal file
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@@ -0,0 +1,72 @@
/*
* Copyright (c) 2014-2015 NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA210_MC_H_
#define _TEGRA210_MC_H_
/**
* Defines the memory controller registers we need/care about
*/
struct mc_ctlr {
u32 reserved0[4]; /* offset 0x00 - 0x0C */
u32 mc_smmu_config; /* offset 0x10 */
u32 mc_smmu_tlb_config; /* offset 0x14 */
u32 mc_smmu_ptc_config; /* offset 0x18 */
u32 mc_smmu_ptb_asid; /* offset 0x1C */
u32 mc_smmu_ptb_data; /* offset 0x20 */
u32 reserved1[3]; /* offset 0x24 - 0x2C */
u32 mc_smmu_tlb_flush; /* offset 0x30 */
u32 mc_smmu_ptc_flush; /* offset 0x34 */
u32 reserved2[6]; /* offset 0x38 - 0x4C */
u32 mc_emem_cfg; /* offset 0x50 */
u32 mc_emem_adr_cfg; /* offset 0x54 */
u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */
u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */
u32 reserved3[4]; /* offset 0x60 - 0x6C */
u32 mc_security_cfg0; /* offset 0x70 */
u32 mc_security_cfg1; /* offset 0x74 */
u32 reserved4[6]; /* offset 0x7C - 0x8C */
u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */
u32 reserved5[74]; /* offset 0x100 - 0x224 */
u32 mc_smmu_translation_enable_0; /* offset 0x228 */
u32 mc_smmu_translation_enable_1; /* offset 0x22C */
u32 mc_smmu_translation_enable_2; /* offset 0x230 */
u32 mc_smmu_translation_enable_3; /* offset 0x234 */
u32 mc_smmu_afi_asid; /* offset 0x238 */
u32 mc_smmu_avpc_asid; /* offset 0x23C */
u32 mc_smmu_dc_asid; /* offset 0x240 */
u32 mc_smmu_dcb_asid; /* offset 0x244 */
u32 reserved6[2]; /* offset 0x248 - 0x24C */
u32 mc_smmu_hc_asid; /* offset 0x250 */
u32 mc_smmu_hda_asid; /* offset 0x254 */
u32 mc_smmu_isp2_asid; /* offset 0x258 */
u32 reserved7[2]; /* offset 0x25C - 0x260 */
u32 mc_smmu_msenc_asid; /* offset 0x264 */
u32 mc_smmu_nv_asid; /* offset 0x268 */
u32 mc_smmu_nv2_asid; /* offset 0x26C */
u32 mc_smmu_ppcs_asid; /* offset 0x270 */
u32 mc_smmu_sata_asid; /* offset 0x274 */
u32 reserved8[1]; /* offset 0x278 */
u32 mc_smmu_vde_asid; /* offset 0x27C */
u32 mc_smmu_vi_asid; /* offset 0x280 */
u32 mc_smmu_vic_asid; /* offset 0x284 */
u32 mc_smmu_xusb_host_asid; /* offset 0x288 */
u32 mc_smmu_xusb_dev_asid; /* offset 0x28C */
u32 reserved9[1]; /* offset 0x290 */
u32 mc_smmu_tsec_asid; /* offset 0x294 */
u32 mc_smmu_ppcs1_asid; /* offset 0x298 */
u32 reserved10[235]; /* offset 0x29C - 0x644 */
u32 mc_video_protect_bom; /* offset 0x648 */
u32 mc_video_protect_size_mb; /* offset 0x64c */
u32 mc_video_protect_reg_ctrl; /* offset 0x650 */
};
#define TEGRA_MC_SMMU_CONFIG_ENABLE (1 << 0)
#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED (0 << 0)
#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 << 0)
#endif /* _TEGRA210_MC_H_ */

14
arch/arm/include/asm/arch-tegra210/pmu.h Normal file
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@@ -0,0 +1,14 @@
/*
* (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA210_PMU_H_
#define _TEGRA210_PMU_H_
/* Set core and CPU voltages to nominal levels */
int pmu_set_nominal(void);
#endif /* _TEGRA210_PMU_H_ */

12
arch/arm/include/asm/arch-tegra210/powergate.h Normal file
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@@ -0,0 +1,12 @@
/*
* Copyright (c) 2014-2015 NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA210_POWERGATE_H_
#define _TEGRA210_POWERGATE_H_
#include <asm/arch-tegra/powergate.h>
#endif /* _TEGRA210_POWERGATE_H_ */

26
arch/arm/include/asm/arch-tegra210/sysctr.h Normal file
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@@ -0,0 +1,26 @@
/*
* (C) Copyright 2013-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA210_SYSCTR_H_
#define _TEGRA210_SYSCTR_H_
struct sysctr_ctlr {
u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */
u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */
u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */
u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */
u32 reserved1[4]; /* 0x10 - 0x1C */
u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */
u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */
u32 reserved2[1002]; /* 0x28 - 0xFCC */
u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */
};
#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */
#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */
#endif /* _TEGRA210_SYSCTR_H_ */

32
arch/arm/include/asm/arch-tegra210/tegra.h Normal file
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@@ -0,0 +1,32 @@
/*
* (C) Copyright 2013-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA210_TEGRA_H_
#define _TEGRA210_TEGRA_H_
#define GICD_BASE 0x50041000 /* Generic Int Cntrlr Distrib */
#define GICC_BASE 0x50042000 /* Generic Int Cntrlr CPU I/F */
#define NV_PA_AHB_BASE 0x6000C000 /* System regs (AHB, etc.) */
#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */
#define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */
#define NV_PA_SDRAM_BASE 0x80000000
#include <asm/arch-tegra/tegra.h>
#define BCT_ODMDATA_OFFSET 1288 /* offset to ODMDATA word */
#undef NVBOOTINFOTABLE_BCTSIZE
#undef NVBOOTINFOTABLE_BCTPTR
#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */
#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */
#define MAX_NUM_CPU 4
#define MCB_EMEM_ARB_OVERRIDE (NV_PA_MC_BASE + 0xE8)
#define TEGRA_USB1_BASE 0x7D000000
#endif /* _TEGRA210_TEGRA_H_ */

3
arch/arm/lib/crt0_64.S
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@@ -74,7 +74,8 @@ zero_gd:
cmp x0, x18
b.gt zero_gd
#if defined(CONFIG_SYS_MALLOC_F_LEN)
sub x0, x18, #CONFIG_SYS_MALLOC_F_LEN
ldr x0, =CONFIG_SYS_MALLOC_F_LEN
sub x0, x18, x0
str x0, [x18, #GD_MALLOC_BASE]
#endif
bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */

30
arch/arm/mach-tegra/Kconfig
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@@ -1,20 +1,49 @@
if TEGRA
config TEGRA_ARMV7_COMMON
bool "Tegra 32-bit"
select SUPPORT_SPL
select SPL
select OF_CONTROL
select SPL_DISABLE_OF_CONTROL
select CPU_V7
select DM
select DM_SPI_FLASH
select DM_SERIAL
select DM_I2C
select DM_SPI
select DM_GPIO
choice
prompt "Tegra SoC select"
optional
config TEGRA20
bool "Tegra20 family"
select TEGRA_ARMV7_COMMON
config TEGRA30
bool "Tegra30 family"
select TEGRA_ARMV7_COMMON
config TEGRA114
bool "Tegra114 family"
select TEGRA_ARMV7_COMMON
config TEGRA124
bool "Tegra124 family"
select TEGRA_ARMV7_COMMON
config TEGRA210
bool "Tegra210 family"
select OF_CONTROL
select ARM64
select DM
select DM_SPI_FLASH
select DM_SERIAL
select DM_I2C
select DM_SPI
select DM_GPIO
endchoice
@@ -25,5 +54,6 @@ source "arch/arm/mach-tegra/tegra20/Kconfig"
source "arch/arm/mach-tegra/tegra30/Kconfig"
source "arch/arm/mach-tegra/tegra114/Kconfig"
source "arch/arm/mach-tegra/tegra124/Kconfig"
source "arch/arm/mach-tegra/tegra210/Kconfig"
endif

5
arch/arm/mach-tegra/Makefile
View File

@@ -1,5 +1,5 @@
#
# (C) Copyright 2010,2011 Nvidia Corporation.
# (C) Copyright 2010-2015 Nvidia Corporation.
#
# (C) Copyright 2000-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -24,7 +24,9 @@ obj-y += pinmux-common.o
obj-y += powergate.o
obj-y += xusb-padctl.o
obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
#TCW Fix this to use a common config switch (CONFIG_LOCK_VPR?)
obj-$(CONFIG_TEGRA124) += vpr.o
obj-$(CONFIG_TEGRA210) += vpr.o
obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
ifndef CONFIG_SPL_BUILD
@@ -35,3 +37,4 @@ obj-$(CONFIG_TEGRA20) += tegra20/
obj-$(CONFIG_TEGRA30) += tegra30/
obj-$(CONFIG_TEGRA114) += tegra114/
obj-$(CONFIG_TEGRA124) += tegra124/
obj-$(CONFIG_TEGRA210) += tegra210/

15
arch/arm/mach-tegra/ap.c
View File

@@ -1,5 +1,5 @@
/*
* (C) Copyright 2010-2014
* (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -92,6 +92,13 @@ int tegra_get_chip_sku(void)
return TEGRA_SOC_T124;
}
break;
case CHIPID_TEGRA210:
switch (sku_id) {
case SKU_ID_T210_ENG:
default:
return TEGRA_SOC_T210;
}
break;
}
/* unknown chip/sku id */
@@ -100,6 +107,7 @@ int tegra_get_chip_sku(void)
return TEGRA_SOC_UNKNOWN;
}
#ifndef CONFIG_ARM64
static void enable_scu(void)
{
struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
@@ -131,8 +139,8 @@ static u32 get_odmdata(void)
* on BCTs for currently supported SoCs, which are locked down.
* If this changes in new chips, we can revisit this algorithm.
*/
u32 bct_start, odmdata;
unsigned long bct_start;
u32 odmdata;
bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR);
odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
@@ -222,3 +230,4 @@ void s_init(void)
/* init vpr */
config_vpr();
}
#endif

30
arch/arm/mach-tegra/board.c
View File

@@ -1,11 +1,12 @@
/*
* (C) Copyright 2010-2014
* (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
@@ -17,6 +18,8 @@
#include <asm/arch-tegra/sys_proto.h>
#include <asm/arch-tegra/warmboot.h>
void save_boot_params_ret(void);
DECLARE_GLOBAL_DATA_PTR;
enum {
@@ -29,6 +32,21 @@ enum {
UART_COUNT = 5,
};
static bool from_spl __attribute__ ((section(".data")));
#ifndef CONFIG_SPL_BUILD
void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
{
from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL;
save_boot_params_ret();
}
#endif
bool spl_was_boot_source(void)
{
return from_spl;
}
#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
#if !defined(CONFIG_TEGRA124)
#error tegra_cpu_is_non_secure has only been validated on Tegra124
@@ -125,12 +143,18 @@ static int uart_configs[] = {
-1,
FUNCMUX_UART4_GMI, /* UARTD */
-1,
#else /* Tegra124 */
#elif defined(CONFIG_TEGRA124)
FUNCMUX_UART1_KBC, /* UARTA */
-1,
-1,
FUNCMUX_UART4_GPIO, /* UARTD */
-1,
#else /* Tegra210 */
FUNCMUX_UART1_UART1, /* UARTA */
-1,
-1,
FUNCMUX_UART4_UART4, /* UARTD */
-1,
#endif
};
@@ -182,7 +206,7 @@ void board_init_uart_f(void)
setup_uarts(uart_ids);
}
#ifndef CONFIG_SYS_DCACHE_OFF
#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */

22
arch/arm/mach-tegra/board2.c
View File

@@ -196,6 +196,12 @@ void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
int board_early_init_f(void)
{
/* Do any special system timer/TSC setup */
#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
if (!tegra_cpu_is_non_secure())
#endif
arch_timer_init();
pinmux_init();
board_init_uart_f();
@@ -274,3 +280,19 @@ void pad_init_mmc(struct mmc_host *host)
#endif /* T30 */
}
#endif /* MMC */
#ifdef CONFIG_ARM64
/*
* Most hardware on 64-bit Tegra is still restricted to DMA to the lower
* 32-bits of the physical address space. Cap the maximum usable RAM area
* at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit
* boundary that most devices can address.
*/
ulong board_get_usable_ram_top(ulong total_size)
{
if (gd->ram_top > 0x100000000)
return 0x100000000;
return gd->ram_top;
}
#endif

2
arch/arm/mach-tegra/cache.c
View File

@@ -21,6 +21,7 @@
#include <asm/arch-tegra/ap.h>
#include <asm/arch/gp_padctrl.h>
#ifndef CONFIG_ARM64
void config_cache(void)
{
u32 reg = 0;
@@ -44,3 +45,4 @@ void config_cache(void)
reg |= 2;
asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg));
}
#endif

36
arch/arm/mach-tegra/clock.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -113,7 +113,11 @@ int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
data = readl(&pll->pll_misc);
*cpcon = (data & PLL_CPCON_MASK) >> PLL_CPCON_SHIFT;
*lfcon = (data & PLL_LFCON_MASK) >> PLL_LFCON_SHIFT;
#if defined(CONFIG_TEGRA210)
/* T210 PLLU uses KCP/KVCO instead of CPCON/LFCON */
*cpcon = (data & PLLU_KCP_MASK) >> PLLU_KCP_SHIFT;
*lfcon = (data & PLLU_KVCO_MASK) >> PLLU_KVCO_SHIFT;
#endif
return 0;
}
@@ -132,14 +136,28 @@ unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
* - same fields are always mapped at same offsets, except DCCON
* - DCCON is always 0, doesn't conflict
* - M,N, P of PLLP values are ignored for PLLP
* NOTE: Above is no longer true with T210 - TBD: FIX THIS
*/
misc_data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT);
#if defined(CONFIG_TEGRA210)
/* T210 PLLU uses KCP/KVCO instead of cpcon/lfcon */
if (clkid == CLOCK_ID_USB) {
/* preserve EN_LOCKDET, set by default */
misc_data = readl(&pll->pll_misc);
misc_data |= (cpcon << PLLU_KCP_SHIFT) |
(lfcon << PLLU_KVCO_SHIFT);
}
#endif
data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) |
(0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT);
if (clkid == CLOCK_ID_USB)
#if defined(CONFIG_TEGRA210)
data |= divp << PLLU_DIVP_SHIFT;
#else
data |= divp << PLLU_VCO_FREQ_SHIFT;
#endif
else
data |= divp << PLL_DIVP_SHIFT;
if (pll) {
@@ -534,8 +552,15 @@ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
/* Set cpcon to PLL_MISC */
misc_reg = readl(&pll->pll_misc);
#if !defined(CONFIG_TEGRA210)
misc_reg &= ~PLL_CPCON_MASK;
misc_reg |= cpcon << PLL_CPCON_SHIFT;
#else
/* T210 uses KCP instead, use the most common bit shift (PLLA/U/D2) */
misc_reg &= ~PLLU_KCP_MASK;
misc_reg |= cpcon << PLLU_KCP_SHIFT;
#endif
writel(misc_reg, &pll->pll_misc);
/* Enable PLL */
@@ -608,12 +633,6 @@ void clock_init(void)
debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
debug("PLLD = %d\n", pll_rate[CLOCK_ID_DISPLAY]);
debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
/* Do any special system timer/TSC setup */
#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
if (!tegra_cpu_is_non_secure())
#endif
arch_timer_init();
}
static void set_avp_clock_source(u32 src)
@@ -634,6 +653,7 @@ static void set_avp_clock_source(u32 src)
/*
* This function is useful on Tegra30, and any later SoCs that have compatible
* PLLP configuration registers.
* NOTE: Not used on Tegra210 - see tegra210_setup_pllp in T210 clock.c
*/
void tegra30_set_up_pllp(void)
{

55
arch/arm/mach-tegra/cpu.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -29,6 +29,7 @@ int get_num_cpus(void)
{
struct apb_misc_gp_ctlr *gp;
uint rev;
debug("%s entry\n", __func__);
gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
@@ -39,6 +40,8 @@ int get_num_cpus(void)
break;
case CHIPID_TEGRA30:
case CHIPID_TEGRA114:
case CHIPID_TEGRA124:
case CHIPID_TEGRA210:
default:
return 4;
break;
@@ -128,13 +131,30 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
},
/*
* T210: 700 MHz
*
* Register Field Bits Width
* ------------------------------
* PLLX_BASE p 24:20 5
* PLLX_BASE n 15: 8 8
* PLLX_BASE m 7: 0 8
*/
{
{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz = 702 MHz*/
{ .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz*/
{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz*/
{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz*/
},
};
static inline void pllx_set_iddq(void)
{
#if defined(CONFIG_TEGRA124)
#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 reg;
debug("%s entry\n", __func__);
/* Disable IDDQ */
reg = readl(&clkrst->crc_pllx_misc3);
@@ -151,15 +171,14 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
{
int chip = tegra_get_chip();
u32 reg;
debug("%s entry\n", __func__);
/* If PLLX is already enabled, just return */
if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
debug("pllx_set_rate: PLLX already enabled, returning\n");
debug("%s: PLLX already enabled, returning\n", __func__);
return 0;
}
debug(" pllx_set_rate entry\n");
pllx_set_iddq();
/* Set BYPASS, m, n and p to PLLX_BASE */
@@ -182,19 +201,19 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
reg = readl(&pll->pll_base);
reg &= ~PLL_BYPASS_MASK;
writel(reg, &pll->pll_base);
debug("pllx_set_rate: base = 0x%08X\n", reg);
debug("%s: base = 0x%08X\n", __func__, reg);
/* Set lock_enable to PLLX_MISC */
reg = readl(&pll->pll_misc);
reg |= PLL_LOCK_ENABLE_MASK;
writel(reg, &pll->pll_misc);
debug("pllx_set_rate: misc = 0x%08X\n", reg);
debug("%s: misc = 0x%08X\n", __func__, reg);
/* Enable PLLX last, once it's all configured */
reg = readl(&pll->pll_base);
reg |= PLL_ENABLE_MASK;
writel(reg, &pll->pll_base);
debug("pllx_set_rate: base final = 0x%08X\n", reg);
debug("%s: base final = 0x%08X\n", __func__, reg);
return 0;
}
@@ -206,24 +225,23 @@ void init_pllx(void)
int soc_type, sku_info, chip_sku;
enum clock_osc_freq osc;
struct clk_pll_table *sel;
debug("init_pllx entry\n");
debug("%s entry\n", __func__);
/* get SOC (chip) type */
soc_type = tegra_get_chip();
debug(" init_pllx: SoC = 0x%02X\n", soc_type);
debug("%s: SoC = 0x%02X\n", __func__, soc_type);
/* get SKU info */
sku_info = tegra_get_sku_info();
debug(" init_pllx: SKU info byte = 0x%02X\n", sku_info);
debug("%s: SKU info byte = 0x%02X\n", __func__, sku_info);
/* get chip SKU, combo of the above info */
chip_sku = tegra_get_chip_sku();
debug(" init_pllx: Chip SKU = %d\n", chip_sku);
debug("%s: Chip SKU = %d\n", __func__, chip_sku);
/* get osc freq */
osc = clock_get_osc_freq();
debug(" init_pllx: osc = %d\n", osc);
debug("%s: osc = %d\n", __func__, osc);
/* set pllx */
sel = &tegra_pll_x_table[chip_sku][osc];
@@ -234,6 +252,7 @@ void enable_cpu_clock(int enable)
{
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 clk;
debug("%s entry\n", __func__);
/*
* NOTE:
@@ -282,6 +301,7 @@ static void remove_cpu_io_clamps(void)
{
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 reg;
debug("%s entry\n", __func__);
/* Remove the clamps on the CPU I/O signals */
reg = readl(&pmc->pmc_remove_clamping);
@@ -297,6 +317,7 @@ void powerup_cpu(void)
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 reg;
int timeout = IO_STABILIZATION_DELAY;
debug("%s entry\n", __func__);
if (!is_cpu_powered()) {
/* Toggle the CPU power state (OFF -> ON) */
@@ -336,7 +357,7 @@ void reset_A9_cpu(int reset)
int num_cpus = get_num_cpus();
int cpu;
debug("reset_a9_cpu entry\n");
debug("%s entry\n", __func__);
/* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
for (cpu = 1; cpu < num_cpus; cpu++)
reset_cmplx_set_enable(cpu, mask, 1);
@@ -350,7 +371,7 @@ void clock_enable_coresight(int enable)
{
u32 rst, src = 2;
debug("clock_enable_coresight entry\n");
debug("%s entry\n", __func__);
clock_set_enable(PERIPH_ID_CORESIGHT, enable);
reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
@@ -377,6 +398,8 @@ void clock_enable_coresight(int enable)
void halt_avp(void)
{
debug("%s entry\n", __func__);
for (;;) {
writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29),
FLOW_CTLR_HALT_COP_EVENTS);

10
arch/arm/mach-tegra/cpu.h
View File

@@ -1,5 +1,5 @@
/*
* (C) Copyright 2010-2014
* (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -14,7 +14,7 @@
#define NVBL_PLLP_KHZ 216000
#define CSITE_KHZ 144000
#elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) || \
defined(CONFIG_TEGRA124)
defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
#define NVBL_PLLP_KHZ 408000
#define CSITE_KHZ 204000
#else
@@ -35,7 +35,7 @@
#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
#define PG_UP_TAG_0 0x0
#define CORESIGHT_UNLOCK 0xC5ACCE55;
#define CORESIGHT_UNLOCK 0xC5ACCE55
#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
@@ -53,6 +53,10 @@
#define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
/* SB_AA64_RESET_LOW and _HIGH defines for CPU reset vector */
#define SB_AA64_RESET_LOW 0x6000C230
#define SB_AA64_RESET_HIGH 0x6000C234
struct clk_pll_table {
u16 n;
u16 m;

15
arch/arm/mach-tegra/lowlevel_init.S
View File

@@ -10,6 +10,20 @@
#include <config.h>
#include <linux/linkage.h>
#ifdef CONFIG_ARM64
.align 5
ENTRY(reset_cpu)
/* get address for global reset register */
ldr x1, =PRM_RSTCTRL
ldr w3, [x1]
/* force reset */
orr w3, w3, #0x10
str w3, [x1]
mov w0, w0
1:
b 1b
ENDPROC(reset_cpu)
#else
.align 5
ENTRY(reset_cpu)
ldr r1, rstctl @ get addr for global reset
@@ -23,3 +37,4 @@ _loop_forever:
rstctl:
.word PRM_RSTCTRL
ENDPROC(reset_cpu)
#endif

2
arch/arm/mach-tegra/pinmux-common.c
View File

@@ -78,7 +78,7 @@
(((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE))
#endif
#define _R(offset) (u32 *)(NV_PA_APB_MISC_BASE + (offset))
#define _R(offset) (u32 *)((unsigned long)NV_PA_APB_MISC_BASE + (offset))
#if defined(CONFIG_TEGRA20)

18
arch/arm/mach-tegra/tegra210/Kconfig Normal file
View File

@@ -0,0 +1,18 @@
if TEGRA210
choice
prompt "Tegra210 board select"
config TARGET_P2571
bool "NVIDIA Tegra210 P2571 base board"
help
P2571 is a P2530 married to a P1963 I/O board
endchoice
config SYS_SOC
default "tegra210"
source "board/nvidia/p2571/Kconfig"
endif

11
arch/arm/mach-tegra/tegra210/Makefile Normal file
View File

@@ -0,0 +1,11 @@
#
# (C) Copyright 2013-2015
# NVIDIA Corporation <www.nvidia.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += clock.o
obj-y += funcmux.o
obj-y += pinmux.o
obj-y += xusb-padctl.o

1091
arch/arm/mach-tegra/tegra210/clock.c Normal file
View File

File diff suppressed because it is too large Load Diff

40
arch/arm/mach-tegra/tegra210/funcmux.c Normal file
View File

@@ -0,0 +1,40 @@
/*
* (C) Copyright 2013-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* Tegra210 high-level function multiplexing */
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
int funcmux_select(enum periph_id id, int config)
{
int bad_config = config != FUNCMUX_DEFAULT;
switch (id) {
/*
* Add other periph IDs here as needed.
* Note that all pinmux/pads should have already
* been set up in the board pinmux table in
* pinmux-config-<board>.h for all periphs.
* Leave this in for the odd case where a mux
* needs to be changed on-the-fly.
*/
default:
debug("%s: invalid periph_id %d", __func__, id);
return -1;
}
if (bad_config) {
debug("%s: invalid config %d for periph_id %d", __func__,
config, id);
return -1;
}
return 0;
}

495
arch/arm/mach-tegra/tegra210/xusb-padctl.c Normal file
View File

@@ -0,0 +1,495 @@
/*
* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0
*/
#define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
#include <common.h>
#include <errno.h>
#include <fdtdec.h>
#include <malloc.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch-tegra/xusb-padctl.h>
#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
struct tegra_xusb_phy_ops {
int (*prepare)(struct tegra_xusb_phy *phy);
int (*enable)(struct tegra_xusb_phy *phy);
int (*disable)(struct tegra_xusb_phy *phy);
int (*unprepare)(struct tegra_xusb_phy *phy);
};
struct tegra_xusb_phy {
const struct tegra_xusb_phy_ops *ops;
struct tegra_xusb_padctl *padctl;
};
struct tegra_xusb_padctl {
struct fdt_resource regs;
unsigned int enable;
struct tegra_xusb_phy phys[2];
};
static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
unsigned long offset)
{
u32 value = readl(padctl->regs.start + offset);
debug("padctl: %08lx > %08x\n", offset, value);
return value;
}
static inline void padctl_writel(struct tegra_xusb_padctl *padctl,
u32 value, unsigned long offset)
{
debug("padctl: %08lx < %08x\n", offset, value);
writel(value, padctl->regs.start + offset);
}
#define XUSB_PADCTL_ELPG_PROGRAM 0x024
#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)
#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 29)
static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
{
u32 value;
if (padctl->enable++ > 0)
return 0;
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
udelay(100);
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
udelay(100);
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
return 0;
}
static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
{
u32 value;
if (padctl->enable == 0) {
error("unbalanced enable/disable");
return 0;
}
if (--padctl->enable > 0)
return 0;
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
udelay(100);
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
udelay(100);
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
return 0;
}
static int phy_prepare(struct tegra_xusb_phy *phy)
{
int err;
err = tegra_xusb_padctl_enable(phy->padctl);
if (err < 0)
return err;
reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 0);
return 0;
}
static int phy_unprepare(struct tegra_xusb_phy *phy)
{
reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 1);
return tegra_xusb_padctl_disable(phy->padctl);
}
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK (0xff << 20)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(x) (((x) & 0xff) << 20)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK (0x3 << 16)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS (1 << 15)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD (1 << 4)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE (1 << 3)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK (0x3 << 1)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP(x) (((x) & 0x3) << 1)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ (1 << 0)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364
#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK (0xffffff << 4)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(x) (((x) & 0xffffff) << 4)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD (1 << 2)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE (1 << 1)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN (1 << 0)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL4 0x36c
#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN (1 << 15)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK (0x3 << 12)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(x) (((x) & 0x3) << 12)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN (1 << 8)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK (0xf << 4)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370
#define XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK (0xff << 16)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(x) (((x) & 0xff) << 16)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL8 0x37c
#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE (1 << 31)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD (1 << 15)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN (1 << 13)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN (1 << 12)
#define CLK_RST_XUSBIO_PLL_CFG0 0x51c
#define CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE (1 << 24)
#define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ (1 << 13)
#define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1 << 6)
#define CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1 << 2)
#define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0)
static int pcie_phy_enable(struct tegra_xusb_phy *phy)
{
struct tegra_xusb_padctl *padctl = phy->padctl;
unsigned long start;
u32 value;
debug("> %s(phy=%p)\n", __func__, phy);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK;
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(0x136);
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK;
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(0x2a);
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK;
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK;
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(2);
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK;
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK;
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(25);
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
udelay(1);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
debug(" waiting for calibration\n");
start = get_timer(0);
while (get_timer(start) < 250) {
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)
break;
}
debug(" done\n");
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
debug(" waiting for calibration to stop\n");
start = get_timer(0);
while (get_timer(start) < 250) {
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) == 0)
break;
}
debug(" done\n");
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
debug(" waiting for PLL to lock...\n");
start = get_timer(0);
while (get_timer(start) < 250) {
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)
break;
}
debug(" done\n");
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
debug(" waiting for register calibration...\n");
start = get_timer(0);
while (get_timer(start) < 250) {
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)
break;
}
debug(" done\n");
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
debug(" waiting for register calibration to stop...\n");
start = get_timer(0);
while (get_timer(start) < 250) {
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) == 0)
break;
}
debug(" done\n");
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
value &= ~CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL;
value &= ~CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL;
value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET;
value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ;
writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
udelay(1);
value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
value |= CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE;
writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
debug("< %s()\n", __func__);
return 0;
}
static int pcie_phy_disable(struct tegra_xusb_phy *phy)
{
return 0;
}
static const struct tegra_xusb_phy_ops pcie_phy_ops = {
.prepare = phy_prepare,
.enable = pcie_phy_enable,
.disable = pcie_phy_disable,
.unprepare = phy_unprepare,
};
static struct tegra_xusb_padctl *padctl = &(struct tegra_xusb_padctl) {
.phys = {
[0] = {
.ops = &pcie_phy_ops,
},
},
};
static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl,
const void *fdt, int node)
{
int err;
err = fdt_get_resource(fdt, node, "reg", 0, &padctl->regs);
if (err < 0) {
error("registers not found");
return err;
}
debug("regs: %pa-%pa\n", &padctl->regs.start,
&padctl->regs.end);
return 0;
}
static int process_nodes(const void *fdt, int nodes[], unsigned int count)
{
unsigned int i;
int err;
debug("> %s(fdt=%p, nodes=%p, count=%u)\n", __func__, fdt, nodes,
count);
for (i = 0; i < count; i++) {
enum fdt_compat_id id;
if (!fdtdec_get_is_enabled(fdt, nodes[i]))
continue;
id = fdtdec_lookup(fdt, nodes[i]);
switch (id) {
case COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL:
case COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL:
break;
default:
error("unsupported compatible: %s",
fdtdec_get_compatible(id));
continue;
}
err = tegra_xusb_padctl_parse_dt(padctl, fdt, nodes[i]);
if (err < 0) {
error("failed to parse DT: %d",
err);
continue;
}
/* deassert XUSB padctl reset */
reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0);
/* only a single instance is supported */
break;
}
debug("< %s()\n", __func__);
return 0;
}
struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type)
{
struct tegra_xusb_phy *phy = NULL;
switch (type) {
case TEGRA_XUSB_PADCTL_PCIE:
phy = &padctl->phys[0];
phy->padctl = padctl;
break;
}
return phy;
}
int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy)
{
if (phy && phy->ops && phy->ops->prepare)
return phy->ops->prepare(phy);
return phy ? -ENOSYS : -EINVAL;
}
int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy)
{
if (phy && phy->ops && phy->ops->enable)
return phy->ops->enable(phy);
return phy ? -ENOSYS : -EINVAL;
}
int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy)
{
if (phy && phy->ops && phy->ops->disable)
return phy->ops->disable(phy);
return phy ? -ENOSYS : -EINVAL;
}
int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy)
{
if (phy && phy->ops && phy->ops->unprepare)
return phy->ops->unprepare(phy);
return phy ? -ENOSYS : -EINVAL;
}
void tegra_xusb_padctl_init(const void *fdt)
{
int count, nodes[1];
debug("> %s(fdt=%p)\n", __func__, fdt);
count = fdtdec_find_aliases_for_id(fdt, "padctl",
COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,
nodes, ARRAY_SIZE(nodes));
if (process_nodes(fdt, nodes, count))
return;
count = fdtdec_find_aliases_for_id(fdt, "padctl",
COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
nodes, ARRAY_SIZE(nodes));
if (process_nodes(fdt, nodes, count))
return;
debug("< %s()\n", __func__);
}