ARC: [plat-axs10x]: migrate to DM_MMC

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

arch/arc/dts/axs10x_mb.dtsi

@@ -31,6 +31,25 @@
 				#clock-cells = <0>;
 				u-boot,dm-pre-reloc;
 			};
+
+			mmcclk_ciu: mmcclk-ciu {
+				compatible = "fixed-clock";
+				/*
+				 * DW sdio controller has external ciu clock divider
+				 * controlled via register in SDIO IP. It divides
+				 * sdio_ref_clk (which comes from CGU) by 16 for
+				 * default. So default mmcclk clock (which comes
+				 * to sdk_in) is 25000000 Hz.
+				 */
+				clock-frequency = <25000000>;
+				#clock-cells = <0>;
+			};
+
+			mmcclk_biu: mmcclk-biu {
+				compatible = "fixed-clock";
+				clock-frequency = <50000000>;
+				#clock-cells = <0>;
+			};
 		};
 
 		ethernet@18000 {
@@ -53,6 +72,15 @@
 			reg = < 0x60000 0x100 >;
 		};
 
+		mmc: mmc@15000 {
+			compatible = "snps,dw-mshc";
+			reg = <0x15000 0x400>;
+			bus-width = <4>;
+			clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
+			clock-names = "biu", "ciu";
+			max-frequency = <25000000>;
+		};
+
 		uart0: serial0@22000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x22000 0x100>;