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Merge tag 'xilinx-for-v2021.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

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Xilinx changes for v2021.04-rc3

qspi:
- Support for dual/quad mode
- Fix speed handling

clk:
- Add clock enable function for zynq/zynqmp/versal

gem:
- Enable clock for Versal
- Fix error path
- Fix mdio deregistration path

fpga:
- Fix buffer alignment for ZynqMP

xilinx:
- Fix reset reason clearing in ZynqMP
- Show silicon version in SPL for Zynq/ZynqMP
- Fix DTB selection for ZynqMP
- Rename zc1275 to zcu1275 to match DT name
This commit is contained in:
Tom Rini
2021-02-23 10:45:55 -05:00
parent 8f7a16aac3 d9aa19efa8
commit cbe607b920
18 changed files with 208 additions and 134 deletions
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4
arch/arm/mach-zynqmp/include/mach/hardware.h
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@@ -128,8 +128,8 @@ struct apu_regs {
#define ZYNQMP_CSU_VERSION_EMPTY_SHIFT 20
#define ZYNQMP_SILICON_VER_MASK 0xF000
#define ZYNQMP_SILICON_VER_SHIFT 12
#define ZYNQMP_SILICON_VER_MASK 0xF
#define ZYNQMP_SILICON_VER_SHIFT 0
struct csu_regs {
u32 reserved0[4];