spi: Zap armada100_spi.c and env
armada100_spi.c and related env is zapping becuase of "no DM conversion". Cc: Ajay Bhargav <ajay.bhargav@einfochips.com> Signed-off-by: Jagan Teki <jagan@openedev.com>
This commit is contained in:
Jagan Teki
Jagan Teki
parent
353f6a770f
commit
cb71c6d854
@ -4,9 +4,7 @@ CONFIG_IDENT_STRING="\nMarvell-gplugD"
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CONFIG_BOOTDELAY=3
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# CONFIG_DISPLAY_BOARDINFO is not set
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# CONFIG_CMD_IMLS is not set
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CONFIG_CMD_ASKENV=y
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_SF=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_USB=y
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# CONFIG_CMD_FPGA is not set
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@ -16,9 +14,6 @@ CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_FAT=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_ATMEL=y
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SYS_NS16550=y
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CONFIG_USB=y
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CONFIG_USB_STORAGE=y
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@ -16,7 +16,6 @@ obj-$(CONFIG_SOFT_SPI) += soft_spi_legacy.o
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endif
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obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
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obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o
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obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
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obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
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obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
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@ -1,203 +0,0 @@
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/*
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* (C) Copyright 2011
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* eInfochips Ltd. <www.einfochips.com>
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* Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
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*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Based on SSP driver
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* Written-by: Lei Wen <leiwen@marvell.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <spi.h>
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#include <asm/io.h>
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#include <asm/arch/spi.h>
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#include <asm/gpio.h>
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#define to_armd_spi_slave(s) container_of(s, struct armd_spi_slave, slave)
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struct armd_spi_slave {
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struct spi_slave slave;
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struct ssp_reg *spi_reg;
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u32 cr0, cr1;
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u32 int_cr1;
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u32 clear_sr;
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const void *tx;
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void *rx;
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int gpio_cs_inverted;
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};
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static int spi_armd_write(struct armd_spi_slave *pss)
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{
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int wait_timeout = SSP_FLUSH_NUM;
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while (--wait_timeout && !(readl(&pss->spi_reg->sssr) & SSSR_TNF))
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;
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if (!wait_timeout) {
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debug("%s: timeout error\n", __func__);
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return -1;
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}
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if (pss->tx != NULL) {
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writel(*(u8 *)pss->tx, &pss->spi_reg->ssdr);
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++pss->tx;
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} else {
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writel(0, &pss->spi_reg->ssdr);
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}
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return 0;
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}
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static int spi_armd_read(struct armd_spi_slave *pss)
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{
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int wait_timeout = SSP_FLUSH_NUM;
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while (--wait_timeout && !(readl(&pss->spi_reg->sssr) & SSSR_RNE))
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;
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if (!wait_timeout) {
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debug("%s: timeout error\n", __func__);
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return -1;
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}
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if (pss->rx != NULL) {
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*(u8 *)pss->rx = readl(&pss->spi_reg->ssdr);
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++pss->rx;
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} else {
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readl(&pss->spi_reg->ssdr);
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}
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return 0;
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}
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static int spi_armd_flush(struct armd_spi_slave *pss)
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{
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unsigned long limit = SSP_FLUSH_NUM;
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do {
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while (readl(&pss->spi_reg->sssr) & SSSR_RNE)
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readl(&pss->spi_reg->ssdr);
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} while ((readl(&pss->spi_reg->sssr) & SSSR_BSY) && limit--);
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writel(SSSR_ROR, &pss->spi_reg->sssr);
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return limit;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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struct armd_spi_slave *pss = to_armd_spi_slave(slave);
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gpio_set_value(slave->cs, pss->gpio_cs_inverted);
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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struct armd_spi_slave *pss = to_armd_spi_slave(slave);
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gpio_set_value(slave->cs, !pss->gpio_cs_inverted);
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct armd_spi_slave *pss;
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pss = spi_alloc_slave(struct armd_spi_slave, bus, cs);
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if (!pss)
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return NULL;
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pss->spi_reg = (struct ssp_reg *)SSP_REG_BASE(CONFIG_SYS_SSP_PORT);
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pss->cr0 = SSCR0_MOTO | SSCR0_DATASIZE(DEFAULT_WORD_LEN) | SSCR0_SSE;
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pss->cr1 = (SSCR1_RXTRESH(RX_THRESH_DEF) & SSCR1_RFT) |
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(SSCR1_TXTRESH(TX_THRESH_DEF) & SSCR1_TFT);
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pss->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
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pss->cr1 |= (((mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
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| (((mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
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pss->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
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pss->clear_sr = SSSR_ROR | SSSR_TINT;
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pss->gpio_cs_inverted = mode & SPI_CS_HIGH;
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gpio_set_value(cs, !pss->gpio_cs_inverted);
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return &pss->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct armd_spi_slave *pss = to_armd_spi_slave(slave);
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free(pss);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct armd_spi_slave *pss = to_armd_spi_slave(slave);
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debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
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if (spi_armd_flush(pss) == 0)
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return -1;
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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void *din, unsigned long flags)
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{
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struct armd_spi_slave *pss = to_armd_spi_slave(slave);
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uint bytes = bitlen / 8;
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unsigned long limit;
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int ret = 0;
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if (bitlen == 0)
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goto done;
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/* we can only do 8 bit transfers */
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if (bitlen % 8) {
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flags |= SPI_XFER_END;
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goto done;
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}
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pss->tx = dout;
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pss->rx = din;
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if (flags & SPI_XFER_BEGIN) {
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spi_cs_activate(slave);
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writel(pss->cr1 | pss->int_cr1, &pss->spi_reg->sscr1);
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writel(TIMEOUT_DEF, &pss->spi_reg->ssto);
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writel(pss->cr0, &pss->spi_reg->sscr0);
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}
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while (bytes--) {
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limit = SSP_FLUSH_NUM;
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ret = spi_armd_write(pss);
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if (ret)
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break;
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while ((readl(&pss->spi_reg->sssr) & SSSR_BSY) && limit--)
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udelay(1);
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ret = spi_armd_read(pss);
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if (ret)
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break;
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}
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done:
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if (flags & SPI_XFER_END) {
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/* Stop SSP */
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writel(pss->clear_sr, &pss->spi_reg->sssr);
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clrbits_le32(&pss->spi_reg->sscr1, pss->int_cr1);
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writel(0, &pss->spi_reg->ssto);
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spi_cs_deactivate(slave);
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}
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return ret;
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}
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@ -72,11 +72,6 @@
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/* GPIO Configuration for PHY */
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#define CONFIG_SYS_GPIO_PHY_RST 104 /* GPIO104 */
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/* SPI Support */
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#define CONFIG_ARMADA100_SPI
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#define CONFIG_ENV_SPI_CS 110
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#define CONFIG_SYS_SSP_PORT 2
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/* Flash Support */
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/*
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@ -95,10 +90,8 @@
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/*
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* Environment variables configurations
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*/
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_SECT_SIZE 0x4000
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#define CONFIG_ENV_IS_NOWHERE
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#define CONFIG_ENV_SIZE 0x4000
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#define CONFIG_ENV_OFFSET 0x07C000
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#ifdef CONFIG_CMD_USB
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#define CONFIG_USB_EHCI
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@ -176,7 +176,6 @@ CONFIG_ARIA_FPGA
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CONFIG_ARM926EJS
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CONFIG_ARMADA100
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CONFIG_ARMADA100_FEC
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CONFIG_ARMADA100_SPI
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CONFIG_ARMADA168
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CONFIG_ARMADA_39X
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CONFIG_ARMCORTEXA9
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