Merge tag 'u-boot-rockchip-20190729' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Clean up and migrate to use common rockchip spl board file - Clean up and migrate to use common rockchip board file - Increase rk3288 CONFIG_SYS_BOOTM_LEN to 16MB
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@@ -19,6 +19,8 @@
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#define CONFIG_SYS_ARCH_TIMER
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#define CONFIG_SYS_HZ_CLOCK 24000000
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#define CONFIG_IRAM_BASE 0x10080000
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#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
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#define CONFIG_SYS_LOAD_ADDR 0x60800800
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@@ -15,8 +15,6 @@
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#define CONFIG_SYS_MALLOC_LEN (32 << 20)
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#define CONFIG_SYS_CBSIZE 1024
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#define CONFIG_SYS_NS16550_MEM32
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#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
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/* Bootrom will load u-boot binary to 0x60000000 once return from SPL */
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#endif
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@@ -25,6 +23,7 @@
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#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x8000 - 0x800)
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#define CONFIG_ROCKCHIP_CHIP_TAG "RK31"
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#define CONFIG_IRAM_BASE 0x10080000
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/* spl size 32kb sram - 2kb bootrom */
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#define CONFIG_SPL_MAX_SIZE (0x8000 - 0x800)
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@@ -24,6 +24,7 @@
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#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (28 << 10)
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#define CONFIG_ROCKCHIP_CHIP_TAG "RK32"
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#define CONFIG_IRAM_BASE 0x10080000
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#define CONFIG_SYS_SDRAM_BASE 0x60000000
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#define SDRAM_BANK_SIZE (512UL << 20UL)
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@@ -9,6 +9,8 @@
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#include <asm/arch-rockchip/hardware.h>
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#include "rockchip-common.h"
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#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* 16MB */
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#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
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#define CONFIG_SYS_MALLOC_LEN (32 << 20)
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#define CONFIG_SYS_CBSIZE 1024
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@@ -25,6 +27,8 @@
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#define CONFIG_SYS_LOAD_ADDR 0x00800800
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#define CONFIG_SPL_STACK 0xff718000
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#define CONFIG_IRAM_BASE 0xff700000
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/* RAW SD card / eMMC locations. */
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#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
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@@ -8,12 +8,14 @@
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#include "rockchip-common.h"
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#define CONFIG_IRAM_BASE 0xff090000
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#define CONFIG_ROCKCHIP_STIMER_BASE 0xff1d0020
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#define CONFIG_SYS_MALLOC_LEN (32 << 20)
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#define CONFIG_SYS_CBSIZE 1024
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_SYS_NS16550_MEM32
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#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
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#define CONFIG_SYS_LOAD_ADDR 0x00800800
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#define CONFIG_SPL_STACK 0x00400000
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@@ -23,7 +23,7 @@
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#define CONFIG_ROCKCHIP_STIMER_BASE 0xff830020
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#define COUNTER_FREQUENCY 24000000
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#define CONFIG_SYS_NS16550_MEM32
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#define CONFIG_IRAM_BASE 0xff8c0000
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#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
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#define CONFIG_SYS_LOAD_ADDR 0x00280000
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@@ -15,7 +15,7 @@
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#define COUNTER_FREQUENCY 24000000
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#define CONFIG_ROCKCHIP_STIMER_BASE 0xff8680a0
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#define CONFIG_SYS_NS16550_MEM32
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#define CONFIG_IRAM_BASE 0xff8c0000
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#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
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#define CONFIG_SYS_LOAD_ADDR 0x00800800
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@@ -8,6 +8,8 @@
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#include <asm/arch-rockchip/hardware.h>
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#include "rockchip-common.h"
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#define CONFIG_IRAM_BASE 0x10080000
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#define CONFIG_SYS_MALLOC_LEN (32 << 20)
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#define CONFIG_SYS_CBSIZE 1024
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#define CONFIG_SKIP_LOWLEVEL_INIT
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