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x86: dts: Define a default TSC timer frequency

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If for some reason, TSC timer frequency cannot be determined from
hardware, nor is it specified in the device tree, U-Boot will panic
resulting in endless reset during boot.

Let's define a default TSC timer frequency using the Kconfig value
CONFIG_X86_TSC_TIMER_FREQ (note: #include must be used instead of
/include/ otherwise the macro is not pre-processed).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Bin Meng 2021-07-28 12:00:23 +08:00
parent 5824bc6d6f
commit c79cbb5952
20 changed files with 25 additions and 43 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/x86/dts/bayleybay.dts
View File

@ -14,8 +14,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {

2
arch/x86/dts/baytrail_som-db5800-som-6867.dts
View File

@ -14,8 +14,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {

2
arch/x86/dts/cherryhill.dts
View File

@ -12,8 +12,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {

3
arch/x86/dts/chromebook_coral.dts
View File

@ -8,7 +8,8 @@
/include/ "keyboard.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
#if defined(CONFIG_CHROMEOS_VBOOT) && defined(CONFIG_ROM_SIZE)
#include "chromeos-x86.dtsi"

2
arch/x86/dts/chromebook_link.dts
View File

@ -9,8 +9,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {

2
arch/x86/dts/chromebook_samus.dts
View File

@ -7,8 +7,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
#include "smbios.dtsi"
#if defined(CONFIG_CHROMEOS_VBOOT) && defined(CONFIG_ROM_SIZE)

2
arch/x86/dts/chromebox_panther.dts
View File

@ -4,8 +4,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {

2
arch/x86/dts/conga-qeval20-qa3-e3845.dts
View File

@ -14,8 +14,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {

7
arch/x86/dts/coreboot.dts
View File

@ -12,7 +12,8 @@
/include/ "pcspkr.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
/ {
model = "coreboot x86 payload";
@ -30,10 +31,6 @@
stdout-path = "/serial";
};
tsc-timer {
clock-frequency = <1000000000>;
};
pci {
compatible = "pci-x86";
u-boot,dm-pre-reloc;

2
arch/x86/dts/cougarcanyon2.dts
View File

@ -12,8 +12,8 @@
/include/ "keyboard.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {

2
arch/x86/dts/crownbay.dts
View File

@ -13,8 +13,8 @@
/include/ "pcspkr.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {

2
arch/x86/dts/edison.dts
View File

@ -10,8 +10,8 @@
/include/ "skeleton.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {

7
arch/x86/dts/efi-x86_app.dts
View File

@ -6,7 +6,8 @@
/dts-v1/;
/include/ "skeleton.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
/ {
model = "EFI x86 Application";
@ -16,10 +17,6 @@
stdout-path = &serial;
};
tsc-timer {
clock-frequency = <1000000000>;
};
serial: serial {
compatible = "efi,uart";
};

7
arch/x86/dts/efi-x86_payload.dts
View File

@ -12,7 +12,8 @@
/include/ "keyboard.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
/ {
model = "EFI x86 Payload";
@ -30,10 +31,6 @@
stdout-path = "/serial";
};
tsc-timer {
clock-frequency = <1000000000>;
};
pci {
compatible = "pci-x86";
u-boot,dm-pre-reloc;

7
arch/x86/dts/galileo.dts
View File

@ -11,7 +11,8 @@
/include/ "skeleton.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
/ {
model = "Intel Galileo";
@ -41,10 +42,6 @@
};
};
tsc-timer {
clock-frequency = <CONFIG_X86_TSC_TIMER_FREQ>;
};
mrc {
compatible = "intel,quark-mrc";
flags = <MRC_FLAG_SCRAMBLE_EN>;

2
arch/x86/dts/minnowmax.dts
View File

@ -13,8 +13,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {

6
arch/x86/dts/qemu-x86_i440fx.dts
View File

@ -12,8 +12,8 @@
/include/ "keyboard.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
@ -42,10 +42,6 @@
};
};
tsc-timer {
clock-frequency = <1000000000>;
};
pci {
compatible = "pci-x86";
#address-cells = <3>;

6
arch/x86/dts/qemu-x86_q35.dts
View File

@ -22,8 +22,8 @@
/include/ "keyboard.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
@ -53,10 +53,6 @@
};
};
tsc-timer {
clock-frequency = <1000000000>;
};
pci {
compatible = "pci-x86";
#address-cells = <3>;

2
arch/x86/dts/slimbootloader.dts
View File

@ -7,7 +7,7 @@
/include/ "skeleton.dtsi"
/include/ "reset.dtsi"
/include/ "tsc_timer.dtsi"
#include "tsc_timer.dtsi"
/ {
model = "slimbootloader x86 payload";

1
arch/x86/dts/tsc_timer.dtsi
View File

@ -1,6 +1,7 @@
/ {
tsc-timer {
compatible = "x86,tsc-timer";
clock-frequency = <CONFIG_X86_TSC_TIMER_FREQ>;
u-boot,dm-pre-reloc;
};
};