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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

Browse Source 
* 'master' of git://git.denx.de/u-boot-mpc85xx:
  powerpc/85xx: Fix builds of P1020/P2020RDB-PC_36BIT_NAND
  arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c: Fix GCC 4.6 build warning
  arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c: Fix GCC 4.6 build warning
  arch/powerpc/cpu/mpc8xxx/ddr/options.c: Fix GCC 4.6 build warning
  drivers/qe/uec.c: Fix GCC 4.6 build warning
  drivers/usb/host/ehci-fsl.c: Fix GCC 4.6 build warning
  drivers/net/fm/fm.c: Fix GCC 4.6 build warning
  board/sbc8560/sbc8560.c: Fix GCC 4.6 build warning
  board/sbc8548/sbc8548.c: Fix GCC 4.6 build warning
  board/freescale/mpc8569mds/mpc8569mds.c: Fix GCC 4.6 build warning
  board/freescale/mpc8568mds/mpc8568mds.c: Fix GCC 4.6 build warning
  board/freescale/mpc8548cds/mpc8548cds.c: Fix GCC 4.6 build warning
  board/freescale/common/pixis.c: Fix GCC 4.6 build warning
  board/freescale/common/cds_pci_ft.c: Fix GCC 4.6 build warning
  arch/powerpc/cpu/mpc8xxx/fsl_lbc.c: Fix GCC 4.6 build warning
  arch/powerpc/cpu/mpc85xx/tlb.c: Fix GCC 4.6 build warning
  arch/powerpc/cpu/mpc85xx/cpu_init.c: Fix GCC 4.6 build warning
  phylib: Enable AR8021 phy support
  powerpc/85xx: Set max alloc length to 10MB on P1022DS
  powerpc/mpc85xx: Set SYSCLK to the required frequency
  powerpc/85xx: Fix NAND SPL support
  powerpc/85xx: Fix MPC8572DS NAND build
  fsl_ifc: Fixed a bug in the erratum handling code for IFC_A003399
  powerpc/85xx: Add support for Book-E MMU Arch v2.0
  powerpc/85xx: Make inclusion of USB device fixup conditional
  powerpc/85xx: Fix warning for USB device-fixup
  powerpc/85xx: resize the boot page TLB before relocating CCSR
  powerpc/85xx: verify the current address of CCSR before relocating it
  powerpc/85xx: add some missing sync instructions in the CCSR relocation code
  powerpc/85xx: fix some comments in the CCSR relocation code
  powerpc/85xx: fix definition of MAS register macros
  powerpc/mpc8548cds: Fix network initialization
  powerpc/mpc8548: Add workaround for erratum NMG_eTSEC129
  powerpc/QorIQ: fix network frame manager TBI PHY address settings
This commit is contained in:
Wolfgang Denk
2011-11-16 20:06:21 +01:00
parent 4055a66847 4589728e21
commit c7801ee43b
43 changed files with 420 additions and 106 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
board/freescale/common/cds_pci_ft.c
View File

@@ -28,13 +28,12 @@
#if defined(CONFIG_OF_BOARD_SETUP)
static void cds_pci_fixup(void *blob)
{
int node, tmp[2];
int node;
const char *path;
int len, slot, i;
u32 *map = NULL;
node = fdt_path_offset(blob, "/aliases");
tmp[0] = 0;
if (node >= 0) {
path = fdt_getprop(blob, node, "pci0", NULL);
if (path) {

69
board/freescale/common/ics307_clk.c
View File

@@ -31,11 +31,80 @@
#include "pixis.h"
#endif
/* define for SYS CLK or CLK1Frequency */
#define TTL 1
#define CLK2 0
#define CRYSTAL 0
#define MAX_VDW (511 + 8)
#define MAX_RDW (127 + 2)
#define MIN_VDW (4 + 8)
#define MIN_RDW (1 + 2)
#define NUM_OD_SETTING 8
/*
* These defines cover the industrial temperature range part,
* for commercial, change below to 400000 and 55000, respectively
*/
#define MAX_VCO 360000
#define MIN_VCO 60000
/* decode S[0-2] to Output Divider (OD) */
static u8 ics307_s_to_od[] = {
10, 2, 8, 4, 5, 7, 3, 6
};
/*
* Find one solution to generate required frequency for SYSCLK
* out_freq: KHz, required frequency to the SYSCLK
* the result will be retuned with component RDW, VDW, OD, TTL,
* CLK2 and crystal
*/
unsigned long ics307_sysclk_calculator(unsigned long out_freq)
{
const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ;
unsigned long vdw, rdw, odp, s_vdw = 0, s_rdw = 0, s_odp = 0, od;
unsigned long tmp_out, diff, result = 0;
int found = 0;
for (odp = 0; odp < NUM_OD_SETTING; odp++) {
od = ics307_s_to_od[odp];
if (od * out_freq < MIN_VCO || od * out_freq > MAX_VCO)
continue;
for (rdw = MIN_RDW; rdw <= MAX_RDW; rdw++) {
/* Calculate the VDW */
vdw = out_freq * 1000 * od * rdw / (input_freq * 2);
if (vdw > MAX_VDW)
vdw = MAX_VDW;
if (vdw < MIN_VDW)
continue;
/* Calculate the temp out frequency */
tmp_out = input_freq * 2 * vdw / (rdw * od * 1000);
diff = MAX(out_freq, tmp_out) - MIN(out_freq, tmp_out);
/*
* calculate the percent, the precision is 1/1000
* If greater than 1/1000, continue
* otherwise, we think the solution is we required
*/
if (diff * 1000 / out_freq > 1)
continue;
else {
s_vdw = vdw;
s_rdw = rdw;
s_odp = odp;
found = 1;
break;
}
}
}
if (found)
result = (s_rdw - 2) | (s_vdw - 8) << 7 | s_odp << 16 |
CLK2 << 19 | TTL << 21 | CRYSTAL << 22;
debug("ICS307-02: RDW: %ld, VDW: %ld, OD: %d\n", s_rdw - 2, s_vdw - 8,
ics307_s_to_od[s_odp]);
return result;
}
/*
* Calculate frequency being generated by ICS307-02 clock chip based upon
* the control bytes being programmed into it.

4
board/freescale/common/ics307_clk.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright 2010 Freescale Semiconductor, Inc.
* Copyright 2010-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -23,8 +23,10 @@
#define __ICS_CLK_H_ 1
#ifndef __ASSEMBLY__
extern unsigned long get_board_sys_clk(void);
extern unsigned long get_board_ddr_clk(void);
extern unsigned long ics307_sysclk_calculator(unsigned long out_freq);
#endif
#endif /* __ICS_CLK_H_ */

27
board/freescale/common/ngpixis.c
View File

@@ -156,9 +156,29 @@ static void pixis_dump_regs(void)
}
#endif
void pixis_sysclk_set(unsigned long sysclk)
{
unsigned long freq_word;
u8 sclk0, sclk1, sclk2;
freq_word = ics307_sysclk_calculator(sysclk);
sclk2 = freq_word & 0xff;
sclk1 = (freq_word >> 8) & 0xff;
sclk0 = (freq_word >> 16) & 0xff;
/* set SYSCLK enable bit */
PIXIS_WRITE(vcfgen0, 0x01);
/* SYSCLK to required frequency */
PIXIS_WRITE(sclk[0], sclk0);
PIXIS_WRITE(sclk[1], sclk1);
PIXIS_WRITE(sclk[2], sclk2);
}
int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned int i;
unsigned long sysclk;
char *p_altbank = NULL;
#ifdef DEBUG
char *p_dump = NULL;
@@ -182,6 +202,12 @@ int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
continue;
}
#endif
if (strcmp(argv[i], "sysclk") == 0) {
sysclk = simple_strtoul(argv[i + 1], NULL, 0);
i += 1;
pixis_sysclk_set(sysclk);
continue;
}
unknown_param = argv[i];
}
@@ -219,4 +245,5 @@ U_BOOT_CMD(
#ifdef DEBUG
"pixis_reset dump - display the PIXIS registers\n"
#endif
"pixis_reset sysclk <SYSCLK_freq> - reset with SYSCLK frequency(KHz)\n"
);

4
board/freescale/common/pixis.c
View File

@@ -380,7 +380,7 @@ static unsigned long strfractoint(char *strptr)
{
int i, j;
int mulconst;
int intarr_len, no_dec = 0;
int no_dec = 0;
unsigned long intval = 0, decval = 0;
char intarr[3], decarr[3];
@@ -399,8 +399,6 @@ static unsigned long strfractoint(char *strptr)
i++;
}
/* Assign length of integer part to intarr_len. */
intarr_len = i;
intarr[i] = '\0';
if (no_dec) {

8
board/freescale/corenet_ds/eth_hydra.c
View File

@@ -377,7 +377,6 @@ void fdt_fixup_board_enet(void *fdt)
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
struct fsl_pq_mdio_info dtsec_mdio_info;
struct tgec_mdio_info tgec_mdio_info;
unsigned int i, slot;
@@ -387,13 +386,6 @@ int board_eth_init(bd_t *bis)
initialize_lane_to_slot();
/*
* Set TBIPA on FM1@DTSEC1. This is needed for configurations
* where FM1@DTSEC1 isn't used directly, since it provides
* MDIO for other ports.
*/
out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE);
/* We want to use the PIXIS to configure MUX routing, not GPIOs. */
setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL);

8
board/freescale/corenet_ds/eth_p4080.c
View File

@@ -301,7 +301,6 @@ int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
int i;
struct fsl_pq_mdio_info dtsec_mdio_info;
struct tgec_mdio_info tgec_mdio_info;
@@ -327,13 +326,6 @@ int board_eth_init(bd_t *bis)
SLOT5, /* 17 - Bank 3:D */
};
/*
* Set TBIPA on FM1@DTSEC1. This is needed for configurations
* where FM1@DTSEC1 isn't used directly, since it provides
* MDIO for other ports.
*/
out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE);
/* Initialize the mdio_mux array so we can recognize empty elements */
for (i = 0; i < NUM_FM_PORTS; i++)
mdio_mux[i] = EMI_NONE;

69
board/freescale/mpc8548cds/mpc8548cds.c
View File

@@ -33,6 +33,9 @@
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <tsec.h>
#include <fsl_mdio.h>
#include <netdev.h>
#include "../common/cadmus.h"
#include "../common/eeprom.h"
@@ -81,12 +84,10 @@ local_bus_init(void)
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;
sys_info_t sysinfo;
get_sys_info(&sysinfo);
clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
gur->lbiuiplldcr1 = 0x00078080;
if (clkdiv == 16) {
@@ -115,7 +116,6 @@ void lbc_sdram_init(void)
uint idx;
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
uint cpu_board_rev;
uint lsdmr_common;
puts("LBC SDRAM: ");
@@ -137,7 +137,6 @@ void lbc_sdram_init(void)
/*
* MPC8548 uses "new" 15-16 style addressing.
*/
cpu_board_rev = get_cpu_board_revision();
lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
lsdmr_common |= LSDMR_BSMA1516;
@@ -287,7 +286,7 @@ void pci_init_board(void)
fsl_pcie_init_board(first_free_busno);
}
int last_stage_init(void)
void configure_rgmii(void)
{
unsigned short temp;
@@ -295,29 +294,77 @@ int last_stage_init(void)
/* This is needed to get the RGMII working for the 1.3+
* CDS cards */
if (get_board_version() == 0x13) {
miiphy_write(CONFIG_TSEC1_NAME,
miiphy_write(DEFAULT_MII_NAME,
TSEC1_PHY_ADDR, 29, 18);
miiphy_read(CONFIG_TSEC1_NAME,
miiphy_read(DEFAULT_MII_NAME,
TSEC1_PHY_ADDR, 30, &temp);
temp = (temp & 0xf03f);
temp |= 2 << 9; /* 36 ohm */
temp |= 2 << 6; /* 39 ohm */
miiphy_write(CONFIG_TSEC1_NAME,
miiphy_write(DEFAULT_MII_NAME,
TSEC1_PHY_ADDR, 30, temp);
miiphy_write(CONFIG_TSEC1_NAME,
miiphy_write(DEFAULT_MII_NAME,
TSEC1_PHY_ADDR, 29, 3);
miiphy_write(CONFIG_TSEC1_NAME,
miiphy_write(DEFAULT_MII_NAME,
TSEC1_PHY_ADDR, 30, 0x8000);
}
return 0;
return;
}
#ifdef CONFIG_TSEC_ENET
int board_eth_init(bd_t *bis)
{
struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[4];
int num = 0;
#ifdef CONFIG_TSEC1
SET_STD_TSEC_INFO(tsec_info[num], 1);
num++;
#endif
#ifdef CONFIG_TSEC2
SET_STD_TSEC_INFO(tsec_info[num], 2);
num++;
#endif
#ifdef CONFIG_TSEC3
/* initialize TSEC3 only if Carrier is 1.3 or above on CDS */
if (get_board_version() >= 0x13) {
SET_STD_TSEC_INFO(tsec_info[num], 3);
tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
num++;
}
#endif
#ifdef CONFIG_TSEC4
/* initialize TSEC4 only if Carrier is 1.3 or above on CDS */
if (get_board_version() >= 0x13) {
SET_STD_TSEC_INFO(tsec_info[num], 4);
tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
num++;
}
#endif
if (!num) {
printf("No TSECs initialized\n");
return 0;
}
mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
mdio_info.name = DEFAULT_MII_NAME;
fsl_pq_mdio_init(bis, &mdio_info);
tsec_eth_init(bis, tsec_info, num);
configure_rgmii();
return pci_eth_init(bis);
}
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_pci_setup(void *blob, bd_t *bd)

3
board/freescale/mpc8568mds/mpc8568mds.c
View File

@@ -147,12 +147,10 @@ local_bus_init(void)
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;
sys_info_t sysinfo;
get_sys_info(&sysinfo);
clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
gur->lbiuiplldcr1 = 0x00078080;
if (clkdiv == 16) {
@@ -302,6 +300,7 @@ pib_init(void)
i2c_write(0x27, 0x3, 1, &val8, 1);
asm("eieio");
i2c_set_bus_num(orig_i2c_bus);
}
#ifdef CONFIG_PCI

2
board/freescale/mpc8569mds/mpc8569mds.c
View File

@@ -303,12 +303,10 @@ local_bus_init(void)
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;
sys_info_t sysinfo;
get_sys_info(&sysinfo);
clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
out_be32(&gur->lbiuiplldcr1, 0x00078080);
if (clkdiv == 16)

2
board/freescale/mpc8572ds/tlb.c
View File

@@ -58,6 +58,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
#ifndef CONFIG_NAND_SPL
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -76,6 +77,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_256K, 1),
#endif
/* *I*G - NAND */
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,

2
board/freescale/p1010rdb/p1010rdb.c
View File

@@ -275,7 +275,9 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory(blob, (u64)base, (u64)size);
#if defined(CONFIG_HAS_FSL_DR_USB)
fdt_fixup_dr_usb(blob, bd);
#endif
/* P1014 and it's derivatives don't support CAN and eTSEC3 */
if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) {

2
board/freescale/p1_p2_rdb/p1_p2_rdb.c
View File

@@ -264,7 +264,9 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory(blob, (u64)base, (u64)size);
#if defined(CONFIG_HAS_FSL_DR_USB)
fdt_fixup_dr_usb(blob, bd);
#endif
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
/* Delete eLBC node as it is muxed with USB2 controller */

10
board/freescale/p1_p2_rdb_pc/law.c
View File

@@ -25,15 +25,17 @@
#include <asm/mmu.h>
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
#ifndef CONFIG_NAND_SPL
SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PMC_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
#ifdef CONFIG_VSC7385_ENET
SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
#endif
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
};
int num_law_entries = ARRAY_SIZE(law_table);

3
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
View File

@@ -444,6 +444,9 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_board_fixup_qe_pins(blob);
#endif
#endif
#if defined(CONFIG_HAS_FSL_DR_USB)
fdt_fixup_dr_usb(blob, bd);
#endif
}
#endif

8
board/freescale/p2041rdb/eth.c
View File

@@ -139,7 +139,6 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
struct fsl_pq_mdio_info dtsec_mdio_info;
struct tgec_mdio_info tgec_mdio_info;
unsigned int i, slot;
@@ -149,13 +148,6 @@ int board_eth_init(bd_t *bis)
initialize_lane_to_slot();
/*
* Set TBIPA on FM1@DTSEC1. This is needed for configurations
* where FM1@DTSEC1 isn't used directly, since it provides
* MDIO for other ports.
*/
out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE);
dtsec_mdio_info.regs =
(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;

2
board/sbc8548/sbc8548.c
View File

@@ -77,12 +77,10 @@ local_bus_init(void)
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;
sys_info_t sysinfo;
get_sys_info(&sysinfo);
clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
out_be32(&gur->lbiuiplldcr1, 0x00078080);
if (clkdiv == 16) {

3
board/sbc8560/sbc8560.c
View File

@@ -348,7 +348,7 @@ phys_size_t fixed_sdram(void)
void
ft_board_setup(void *blob, bd_t *bd)
{
int node, tmp[2];
int node;
#ifdef CONFIG_PCI
const char *path;
#endif
@@ -356,7 +356,6 @@ ft_board_setup(void *blob, bd_t *bd)
ft_cpu_setup(blob, bd);
node = fdt_path_offset(blob, "/aliases");
tmp[0] = 0;
if (node >= 0) {
#ifdef CONFIG_PCI
path = fdt_getprop(blob, node, "pci0", NULL);