Merge tag 'video-2021-07-rc1' of https://source.denx.de/u-boot/custodians/u-boot-video

- rk3399 eDP support
 - pwm backlight without a known period_ns
 - add Chrome OS EC PWM driver
 - Kconfig SIMPLE_PANEL DM_GPIO dependency
 - remove mb862xx driver remnants
 - fix KiB format in reserve_video() debug trace
 - fix tegra124 sor CSTM LVDS_EN_ENABLE/DISABLE config
 - fix line padding calculation for 16 and 24 BPP bitmaps

arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi

@@ -16,6 +16,10 @@
 	};
 };
 
+&edp {
+	rockchip,panel = <&edp_panel>;
+};
+
 &i2c0 {
 	u-boot,dm-pre-reloc;
 };

arch/arm/include/asm/arch-rockchip/edp_rk3288.h

@@ -232,8 +232,9 @@ check_member(rk3288_edp, pll_reg_5, 0xa00);
 #define PD_CH0					(0x1 << 0)
 
 /* pll_reg_1 */
-#define REF_CLK_24M				(0x1 << 1)
-#define REF_CLK_27M				(0x0 << 1)
+#define REF_CLK_24M				(0x1 << 0)
+#define REF_CLK_27M				(0x0 << 0)
+#define REF_CLK_MASK				(0x1 << 0)
 
 /* line_map */
 #define LANE3_MAP_LOGIC_LANE_0			(0x0 << 6)
@@ -296,7 +297,9 @@ check_member(rk3288_edp, pll_reg_5, 0xa00);
 
 /* int_ctl */
 #define SOFT_INT_CTRL				(0x1 << 2)
-#define INT_POL					(0x1 << 0)
+#define INT_POL1				(0x1 << 1)
+#define INT_POL0				(0x1 << 0)
+#define INT_POL					(INT_POL0 | INT_POL1)
 
 /* sys_ctl_1 */
 #define DET_STA					(0x1 << 2)

arch/arm/include/asm/arch-rockchip/vop_rk3288.h

@@ -85,26 +85,13 @@ enum {
 	LB_RGB_1280X8 = 0x5
 };
 
-#if defined(CONFIG_ROCKCHIP_RK3399)
 enum vop_modes {
 	VOP_MODE_EDP = 0,
 	VOP_MODE_MIPI,
 	VOP_MODE_HDMI,
-	VOP_MODE_MIPI1,
-	VOP_MODE_DP,
-	VOP_MODE_NONE,
-};
-#else
-enum vop_modes {
-	VOP_MODE_EDP = 0,
-	VOP_MODE_HDMI,
 	VOP_MODE_LVDS,
-	VOP_MODE_MIPI,
-	VOP_MODE_NONE,
-	VOP_MODE_AUTO_DETECT,
-	VOP_MODE_UNKNOWN,
+	VOP_MODE_DP,
 };
-#endif
 
 /* VOP_VERSION_INFO */
 #define M_FPGA_VERSION (0xffff << 16)