board/b4qds:Add support of 2 stage NAND boot-loader
Add support of 2 stage NAND boot loader using SPL framework. here, PBL initialise the internal SRAM and copy SPL(160KB). This further initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR. Finally SPL transer control to u-boot. Initialise/create followings required for SPL framework - Add spl.c which defines board_init_f, board_init_r - update tlb and ddr accordingly Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Prabhakar Kushwaha
York Sun
parent
89ad7be8e7
commit
c5dfe6ec58
@ -4,9 +4,14 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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ifdef CONFIG_SPL_BUILD
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obj-y += spl.o
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else
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obj-y += b4860qds.o
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obj-y += ddr.o
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obj-$(CONFIG_B4860QDS)+= eth_b4860qds.o
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obj-$(CONFIG_PCI) += pci.o
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obj-$(CONFIG_PCI) += pci.o
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endif
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obj-y += ddr.o
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obj-y += law.o
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obj-y += tlb.o
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@ -179,6 +179,7 @@ phys_size_t initdram(int board_type)
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{
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phys_size_t dram_size;
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#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
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puts("Initializing....using SPD\n");
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dram_size = fsl_ddr_sdram();
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@ -186,7 +187,9 @@ phys_size_t initdram(int board_type)
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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puts(" DDR: ");
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#else
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dram_size = fsl_ddr_sdram_size();
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#endif
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return dram_size;
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}
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114
board/freescale/b4860qds/spl.c
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114
board/freescale/b4860qds/spl.c
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@ -0,0 +1,114 @@
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/* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/spl.h>
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#include <malloc.h>
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#include <ns16550.h>
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#include <nand.h>
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#include <i2c.h>
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#include "../common/qixis.h"
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#include "b4860qds_qixis.h"
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DECLARE_GLOBAL_DATA_PTR;
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phys_size_t get_effective_memsize(void)
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{
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return CONFIG_SYS_L3_SIZE;
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}
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unsigned long get_board_sys_clk(void)
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{
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u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
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switch ((sysclk_conf & 0x0C) >> 2) {
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case QIXIS_CLK_100:
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return 100000000;
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case QIXIS_CLK_125:
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return 125000000;
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case QIXIS_CLK_133:
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return 133333333;
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}
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return 66666666;
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}
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unsigned long get_board_ddr_clk(void)
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{
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u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
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switch (ddrclk_conf & 0x03) {
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case QIXIS_CLK_100:
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return 100000000;
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case QIXIS_CLK_125:
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return 125000000;
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case QIXIS_CLK_133:
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return 133333333;
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}
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return 66666666;
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}
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void board_init_f(ulong bootflag)
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{
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u32 plat_ratio, sys_clk, uart_clk;
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
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memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
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/* Update GD pointer */
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gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
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/* compiler optimization barrier needed for GCC >= 3.4 */
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__asm__ __volatile__("" : : : "memory");
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console_init_f();
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/* initialize selected port with appropriate baud rate */
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sys_clk = get_board_sys_clk();
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plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
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uart_clk = sys_clk * plat_ratio / 2;
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NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
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uart_clk / 16 / CONFIG_BAUDRATE);
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relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
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}
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void board_init_r(gd_t *gd, ulong dest_addr)
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{
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bd_t *bd;
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bd = (bd_t *)(gd + sizeof(gd_t));
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memset(bd, 0, sizeof(bd_t));
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gd->bd = bd;
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bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
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bd->bi_memsize = CONFIG_SYS_L3_SIZE;
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probecpu();
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get_clocks();
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mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
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CONFIG_SPL_RELOC_MALLOC_SIZE);
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#ifndef CONFIG_SPL_NAND_BOOT
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env_init();
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env_relocate();
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#else
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/* relocate environment function pointers etc. */
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nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
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(uchar *)CONFIG_ENV_ADDR);
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gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
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gd->env_valid = 1;
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#endif
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i2c_init_all();
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puts("\n\n");
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gd->ram_size = initdram(0);
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#ifdef CONFIG_SPL_NAND_BOOT
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nand_boot();
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#endif
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}
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@ -62,6 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
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MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
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0, 2, BOOKE_PAGESZ_256M, 1),
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#ifndef CONFIG_SPL_BUILD
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/* *I*G* - PCI */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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@ -96,6 +97,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 9, BOOKE_PAGESZ_16M, 1),
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#endif
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#endif
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#ifdef CONFIG_SYS_DCSRBAR_PHYS
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SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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@ -118,6 +120,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
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* entry 14 and 15 has been used hard coded, they will be disabled
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* in cpu_init_f, so we use entry 16 for SRIO2.
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*/
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#ifndef CONFIG_SPL_BUILD
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#ifdef CONFIG_SYS_SRIO1_MEM_PHYS
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/* *I*G* - SRIO1 */
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SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
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@ -140,6 +143,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
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0, 17, BOOKE_PAGESZ_1M, 1),
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#endif
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#endif
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#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
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SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 17, BOOKE_PAGESZ_2G, 1)
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#endif
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};
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int num_tlb_entries = ARRAY_SIZE(tlb_table);
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@ -741,11 +741,11 @@ Active powerpc mpc85xx - - sbc8548
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Active powerpc mpc85xx - - socrates socrates - -
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Active powerpc mpc85xx - exmeritus hww1u1a HWW1U1A - Kyle Moffett <Kyle.D.Moffett@boeing.com>
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Active powerpc mpc85xx - freescale b4860qds B4420QDS B4860QDS:PPC_B4420 -
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Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
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Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND -
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Active powerpc mpc85xx - freescale b4860qds B4420QDS_SPIFLASH B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
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Active powerpc mpc85xx - freescale b4860qds B4860QDS B4860QDS:PPC_B4860 -
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Active powerpc mpc85xx - freescale b4860qds B4860QDS_SECURE_BOOT B4860QDS:PPC_B4860,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
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Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
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Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,SPL_FSL_PBL,NAND
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Active powerpc mpc85xx - freescale b4860qds B4860QDS_SPIFLASH B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
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Active powerpc mpc85xx - freescale b4860qds B4860QDS_SRIO_PCIE_BOOT B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
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Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_NAND BSC9131RDB:BSC9131RDB,NAND Poonam Aggrwal <poonam.aggrwal@freescale.com>
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@ -328,3 +328,39 @@ The below commands apply to both B4860QDS and B4420QDS.
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On Linux the interfaces are renamed as:
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. eth2 -> fm1-gb2
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. eth3 -> fm1-gb3
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NAND boot with 2 Stage boot loader
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----------------------------------
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PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.
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SPL further initialise DDR using SPD and environment variables and copy
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u-boot(768 KB) from flash to DDR.
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Finally SPL transer control to u-boot for futher booting.
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SPL has following features:
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- Executes within 256K
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- No relocation required
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Run time view of SPL framework during boot :-
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-----------------------------------------------
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Area | Address |
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-----------------------------------------------
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Secure boot | 0xFFFC0000 (32KB) |
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headers | |
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-----------------------------------------------
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GD, BD | 0xFFFC8000 (4KB) |
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-----------------------------------------------
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ENV | 0xFFFC9000 (8KB) |
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-----------------------------------------------
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HEAP | 0xFFFCB000 (30KB) |
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-----------------------------------------------
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STACK | 0xFFFD8000 (22KB) |
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-----------------------------------------------
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U-boot SPL | 0xFFFD8000 (160KB) |
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-----------------------------------------------
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NAND Flash memory Map on B4860 and B4420QDS
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------------------------------------------
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Start End Definition Size
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0x000000 0x0FFFFF u-boot 1MB
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0x140000 0x15FFFF u-boot env 128KB
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0x1A0000 0x1BFFFF FMAN Ucode 128KB
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@ -14,10 +14,43 @@
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#define CONFIG_PHYS_64BIT
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#ifdef CONFIG_RAMBOOT_PBL
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#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
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#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
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#ifndef CONFIG_NAND
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#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
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#define CONFIG_SYS_FSL_PBL_PBI board/freescale/b4860qds/b4_pbi.cfg
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#define CONFIG_SYS_FSL_PBL_RCW board/freescale/b4860qds/b4_rcw.cfg
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#else
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#define CONFIG_SPL
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#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
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#define CONFIG_SPL_ENV_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_I2C_SUPPORT
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#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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#define CONFIG_SYS_TEXT_BASE 0x00201000
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#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
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#define CONFIG_SPL_PAD_TO 0x40000
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#define CONFIG_SPL_MAX_SIZE 0x28000
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#define RESET_VECTOR_OFFSET 0x27FFC
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#define BOOT_PAGE_OFFSET 0x27000
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#define CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
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#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
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#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
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#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
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#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
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#define CONFIG_SPL_NAND_BOOT
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SPL_SKIP_RELOCATE
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#define CONFIG_SPL_COMMON_INIT_DDR
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#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
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#define CONFIG_SYS_NO_FLASH
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#endif
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#endif
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#endif
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#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
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@ -113,8 +146,8 @@
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#elif defined(CONFIG_NAND)
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#define CONFIG_SYS_EXTRA_ENV_RELOC
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
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#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
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#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
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#define CONFIG_ENV_IS_IN_REMOTE
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#define CONFIG_ENV_ADDR 0xffe20000
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@ -164,7 +197,16 @@ unsigned long get_board_ddr_clk(void);
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/*
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* Config the L3 Cache as L3 SRAM
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*/
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#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
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#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
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#define CONFIG_SYS_L3_SIZE 256 << 10
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#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
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#ifdef CONFIG_NAND
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#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
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#endif
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#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
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#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
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#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
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#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_DCSRBAR 0xf0000000
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@ -193,7 +235,9 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_DDR_SPD
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#define CONFIG_SYS_DDR_RAW_TIMING
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#define CONFIG_SYS_FSL_DDR3
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_FSL_DDR_INTERACTIVE
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#endif
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#define CONFIG_SYS_SPD_BUS_NUM 0
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#define SPD_EEPROM_ADDRESS1 0x51
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@ -381,7 +425,11 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
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#else
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#endif
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#if defined(CONFIG_RAMBOOT_PBL)
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#define CONFIG_SYS_RAMBOOT
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@ -435,7 +483,9 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
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#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
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#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
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#endif
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/* Use the HUSH parser */
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@ -607,7 +657,7 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
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#elif defined(CONFIG_NAND)
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#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
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#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
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#define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
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#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
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/*
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* Slave has no ucode locally, it can fetch this from remote. When implementing
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