powerpc: add support for the Freescale P1022DS reference board
Specifics: 1) 36-bit only 2) Booting from NOR flash only 3) Environment stored in NOR flash only 4) No SPI support 5) No DIU support Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Timur Tabi
Kumar Gala
parent
ddac6f08db
commit
c59e1b4d07
@ -448,6 +448,7 @@ Timur Tabi <timur@freescale.com>
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MPC8349E-mITX MPC8349
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MPC8349E-mITX-GP MPC8349
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P1022DS P1022
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Erik Theisen <etheisen@mindspring.com>
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1
MAKEALL
1
MAKEALL
@ -410,6 +410,7 @@ LIST_85xx=" \
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MPC8569MDS_NAND \
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MPC8572DS \
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MPC8572DS_36BIT \
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P1022DS \
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P2020DS \
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P2020DS_36BIT \
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P1011RDB \
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@ -63,6 +63,7 @@ COBJS-$(CONFIG_CPM2) += ether_fcc.o
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COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
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COBJS-$(CONFIG_MP) += mp.o
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COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
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COBJS-$(CONFIG_P1022) += p1022_serdes.o
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COBJS-$(CONFIG_PCI) += pci.o
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COBJS-$(CONFIG_QE) += qe_io.o
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COBJS-$(CONFIG_CPM2) += serial_scc.o
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166
arch/powerpc/cpu/mpc85xx/p1022_serdes.c
Normal file
166
arch/powerpc/cpu/mpc85xx/p1022_serdes.c
Normal file
@ -0,0 +1,166 @@
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/*
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* Copyright 2010 Freescale Semiconductor, Inc.
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* Author: Timur Tabi <timur@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_serdes.h>
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#define SRDS1_MAX_LANES 4
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#define SRDS2_MAX_LANES 2
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static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
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[0x00] = {NONE, NONE, NONE, NONE},
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[0x01] = {NONE, NONE, NONE, NONE},
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[0x02] = {NONE, NONE, NONE, NONE},
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[0x03] = {NONE, NONE, NONE, NONE},
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[0x04] = {NONE, NONE, NONE, NONE},
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[0x06] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2},
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[0x07] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2},
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[0x09] = {PCIE1, NONE, NONE, NONE},
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[0x0a] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2},
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[0x0b] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2},
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[0x0d] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
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[0x0e] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
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[0x0f] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
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[0x15] = {PCIE1, PCIE3, PCIE2, PCIE2},
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[0x16] = {PCIE1, PCIE3, PCIE2, PCIE2},
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[0x17] = {PCIE1, PCIE3, PCIE2, PCIE2},
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[0x18] = {PCIE1, PCIE1, PCIE2, PCIE2},
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[0x19] = {PCIE1, PCIE1, PCIE2, PCIE2},
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[0x1a] = {PCIE1, PCIE1, PCIE2, PCIE2},
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[0x1b] = {PCIE1, PCIE1, PCIE2, PCIE2},
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[0x1c] = {PCIE1, PCIE1, PCIE1, PCIE1},
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[0x1d] = {PCIE1, PCIE1, PCIE2, PCIE2},
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[0x1e] = {PCIE1, PCIE1, PCIE2, PCIE2},
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[0x1f] = {PCIE1, PCIE1, PCIE2, PCIE2},
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};
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static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
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[0x00] = {PCIE3, PCIE3},
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[0x01] = {PCIE2, PCIE3},
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[0x02] = {SATA1, SATA2},
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[0x03] = {SGMII_TSEC1, SGMII_TSEC2},
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[0x04] = {NONE, NONE},
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[0x06] = {SATA1, SATA2},
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[0x07] = {NONE, NONE},
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[0x09] = {PCIE3, PCIE2},
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[0x0a] = {SATA1, SATA2},
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[0x0b] = {NONE, NONE},
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[0x0d] = {PCIE3, PCIE2},
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[0x0e] = {SATA1, SATA2},
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[0x0f] = {NONE, NONE},
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[0x15] = {SGMII_TSEC1, SGMII_TSEC2},
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[0x16] = {SATA1, SATA2},
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[0x17] = {NONE, NONE},
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[0x18] = {PCIE3, PCIE3},
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[0x19] = {SGMII_TSEC1, SGMII_TSEC2},
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[0x1a] = {SATA1, SATA2},
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[0x1b] = {NONE, NONE},
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[0x1c] = {PCIE3, PCIE3},
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[0x1d] = {SGMII_TSEC1, SGMII_TSEC2},
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[0x1e] = {SATA1, SATA2},
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[0x1f] = {NONE, NONE},
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};
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/*
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* A list of PCI and SATA slots
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*/
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enum slot_id {
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SLOT_PCIE1 = 1,
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SLOT_PCIE2,
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SLOT_PCIE3,
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SLOT_PCIE4,
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SLOT_PCIE5,
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SLOT_SATA1,
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SLOT_SATA2
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};
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/*
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* This array maps the slot identifiers to their names on the P1022DS board.
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*/
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static const char *slot_names[] = {
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[SLOT_PCIE1] = "Slot 1",
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[SLOT_PCIE2] = "Slot 2",
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[SLOT_PCIE3] = "Slot 3",
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[SLOT_PCIE4] = "Slot 4",
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[SLOT_PCIE5] = "Mini-PCIe",
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[SLOT_SATA1] = "SATA 1",
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[SLOT_SATA2] = "SATA 2",
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};
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/*
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* This array maps a given SERDES configuration and SERDES device to the PCI or
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* SATA slot that it connects to. This mapping is hard-coded in the FPGA.
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*/
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static u8 serdes_dev_slot[][SATA2 + 1] = {
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[0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
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[0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
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[0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
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[PCIE2] = SLOT_PCIE5 },
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[0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
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[PCIE2] = SLOT_PCIE3,
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[SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
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[0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
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[PCIE2] = SLOT_PCIE3 },
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[0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
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[PCIE2] = SLOT_PCIE3,
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[SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
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[0x1c] = { [PCIE1] = SLOT_PCIE1,
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[SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
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[0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
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[0x1f] = { [PCIE1] = SLOT_PCIE1 },
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};
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int is_serdes_configured(enum srds_prtcl device)
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{
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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u32 pordevsr = in_be32(&gur->pordevsr);
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u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
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MPC85xx_PORDEVSR_IO_SEL_SHIFT;
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unsigned int i;
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debug("%s: dev = %d\n", __FUNCTION__, device);
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debug("PORDEVSR[IO_SEL] = 0x%x\n", srds_cfg);
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if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
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printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds_cfg);
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return 0;
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}
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for (i = 0; i < SRDS1_MAX_LANES; i++) {
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if (serdes1_cfg_tbl[srds_cfg][i] == device)
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return 1;
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if (serdes2_cfg_tbl[srds_cfg][i] == device)
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return 1;
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}
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return 0;
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}
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/*
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* Returns the name of the slot to which the PCIe or SATA controller is
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* connected
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*/
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const char *serdes_slot_name(enum srds_prtcl device)
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{
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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u32 pordevsr = in_be32(&gur->pordevsr);
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unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
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MPC85xx_PORDEVSR_IO_SEL_SHIFT;
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enum slot_id slot = serdes_dev_slot[srds_cfg][device];
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const char *name = slot_names[slot];
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if (name)
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return name;
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else
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return "Nothing";
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}
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@ -45,4 +45,6 @@ enum srds_prtcl {
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int is_serdes_configured(enum srds_prtcl device);
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const char *serdes_slot_name(enum srds_prtcl device);
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#endif /* __FSL_SERDES_H */
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@ -42,6 +42,7 @@ COBJS-$(CONFIG_MPC8541CDS) += cds_pci_ft.o
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COBJS-$(CONFIG_MPC8548CDS) += cds_pci_ft.o
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COBJS-$(CONFIG_MPC8555CDS) += cds_pci_ft.o
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COBJS-$(CONFIG_P1022DS) += ics307_clk.o
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COBJS-$(CONFIG_P2020DS) += ics307_clk.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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39
board/freescale/p1022ds/Makefile
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39
board/freescale/p1022ds/Makefile
Normal file
@ -0,0 +1,39 @@
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#
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# Copyright 2010 Freescale Semiconductor, Inc.
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of the GNU General Public License as published by the Free
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# Software Foundation; either version 2 of the License, or (at your option)
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# any later version.
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS-y += $(BOARD).o
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COBJS-y += ddr.o
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COBJS-y += law.o
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COBJS-y += tlb.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean:
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rm -f $(OBJS) $(SOBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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14
board/freescale/p1022ds/config.mk
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14
board/freescale/p1022ds/config.mk
Normal file
@ -0,0 +1,14 @@
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#
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# Copyright 2010 Freescale Semiconductor, Inc.
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of the GNU General Public License as published by the Free
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# Software Foundation; either version 2 of the License, or (at your option)
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# any later version.
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#
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ifndef TEXT_BASE
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TEXT_BASE = 0xeff80000
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endif
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RESET_VECTOR_ADDRESS = 0xeffffffc
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106
board/freescale/p1022ds/ddr.c
Normal file
106
board/freescale/p1022ds/ddr.c
Normal file
@ -0,0 +1,106 @@
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/*
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* Copyright 2010 Freescale Semiconductor, Inc.
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* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
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* Timur Tabi <timur@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_ddr_dimm_params.h>
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unsigned int fsl_ddr_get_mem_data_rate(void)
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{
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return get_ddr_freq(0);
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}
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void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num)
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{
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int ret;
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/*
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* The P1022 has only one DDR controller, and the board has only one
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* DIMM slot.
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*/
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ret = i2c_read(SPD_EEPROM_ADDRESS1, 0, 1, (u8 *)ctrl_dimms_spd,
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sizeof(ddr3_spd_eeprom_t));
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if (ret) {
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debug("DDR: failed to read SPD from address %u\n",
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SPD_EEPROM_ADDRESS1);
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memset(ctrl_dimms_spd, 0, sizeof(ddr3_spd_eeprom_t));
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}
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}
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typedef struct {
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u32 datarate_mhz_low;
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u32 datarate_mhz_high;
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u32 n_ranks;
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u32 clk_adjust; /* Range: 0-8 */
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u32 cpo; /* Range: 2-31 */
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u32 write_data_delay; /* Range: 0-6 */
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u32 force_2T;
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} board_specific_parameters_t;
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static const board_specific_parameters_t bsp[] = {
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/*
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* lo| hi| num| clk| cpo|wrdata|2T
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* mhz| mhz|ranks|adjst| | delay|
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*/
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{ 0, 333, 1, 5, 31, 3, 0},
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{334, 400, 1, 5, 31, 3, 0},
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{401, 549, 1, 5, 31, 3, 0},
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{550, 680, 1, 5, 31, 5, 0},
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{681, 850, 1, 5, 31, 5, 0},
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{ 0, 333, 2, 5, 31, 3, 0},
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{334, 400, 2, 5, 31, 3, 0},
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{401, 549, 2, 5, 31, 3, 0},
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{550, 680, 2, 5, 31, 5, 0},
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{681, 850, 2, 5, 31, 5, 0},
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};
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void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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unsigned long ddr_freq;
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unsigned int i;
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/* set odt_rd_cfg and odt_wr_cfg. */
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for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
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popts->cs_local_opts[i].odt_rd_cfg = 0;
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popts->cs_local_opts[i].odt_wr_cfg = 1;
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}
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/*
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* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
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* freqency and n_banks specified in board_specific_parameters table.
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*/
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ddr_freq = get_ddr_freq(0) / 1000000;
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for (i = 0; i < ARRAY_SIZE(bsp); i++) {
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if (ddr_freq >= bsp[i].datarate_mhz_low &&
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ddr_freq <= bsp[i].datarate_mhz_high &&
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pdimm->n_ranks == bsp[i].n_ranks) {
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popts->clk_adjust = bsp[i].clk_adjust;
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popts->cpo_override = bsp[i].cpo;
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popts->write_data_delay = bsp[i].write_data_delay;
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popts->twoT_en = bsp[i].force_2T;
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break;
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}
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}
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popts->half_strength_driver_enable = 1;
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/* Per AN4039, enable ZQ calibration. */
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popts->zq_en = 1;
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/*
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* For wake-up on ARP, we need auto self refresh enabled
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*/
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popts->auto_self_refresh_en = 1;
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popts->sr_it = 0xb;
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}
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21
board/freescale/p1022ds/law.c
Normal file
21
board/freescale/p1022ds/law.c
Normal file
@ -0,0 +1,21 @@
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/*
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* Copyright 2010 Freescale Semiconductor, Inc.
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* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
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* Timur Tabi <timur@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*/
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#include <common.h>
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#include <asm/fsl_law.h>
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#include <asm/mmu.h>
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|
||||
struct law_entry law_table[] = {
|
||||
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
|
||||
SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
|
||||
};
|
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table);
|
||||
285
board/freescale/p1022ds/p1022ds.c
Normal file
285
board/freescale/p1022ds/p1022ds.c
Normal file
@ -0,0 +1,285 @@
|
||||
/*
|
||||
* Copyright 2010 Freescale Semiconductor, Inc.
|
||||
* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
|
||||
* Timur Tabi <timur@freescale.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <pci.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/cache.h>
|
||||
#include <asm/immap_85xx.h>
|
||||
#include <asm/fsl_pci.h>
|
||||
#include <asm/fsl_ddr_sdram.h>
|
||||
#include <asm/fsl_serdes.h>
|
||||
#include <asm/io.h>
|
||||
#include <libfdt.h>
|
||||
#include <fdt_support.h>
|
||||
#include <tsec.h>
|
||||
#include <asm/fsl_law.h>
|
||||
#include <asm/mp.h>
|
||||
#include <netdev.h>
|
||||
#include <i2c.h>
|
||||
|
||||
#include "../common/ngpixis.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
||||
|
||||
/* Set pmuxcr to allow both i2c1 and i2c2 */
|
||||
setbits_be32(&gur->pmuxcr, 0x1000);
|
||||
|
||||
/* Read back the register to synchronize the write. */
|
||||
in_be32(&gur->pmuxcr);
|
||||
|
||||
/* Set the pin muxing to enable ETSEC2. */
|
||||
clrbits_be32(&gur->pmuxcr2, 0x001F8000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
u8 sw;
|
||||
|
||||
puts("Board: P1022DS ");
|
||||
|
||||
printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
|
||||
in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
|
||||
|
||||
sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
|
||||
|
||||
switch ((sw & PIXIS_LBMAP_MASK) >> 6) {
|
||||
case 0:
|
||||
printf ("vBank: %u\n", ((sw & 0x30) >> 4));
|
||||
break;
|
||||
case 1:
|
||||
printf ("NAND\n");
|
||||
break;
|
||||
case 2:
|
||||
case 3:
|
||||
puts ("Promjet\n");
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
phys_size_t initdram(int board_type)
|
||||
{
|
||||
phys_size_t dram_size = 0;
|
||||
|
||||
puts("Initializing....\n");
|
||||
|
||||
dram_size = fsl_ddr_sdram();
|
||||
dram_size = setup_ddr_tlbs(dram_size / 0x100000) * 0x100000;
|
||||
|
||||
puts(" DDR: ");
|
||||
return dram_size;
|
||||
}
|
||||
|
||||
#define CONFIG_TFP410_I2C_ADDR 0x38
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
u8 temp;
|
||||
|
||||
/* Enable the TFP410 Encoder */
|
||||
|
||||
temp = 0xBF;
|
||||
if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
|
||||
return -1;
|
||||
|
||||
/* Verify if enabled */
|
||||
temp = 0;
|
||||
if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
|
||||
return -1;
|
||||
|
||||
debug("DVI Encoder Read: 0x%02x\n", temp);
|
||||
|
||||
temp = 0x10;
|
||||
if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
|
||||
return -1;
|
||||
|
||||
/* Verify if enabled */
|
||||
temp = 0;
|
||||
if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
|
||||
return -1;
|
||||
|
||||
debug("DVI Encoder Read: 0x%02x\n",temp);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void configure_pcie(struct fsl_pci_info *info,
|
||||
struct pci_controller *hose,
|
||||
const char *connected)
|
||||
{
|
||||
static int bus_number = 0;
|
||||
int is_endpoint;
|
||||
|
||||
set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
|
||||
set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
|
||||
is_endpoint = fsl_setup_hose(hose, info->regs);
|
||||
printf(" PCIE%u connected to %s as %s (base addr %lx)\n",
|
||||
info->pci_num, connected,
|
||||
is_endpoint ? "Endpoint" : "Root Complex", info->regs);
|
||||
bus_number = fsl_pci_init_port(info, hose, bus_number);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCIE1
|
||||
static struct pci_controller pcie1_hose;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCIE2
|
||||
static struct pci_controller pcie2_hose;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCIE3
|
||||
static struct pci_controller pcie3_hose;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
void pci_init_board(void)
|
||||
{
|
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
||||
struct fsl_pci_info pci_info;
|
||||
u32 devdisr = in_be32(&gur->devdisr);
|
||||
|
||||
#ifdef CONFIG_PCIE1
|
||||
if (is_serdes_configured(PCIE1) && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
|
||||
SET_STD_PCIE_INFO(pci_info, 1);
|
||||
configure_pcie(&pci_info, &pcie1_hose, serdes_slot_name(PCIE1));
|
||||
} else {
|
||||
printf(" PCIE1: disabled\n");
|
||||
}
|
||||
#else
|
||||
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCIE2
|
||||
if (is_serdes_configured(PCIE2) && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
|
||||
SET_STD_PCIE_INFO(pci_info, 2);
|
||||
configure_pcie(&pci_info, &pcie2_hose, serdes_slot_name(PCIE2));
|
||||
} else {
|
||||
printf(" PCIE2: disabled\n");
|
||||
}
|
||||
#else
|
||||
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCIE3
|
||||
if (is_serdes_configured(PCIE3) && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
|
||||
SET_STD_PCIE_INFO(pci_info, 3);
|
||||
configure_pcie(&pci_info, &pcie3_hose, serdes_slot_name(PCIE3));
|
||||
} else {
|
||||
printf(" PCIE3: disabled\n");
|
||||
}
|
||||
#else
|
||||
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_early_init_r(void)
|
||||
{
|
||||
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
|
||||
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
|
||||
|
||||
/*
|
||||
* Remap Boot flash + PROMJET region to caching-inhibited
|
||||
* so that flash can be erased properly.
|
||||
*/
|
||||
|
||||
/* Flush d-cache and invalidate i-cache of any FLASH data */
|
||||
flush_dcache();
|
||||
invalidate_icache();
|
||||
|
||||
/* invalidate existing TLB entry for flash + promjet */
|
||||
disable_tlb(flash_esel);
|
||||
|
||||
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, flash_esel, BOOKE_PAGESZ_256M, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize on-board and/or PCI Ethernet devices
|
||||
*
|
||||
* Returns:
|
||||
* <0, error
|
||||
* 0, no ethernet devices found
|
||||
* >0, number of ethernet devices initialized
|
||||
*/
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
struct tsec_info_struct tsec_info[2];
|
||||
unsigned int num = 0;
|
||||
|
||||
#ifdef CONFIG_TSEC1
|
||||
SET_STD_TSEC_INFO(tsec_info[num], 1);
|
||||
num++;
|
||||
#endif
|
||||
#ifdef CONFIG_TSEC2
|
||||
SET_STD_TSEC_INFO(tsec_info[num], 2);
|
||||
num++;
|
||||
#endif
|
||||
|
||||
return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF_BOARD_SETUP
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
phys_addr_t base;
|
||||
phys_size_t size;
|
||||
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
base = getenv_bootm_low();
|
||||
size = getenv_bootm_size();
|
||||
|
||||
fdt_fixup_memory(blob, (u64)base, (u64)size);
|
||||
|
||||
#ifdef CONFIG_PCIE1
|
||||
ft_fsl_pci_setup(blob, "pci0", &pcie1_hose);
|
||||
#else
|
||||
ft_fsl_pci_setup(blob, "pci0", NULL);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCIE2
|
||||
ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
|
||||
#else
|
||||
ft_fsl_pci_setup(blob, "pci1", NULL);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCIE3
|
||||
ft_fsl_pci_setup(blob, "pci2", &pcie3_hose);
|
||||
#else
|
||||
ft_fsl_pci_setup(blob, "pci2", NULL);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_SGMII_RISER
|
||||
fsl_sgmii_riser_fdt_fixup(blob);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MP
|
||||
void board_lmb_reserve(struct lmb *lmb)
|
||||
{
|
||||
cpu_mp_lmb_reserve(lmb);
|
||||
}
|
||||
#endif
|
||||
76
board/freescale/p1022ds/tlb.c
Normal file
76
board/freescale/p1022ds/tlb.c
Normal file
@ -0,0 +1,76 @@
|
||||
/*
|
||||
* Copyright 2010 Freescale Semiconductor, Inc.
|
||||
* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
|
||||
* Timur Tabi <timur@freescale.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = {
|
||||
/* TLB 0 - for temp stack in cache */
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
||||
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
||||
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
||||
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
|
||||
/* TLB 1 */
|
||||
/* *I*** - Covers boot page */
|
||||
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
|
||||
0, 0, BOOKE_PAGESZ_4K, 1),
|
||||
|
||||
/* *I*G* - CCSRBAR */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 1, BOOKE_PAGESZ_1M, 1),
|
||||
|
||||
/* W**G* - Flash/promjet, localbus */
|
||||
/* This will be changed to *I*G* after relocation to RAM. */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
|
||||
0, 2, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/* *I*G* - PCI */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 3, BOOKE_PAGESZ_1G, 1),
|
||||
|
||||
/* *I*G* - PCI */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
|
||||
CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 4, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
|
||||
CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 5, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/* *I*G* - PCI I/O */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 6, BOOKE_PAGESZ_256K, 1),
|
||||
|
||||
SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 7, BOOKE_PAGESZ_4K, 1),
|
||||
};
|
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table);
|
||||
@ -342,6 +342,7 @@ MPC8560ADS powerpc mpc85xx mpc8560ads freescale
|
||||
MPC8568MDS powerpc mpc85xx mpc8568mds freescale
|
||||
XPEDITE5200 powerpc mpc85xx xpedite5200 xes
|
||||
XPEDITE5370 powerpc mpc85xx xpedite5370 xes
|
||||
P1022DS powerpc mpc85xx p1022ds freescale
|
||||
sbc8641d powerpc mpc86xx
|
||||
MPC8610HPCD powerpc mpc86xx mpc8610hpcd freescale
|
||||
XPEDITE5170 powerpc mpc86xx xpedite5170 xes
|
||||
|
||||
470
include/configs/P1022DS.h
Normal file
470
include/configs/P1022DS.h
Normal file
@ -0,0 +1,470 @@
|
||||
/*
|
||||
* Copyright 2010 Freescale Semiconductor, Inc.
|
||||
* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
|
||||
* Timur Tabi <timur@freescale.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include "../board/freescale/common/ics307_clk.h"
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_BOOKE /* BOOKE */
|
||||
#define CONFIG_E500 /* BOOKE e500 family */
|
||||
#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */
|
||||
#define CONFIG_P1022
|
||||
#define CONFIG_P1022DS
|
||||
#define CONFIG_MP /* support multiple processors */
|
||||
|
||||
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
|
||||
#define CONFIG_PCI /* Enable PCI/PCIE */
|
||||
#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
|
||||
#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
|
||||
#define CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */
|
||||
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
||||
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
|
||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
||||
|
||||
#define CONFIG_PHYS_64BIT
|
||||
#define CONFIG_ENABLE_36BIT_PHYS
|
||||
#define CONFIG_ADDR_MAP
|
||||
#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
|
||||
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
|
||||
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
|
||||
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
|
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default.
|
||||
*/
|
||||
#define CONFIG_L2_CACHE
|
||||
#define CONFIG_BTB
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00000000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x7fffffff
|
||||
|
||||
/*
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*/
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
||||
#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
|
||||
|
||||
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) /* pci0 */
|
||||
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0xa000) /* pci1 */
|
||||
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR + 0xb000) /* pci2 */
|
||||
|
||||
/* DDR Setup */
|
||||
#define CONFIG_DDR_SPD
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
#define CONFIG_FSL_DDR3
|
||||
|
||||
#ifdef CONFIG_DDR_ECC
|
||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
|
||||
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
||||
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
|
||||
|
||||
/* I2C addresses of SPD EEPROMs */
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 1
|
||||
#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
|
||||
|
||||
/*
|
||||
* Memory map
|
||||
*
|
||||
* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
|
||||
* 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
|
||||
* 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
|
||||
*
|
||||
* Localbus cacheable (TBD)
|
||||
* 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
|
||||
*
|
||||
* Localbus non-cacheable
|
||||
* 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
|
||||
* 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
|
||||
* 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
|
||||
* 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
|
||||
* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
|
||||
*/
|
||||
|
||||
/*
|
||||
* Local Bus Definitions
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
|
||||
#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
|
||||
|
||||
#define CONFIG_FLASH_BR_PRELIM \
|
||||
(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
|
||||
#define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
|
||||
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
|
||||
|
||||
#define CONFIG_SYS_BR1_PRELIM \
|
||||
(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
|
||||
#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM
|
||||
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST \
|
||||
{CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
|
||||
#define CONFIG_SYS_FLASH_QUIET_TEST
|
||||
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
|
||||
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_BOARD_EARLY_INIT_R
|
||||
#define CONFIG_MISC_INIT_R
|
||||
|
||||
#define CONFIG_FSL_NGPIXIS
|
||||
#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
|
||||
#define PIXIS_BASE_PHYS 0xfffdf0000ull
|
||||
|
||||
#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
|
||||
#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
|
||||
|
||||
#define PIXIS_LBMAP_SWITCH 7
|
||||
#define PIXIS_LBMAP_MASK 0xE0
|
||||
#define PIXIS_LBMAP_ALTBANK 0x20
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
|
||||
#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
|
||||
#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
|
||||
|
||||
/*
|
||||
* Serial Port
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
|
||||
|
||||
/* Use the HUSH parser */
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
#define CONFIG_FSL_DIU_FB
|
||||
#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
|
||||
|
||||
/* Video */
|
||||
/* #define CONFIG_VIDEO */
|
||||
#ifdef CONFIG_VIDEO
|
||||
#define CONFIG_CFB_CONSOLE
|
||||
#define CONFIG_VGA_AS_SINGLE_DEVICE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Pass open firmware flat tree
|
||||
*/
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_OF_BOARD_SETUP
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS
|
||||
|
||||
/* new uImage format support */
|
||||
#define CONFIG_FIT
|
||||
#define CONFIG_FIT_VERBOSE
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
|
||||
/*
|
||||
* I2C2 EEPROM
|
||||
*/
|
||||
#define CONFIG_ID_EEPROM
|
||||
#define CONFIG_SYS_I2C_EEPROM_NXID
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_EEPROM_BUS_NUM 1
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
* Memory space is mapped 1-1, but I/O space must start from 0.
|
||||
*/
|
||||
|
||||
/* controller 1, Slot 2, tgtid 1, Base address a000 */
|
||||
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
|
||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
|
||||
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
|
||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
|
||||
|
||||
/* controller 2, direct to uli, tgtid 2, Base address 9000 */
|
||||
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
|
||||
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
|
||||
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
|
||||
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
|
||||
|
||||
/* controller 3, Slot 1, tgtid 3, Base address b000 */
|
||||
#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
|
||||
#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
|
||||
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
|
||||
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
|
||||
#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
|
||||
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#endif
|
||||
|
||||
/* SATA */
|
||||
#define CONFIG_LIBATA
|
||||
#define CONFIG_FSL_SATA
|
||||
|
||||
#define CONFIG_SYS_SATA_MAX_DEVICE 2
|
||||
#define CONFIG_SATA1
|
||||
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
|
||||
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
|
||||
#define CONFIG_SATA2
|
||||
#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
|
||||
#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
|
||||
|
||||
#ifdef CONFIG_FSL_SATA
|
||||
#define CONFIG_LBA48
|
||||
#define CONFIG_CMD_SATA
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_CMD_EXT2
|
||||
#endif
|
||||
|
||||
#define CONFIG_MMC
|
||||
#ifdef CONFIG_MMC
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_FSL_ESDHC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#endif
|
||||
|
||||
#define CONFIG_TSEC_ENET
|
||||
#ifdef CONFIG_TSEC_ENET
|
||||
|
||||
#define CONFIG_TSECV2
|
||||
#define CONFIG_NET_MULTI
|
||||
|
||||
#define CONFIG_MII /* MII PHY management */
|
||||
#define CONFIG_TSEC1 1
|
||||
#define CONFIG_TSEC1_NAME "eTSEC1"
|
||||
#define CONFIG_TSEC2 1
|
||||
#define CONFIG_TSEC2_NAME "eTSEC2"
|
||||
|
||||
#define TSEC1_PHY_ADDR 1
|
||||
#define TSEC2_PHY_ADDR 2
|
||||
|
||||
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
|
||||
#define TSEC1_PHYIDX 0
|
||||
#define TSEC2_PHYIDX 0
|
||||
|
||||
#define CONFIG_ETHPRIME "eTSEC1"
|
||||
|
||||
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000
|
||||
|
||||
#define CONFIG_LOADS_ECHO
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_IRQ
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_IRQ
|
||||
#define CONFIG_CMD_SETEXPR
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_NET
|
||||
#endif
|
||||
|
||||
/*
|
||||
* USB
|
||||
*/
|
||||
#define CONFIG_USB_EHCI
|
||||
|
||||
#ifdef CONFIG_USB_EHCI
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#define CONFIG_USB_EHCI_FSL
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_CMD_FAT
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#ifdef CONFIG_CMD_KGDB
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 16 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#ifdef CONFIG_CMD_KGDB
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment Configuration
|
||||
*/
|
||||
|
||||
#define CONFIG_HOSTNAME p1022ds
|
||||
#define CONFIG_ROOTPATH /opt/nfsroot
|
||||
#define CONFIG_BOOTFILE uImage
|
||||
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
|
||||
|
||||
#define CONFIG_LOADADDR 1000000
|
||||
|
||||
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
|
||||
#define CONFIG_BOOTARGS
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"perf_mode=stable\0" \
|
||||
"memctl_intlv_ctl=2\0" \
|
||||
"netdev=eth0\0" \
|
||||
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
|
||||
"tftpflash=tftpboot $loadaddr $uboot; " \
|
||||
"protect off " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"erase " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
|
||||
"protect on " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=2000000\0" \
|
||||
"ramdiskfile=uramdisk\0" \
|
||||
"fdtaddr=c00000\0" \
|
||||
"fdtfile=p1022ds.dtb\0" \
|
||||
"bdev=sda3\0" \
|
||||
"diuregs=md e002c000 1d\0" \
|
||||
"dium=mw e002c01c\0" \
|
||||
"diuerr=md e002c014 1\0" \
|
||||
"othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 tty0\0" \
|
||||
"monitor=0-DVI\0"
|
||||
|
||||
#define CONFIG_HDBOOT \
|
||||
"setenv bootargs root=/dev/$bdev rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user