ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 1
Factor out common code from rw_mgr_mem_calibrate_writes_center() and rw_mgr_mem_calibrate_vfifo_center() for searching for the right edge of the window. The code is almost identical, so pull it into separate function and cater for the minor differences. Signed-off-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Marek Vasut
parent
db3a606158
commit
c4907898a1
@ -1780,6 +1780,166 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
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return ret;
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}
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/**
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* search_right_edge() - Find right edge of DQ/DQS working phase
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* @write: Perform read (Stage 2) or write (Stage 3) calibration
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* @rank_bgn: Rank number
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* @write_group: Write Group
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* @read_group: Read Group
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* @start_dqs: DQS start phase
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* @start_dqs_en: DQS enable start phase
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* @bit_chk: Resulting bit mask after the test
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* @sticky_bit_chk: Resulting sticky bit mask after the test
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* @left_edge: Left edge of the DQ/DQS phase
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* @right_edge: Right edge of the DQ/DQS phase
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* @use_read_test: Perform read test
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*
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* Find right edge of DQ/DQS working phase.
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*/
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static int search_right_edge(const int write, const int rank_bgn,
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const u32 write_group, const u32 read_group,
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const int start_dqs, const int start_dqs_en,
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u32 *bit_chk, u32 *sticky_bit_chk,
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int *left_edge, int *right_edge, const u32 use_read_test)
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{
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const u32 correct_mask = write ? param->write_correct_mask :
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param->read_correct_mask;
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const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
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const u32 dqs_max = write ? IO_IO_OUT1_DELAY_MAX : IO_DQS_IN_DELAY_MAX;
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const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
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RW_MGR_MEM_DQ_PER_READ_DQS;
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u32 stop;
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int i, d;
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for (d = 0; d <= dqs_max - start_dqs; d++) {
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if (write) { /* WRITE-ONLY */
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scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
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d + start_dqs);
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} else { /* READ-ONLY */
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scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
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if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
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uint32_t delay = d + start_dqs_en;
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if (delay > IO_DQS_EN_DELAY_MAX)
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delay = IO_DQS_EN_DELAY_MAX;
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scc_mgr_set_dqs_en_delay(read_group, delay);
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}
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scc_mgr_load_dqs(read_group);
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}
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writel(0, &sdr_scc_mgr->update);
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/*
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* Stop searching when the read test doesn't pass AND when
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* we've seen a passing read on every bit.
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*/
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if (write) { /* WRITE-ONLY */
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stop = !rw_mgr_mem_calibrate_write_test(rank_bgn,
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write_group,
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0, PASS_ONE_BIT,
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bit_chk, 0);
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} else if (use_read_test) { /* READ-ONLY */
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stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
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read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
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bit_chk, 0, 0);
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} else { /* READ-ONLY */
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rw_mgr_mem_calibrate_write_test(rank_bgn,
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write_group,
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0, PASS_ONE_BIT,
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bit_chk, 0);
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*bit_chk = *bit_chk >> (per_dqs *
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(read_group - (write_group *
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RW_MGR_MEM_IF_READ_DQS_WIDTH /
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RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
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stop = (*bit_chk == 0);
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}
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*sticky_bit_chk = *sticky_bit_chk | *bit_chk;
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stop = stop && (*sticky_bit_chk == correct_mask);
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debug_cond(DLEVEL == 2,
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"%s:%d center(right): dtap=%u => %u == %u && %u", __func__, __LINE__, d,
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*sticky_bit_chk, correct_mask, stop);
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if (stop == 1) {
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if (write && (d == 0)) { /* WRITE-ONLY */
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for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
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/*
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* d = 0 failed, but it passed when
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* testing the left edge, so it must be
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* marginal, set it to -1
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*/
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if (right_edge[i] == delay_max + 1 &&
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left_edge[i] != delay_max + 1)
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right_edge[i] = -1;
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}
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}
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break;
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}
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/* stop != 1 */
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for (i = 0; i < per_dqs; i++) {
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if (*bit_chk & 1) {
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/*
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* Remember a passing test as
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* the right_edge.
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*/
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right_edge[i] = d;
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} else {
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if (d != 0) {
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/*
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* If a right edge has not
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* been seen yet, then a future
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* passing test will mark this
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* edge as the left edge.
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*/
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if (right_edge[i] == delay_max + 1)
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left_edge[i] = -(d + 1);
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} else {
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/*
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* d = 0 failed, but it passed
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* when testing the left edge,
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* so it must be marginal, set
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* it to -1
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*/
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if (right_edge[i] == delay_max + 1 &&
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left_edge[i] != delay_max + 1)
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right_edge[i] = -1;
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/*
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* If a right edge has not been
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* seen yet, then a future
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* passing test will mark this
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* edge as the left edge.
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*/
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else if (right_edge[i] == delay_max + 1)
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left_edge[i] = -(d + 1);
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}
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}
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debug_cond(DLEVEL == 2, "%s:%d center[r,d=%u]: ",
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__func__, __LINE__, d);
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debug_cond(DLEVEL == 2,
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"bit_chk_test=%i left_edge[%u]: %d ",
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*bit_chk & 1, i, left_edge[i]);
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debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
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right_edge[i]);
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*bit_chk = *bit_chk >> 1;
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}
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}
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/* Check that all bits have a window */
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for (i = 0; i < per_dqs; i++) {
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debug_cond(DLEVEL == 2,
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"%s:%d write_center: left_edge[%u]: %d right_edge[%u]: %d",
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__func__, __LINE__, i, left_edge[i],
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i, right_edge[i]);
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if ((left_edge[i] == dqs_max + 1) ||
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(right_edge[i] == dqs_max + 1))
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return i + 1; /* FIXME: If we fail, retval > 0 */
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}
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return 0;
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}
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/* per-bit deskew DQ and center */
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static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
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uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
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@ -1803,6 +1963,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
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uint32_t stop;
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uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
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uint32_t addr;
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int ret;
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debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
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@ -1909,132 +2070,38 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
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}
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/* Search for the right edge of the window for each bit */
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for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
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scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
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if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
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uint32_t delay = d + start_dqs_en;
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if (delay > IO_DQS_EN_DELAY_MAX)
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delay = IO_DQS_EN_DELAY_MAX;
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scc_mgr_set_dqs_en_delay(read_group, delay);
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}
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scc_mgr_load_dqs(read_group);
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ret = search_right_edge(0, rank_bgn, write_group, read_group,
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start_dqs, start_dqs_en,
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&bit_chk, &sticky_bit_chk,
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left_edge, right_edge, use_read_test);
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if (ret) {
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/*
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* Restore delay chain settings before letting the loop
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* in rw_mgr_mem_calibrate_vfifo to retry different
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* dqs/ck relationships.
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*/
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scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
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if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
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scc_mgr_set_dqs_en_delay(read_group, start_dqs_en);
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scc_mgr_load_dqs(read_group);
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writel(0, &sdr_scc_mgr->update);
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/*
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* Stop searching when the read test doesn't pass AND when
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* we've seen a passing read on every bit.
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*/
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debug_cond(DLEVEL == 1,
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"%s:%d vfifo_center: failed to find edge [%u]: %d %d",
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__func__, __LINE__, i, left_edge[i], right_edge[i]);
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if (use_read_test) {
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stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
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read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
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&bit_chk, 0, 0);
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set_failing_group_stage(read_group *
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RW_MGR_MEM_DQ_PER_READ_DQS + i,
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CAL_STAGE_VFIFO,
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CAL_SUBSTAGE_VFIFO_CENTER);
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} else {
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rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
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0, PASS_ONE_BIT,
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&bit_chk, 0);
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bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
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(read_group - (write_group *
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RW_MGR_MEM_IF_READ_DQS_WIDTH /
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RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
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stop = (bit_chk == 0);
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}
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sticky_bit_chk = sticky_bit_chk | bit_chk;
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stop = stop && (sticky_bit_chk == param->read_correct_mask);
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debug_cond(DLEVEL == 2, "%s:%d vfifo_center(right): dtap=%u => %u == \
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%u && %u", __func__, __LINE__, d,
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sticky_bit_chk, param->read_correct_mask, stop);
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if (stop == 1) {
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break;
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} else {
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for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
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if (bit_chk & 1) {
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/* Remember a passing test as
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the right_edge */
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right_edge[i] = d;
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} else {
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if (d != 0) {
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/* If a right edge has not been
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seen yet, then a future passing
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test will mark this edge as the
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left edge */
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if (right_edge[i] ==
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IO_IO_IN_DELAY_MAX + 1) {
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left_edge[i] = -(d + 1);
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}
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} else {
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/* d = 0 failed, but it passed
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when testing the left edge,
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so it must be marginal,
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set it to -1 */
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if (right_edge[i] ==
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IO_IO_IN_DELAY_MAX + 1 &&
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left_edge[i] !=
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IO_IO_IN_DELAY_MAX
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+ 1) {
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right_edge[i] = -1;
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}
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/* If a right edge has not been
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seen yet, then a future passing
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test will mark this edge as the
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left edge */
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else if (right_edge[i] ==
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IO_IO_IN_DELAY_MAX +
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1) {
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left_edge[i] = -(d + 1);
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}
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}
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}
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debug_cond(DLEVEL == 2, "%s:%d vfifo_center[r,\
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d=%u]: ", __func__, __LINE__, d);
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debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d ",
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(int)(bit_chk & 1), i, left_edge[i]);
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debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
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right_edge[i]);
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bit_chk = bit_chk >> 1;
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}
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}
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}
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/* Check that all bits have a window */
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for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
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debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
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%d right_edge[%u]: %d", __func__, __LINE__,
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i, left_edge[i], i, right_edge[i]);
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if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) || (right_edge[i]
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== IO_IO_IN_DELAY_MAX + 1)) {
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/*
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* Restore delay chain settings before letting the loop
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* in rw_mgr_mem_calibrate_vfifo to retry different
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* dqs/ck relationships.
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*/
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scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
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if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
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scc_mgr_set_dqs_en_delay(read_group,
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start_dqs_en);
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}
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scc_mgr_load_dqs(read_group);
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writel(0, &sdr_scc_mgr->update);
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debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
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find edge [%u]: %d %d", __func__, __LINE__,
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i, left_edge[i], right_edge[i]);
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if (use_read_test) {
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set_failing_group_stage(read_group *
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RW_MGR_MEM_DQ_PER_READ_DQS + i,
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CAL_STAGE_VFIFO,
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CAL_SUBSTAGE_VFIFO_CENTER);
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} else {
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set_failing_group_stage(read_group *
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RW_MGR_MEM_DQ_PER_READ_DQS + i,
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CAL_STAGE_VFIFO_AFTER_WRITES,
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CAL_SUBSTAGE_VFIFO_CENTER);
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}
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return 0;
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set_failing_group_stage(read_group *
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RW_MGR_MEM_DQ_PER_READ_DQS + i,
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CAL_STAGE_VFIFO_AFTER_WRITES,
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CAL_SUBSTAGE_VFIFO_CENTER);
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}
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return 0;
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}
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/* Find middle of window for each DQ bit */
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@ -2729,6 +2796,8 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
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uint32_t temp_dq_out1_delay;
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uint32_t addr;
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int ret;
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debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
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dm_margin = 0;
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@ -2833,107 +2902,14 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
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}
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/* Search for the right edge of the window for each bit */
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for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
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scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
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d + start_dqs);
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writel(0, &sdr_scc_mgr->update);
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/*
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* Stop searching when the read test doesn't pass AND when
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* we've seen a passing read on every bit.
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*/
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stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
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0, PASS_ONE_BIT, &bit_chk, 0);
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sticky_bit_chk = sticky_bit_chk | bit_chk;
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stop = stop && (sticky_bit_chk == param->write_correct_mask);
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debug_cond(DLEVEL == 2, "write_center (right): dtap=%u => %u == \
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%u && %u\n", d, sticky_bit_chk,
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param->write_correct_mask, stop);
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if (stop == 1) {
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if (d == 0) {
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for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS;
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i++) {
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/* d = 0 failed, but it passed when
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testing the left edge, so it must be
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marginal, set it to -1 */
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if (right_edge[i] ==
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IO_IO_OUT1_DELAY_MAX + 1 &&
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left_edge[i] !=
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IO_IO_OUT1_DELAY_MAX + 1) {
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right_edge[i] = -1;
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}
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}
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}
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break;
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} else {
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for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
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if (bit_chk & 1) {
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/*
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* Remember a passing test as
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* the right_edge.
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*/
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right_edge[i] = d;
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} else {
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if (d != 0) {
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/*
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* If a right edge has not
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* been seen yet, then a future
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* passing test will mark this
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* edge as the left edge.
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*/
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if (right_edge[i] ==
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IO_IO_OUT1_DELAY_MAX + 1)
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left_edge[i] = -(d + 1);
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} else {
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/*
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* d = 0 failed, but it passed
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* when testing the left edge,
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* so it must be marginal, set
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* it to -1.
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*/
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if (right_edge[i] ==
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IO_IO_OUT1_DELAY_MAX + 1 &&
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left_edge[i] !=
|
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IO_IO_OUT1_DELAY_MAX + 1)
|
||||
right_edge[i] = -1;
|
||||
/*
|
||||
* If a right edge has not been
|
||||
* seen yet, then a future
|
||||
* passing test will mark this
|
||||
* edge as the left edge.
|
||||
*/
|
||||
else if (right_edge[i] ==
|
||||
IO_IO_OUT1_DELAY_MAX +
|
||||
1)
|
||||
left_edge[i] = -(d + 1);
|
||||
}
|
||||
}
|
||||
debug_cond(DLEVEL == 2, "write_center[r,d=%d):", d);
|
||||
debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
|
||||
(int)(bit_chk & 1), i, left_edge[i]);
|
||||
debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
|
||||
right_edge[i]);
|
||||
bit_chk = bit_chk >> 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Check that all bits have a window */
|
||||
for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
|
||||
debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
|
||||
%d right_edge[%u]: %d", __func__, __LINE__,
|
||||
i, left_edge[i], i, right_edge[i]);
|
||||
if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) ||
|
||||
(right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1)) {
|
||||
set_failing_group_stage(test_bgn + i,
|
||||
CAL_STAGE_WRITES,
|
||||
CAL_SUBSTAGE_WRITES_CENTER);
|
||||
return 0;
|
||||
}
|
||||
ret = search_right_edge(1, rank_bgn, write_group, 0,
|
||||
start_dqs, 0,
|
||||
&bit_chk, &sticky_bit_chk,
|
||||
left_edge, right_edge, 0);
|
||||
if (ret) {
|
||||
set_failing_group_stage(test_bgn + ret - 1, CAL_STAGE_WRITES,
|
||||
CAL_SUBSTAGE_WRITES_CENTER);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Find middle of window for each DQ bit */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user