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clock:aspeed: Sync with Linux kernel clock header define

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v2: modify title description aspeed:clock -> clock:aspeed

Use kernel include/dt-bindings/clock/aspeed-clock.h define
for clock driver.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
This commit is contained in:
Ryan Chen
2020-08-31 14:03:04 +08:00
committed by Tom Rini
parent 15b87feb2b
commit c39c9a94cb
3 changed files with 68 additions and 58 deletions
Download Patch File Download Diff File Expand all files Collapse all files

38
drivers/clk/aspeed/clk_ast2500.c
View File

@@ -122,8 +122,7 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
ulong rate;
switch (clk->id) {
case PLL_HPLL:
case ARMCLK:
case ASPEED_CLK_HPLL:
/*
* This ignores dynamic/static slowdown of ARMCLK and may
* be inaccurate.
@@ -131,11 +130,11 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
rate = ast2500_get_hpll_rate(clkin,
readl(&priv->scu->h_pll_param));
break;
case MCLK_DDR:
case ASPEED_CLK_MPLL:
rate = ast2500_get_mpll_rate(clkin,
readl(&priv->scu->m_pll_param));
break;
case BCLK_PCLK:
case ASPEED_CLK_APB:
{
ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
& SCU_PCLK_DIV_MASK)
@@ -146,7 +145,7 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
rate = rate / apb_div;
}
break;
case BCLK_SDCLK:
case ASPEED_CLK_SDIO:
{
ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
& SCU_SDCLK_DIV_MASK)
@@ -157,19 +156,19 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
rate = rate / apb_div;
}
break;
case PCLK_UART1:
case ASPEED_CLK_GATE_UART1CLK:
rate = ast2500_get_uart_clk_rate(priv->scu, 1);
break;
case PCLK_UART2:
case ASPEED_CLK_GATE_UART2CLK:
rate = ast2500_get_uart_clk_rate(priv->scu, 2);
break;
case PCLK_UART3:
case ASPEED_CLK_GATE_UART3CLK:
rate = ast2500_get_uart_clk_rate(priv->scu, 3);
break;
case PCLK_UART4:
case ASPEED_CLK_GATE_UART4CLK:
rate = ast2500_get_uart_clk_rate(priv->scu, 4);
break;
case PCLK_UART5:
case ASPEED_CLK_GATE_UART5CLK:
rate = ast2500_get_uart_clk_rate(priv->scu, 5);
break;
default:
@@ -431,11 +430,10 @@ static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate)
ulong new_rate;
switch (clk->id) {
case PLL_MPLL:
case MCLK_DDR:
case ASPEED_CLK_MPLL:
new_rate = ast2500_configure_ddr(priv->scu, rate);
break;
case PLL_D2PLL:
case ASPEED_CLK_D2PLL:
new_rate = ast2500_configure_d2pll(priv->scu, rate);
break;
default:
@@ -450,7 +448,7 @@ static int ast2500_clk_enable(struct clk *clk)
struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
switch (clk->id) {
case BCLK_SDCLK:
case ASPEED_CLK_SDIO:
if (readl(&priv->scu->clk_stop_ctrl1) & SCU_CLKSTOP_SDCLK) {
ast_scu_unlock(priv->scu);
@@ -471,13 +469,13 @@ static int ast2500_clk_enable(struct clk *clk)
* configured based on whether RGMII or RMII mode has been selected
* through hardware strapping.
*/
case PCLK_MAC1:
case ASPEED_CLK_GATE_MAC1CLK:
ast2500_configure_mac(priv->scu, 1);
break;
case PCLK_MAC2:
case ASPEED_CLK_GATE_MAC2CLK:
ast2500_configure_mac(priv->scu, 2);
break;
case PLL_D2PLL:
case ASPEED_CLK_D2PLL:
ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE);
break;
default:
@@ -497,9 +495,9 @@ static int ast2500_clk_ofdata_to_platdata(struct udevice *dev)
{
struct ast2500_clk_priv *priv = dev_get_priv(dev);
priv->scu = dev_read_addr_ptr(dev);
if (!priv->scu)
return -EINVAL;
priv->scu = devfdt_get_addr_ptr(dev);
if (IS_ERR(priv->scu))
return PTR_ERR(priv->scu);
return 0;
}