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omap5: Expand CONFIG_SPL_MAX_SIZE and comment upon SRAM_SCRATCH_SPACE_ADDR

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After examining both TRMs and doing some experimentation, we can rely on
using the start of the download area for CONFIG_SPL_TEXT_BASE and then
move SRAM_SCRATCH_SPACE_ADDR up, just like am335x.  This is required for
peripheral boot modes such as UART.

Signed-off-by: Tom Rini <trini@ti.com>
This commit is contained in:
Tom Rini 2013-08-20 08:53:45 -04:00
parent a7142dd096
commit c3799fceda
2 changed files with 12 additions and 3 deletions
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11
arch/arm/include/asm/arch-omap5/omap.h
View File

@ -153,6 +153,15 @@ struct s32ktimer {
#define EFUSE_4 0x45145100
#endif /* __ASSEMBLY__ */
/*
* In all cases, the TRM defines the RAM Memory Map for the processor
* and indicates the area for the downloaded image. We use all of that
* space for download and once up and running may use other parts of the
* map for our needs. We set a scratch space that is at the end of the
* OMAP5 download area, but within the DRA7xx download area (as it is
* much larger) and do not, at this time, make use of the additional
* space.
*/
#ifdef CONFIG_DRA7XX
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */
@ -160,7 +169,7 @@ struct s32ktimer {
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */
#endif
#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
#define SRAM_SCRATCH_SPACE_ADDR 0x4031E000
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4031F000

4
include/configs/omap5_common.h
View File

@ -128,8 +128,8 @@
/* Defines for SPL */
#define CONFIG_SPL_TEXT_BASE 0x40300350
#define CONFIG_SPL_MAX_SIZE 0x19000 /* 100K */
#define CONFIG_SPL_TEXT_BASE 0x40300000
#define CONFIG_SPL_MAX_SIZE (0x4031E000 - CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_DISPLAY_PRINT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"