Add Ethernet 1000BASE-X support for PPC4xx
This patch adds a new switch: "CONFIG_PHY_DYNAMIC_ANEG". When this symbol is defined, the PHY will advertise it's capabilities for autonegotiation based on the capabilities shown in the PHY's status registers, including 1000BASE-X. When "CONFIG_PHY_DYNAMIC_ANEG" is not defined, the PHY will advertise hard-coded capabilities, as before. Signed-off-by: Larry Johnson <lrj@acm.org>
This commit is contained in:
Larry Johnson
Stefan Roese
parent
9e2c347151
commit
c348578bf6
@ -27,19 +27,6 @@
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| Author: Mark Wisner
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| Change Activity-
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| Date Description of Change BY
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| --------- --------------------- ---
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| 05-May-99 Created MKW
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| 01-Jul-99 Changed clock setting of sta_reg from 66Mhz to 50Mhz to
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| better match OPB speed. Also modified delay times. JWB
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| 29-Jul-99 Added Full duplex support MKW
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| 24-Aug-99 Removed printf from dp83843_duplex() JWB
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| 19-Jul-00 Ported to esd cpci405 sr
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| 23-Dec-03 Ported from miiphy.c to 440GX Travis Sawyer TBS
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| <travis.sawyer@sandburst.com>
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+-----------------------------------------------------------------------------*/
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#include <common.h>
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@ -61,7 +48,6 @@ void miiphy_dump (char *devname, unsigned char addr)
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unsigned long i;
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unsigned short data;
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for (i = 0; i < 0x1A; i++) {
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if (miiphy_read (devname, addr, i, &data)) {
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printf ("read error for reg %lx\n", i);
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@ -76,15 +62,86 @@ void miiphy_dump (char *devname, unsigned char addr)
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} /* end for loop */
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} /* end dump */
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/***********************************************************/
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/* (Re)start autonegotiation */
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/***********************************************************/
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int phy_setup_aneg (char *devname, unsigned char addr)
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{
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unsigned short ctl, adv;
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u16 bmcr;
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#if defined(CONFIG_PHY_DYNAMIC_ANEG)
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/*
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* Set up advertisement based on capablilities reported by the PHY.
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* This should work for both copper and fiber.
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*/
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u16 bmsr;
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#if defined(CONFIG_PHY_GIGE)
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u16 exsr = 0x0000;
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#endif
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miiphy_read (devname, addr, PHY_BMSR, &bmsr);
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#if defined(CONFIG_PHY_GIGE)
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if (bmsr & PHY_BMSR_EXT_STAT)
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miiphy_read (devname, addr, PHY_EXSR, &exsr);
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if (exsr & (PHY_EXSR_1000XF | PHY_EXSR_1000XH)) {
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/* 1000BASE-X */
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u16 anar = 0x0000;
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if (exsr & PHY_EXSR_1000XF)
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anar |= PHY_X_ANLPAR_FD;
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if (exsr & PHY_EXSR_1000XH)
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anar |= PHY_X_ANLPAR_HD;
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miiphy_write (devname, addr, PHY_ANAR, anar);
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} else
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#endif
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{
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u16 anar, btcr;
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miiphy_read (devname, addr, PHY_ANAR, &anar);
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anar &= ~(0x5000 | PHY_ANLPAR_T4 | PHY_ANLPAR_TXFD |
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PHY_ANLPAR_TX | PHY_ANLPAR_10FD | PHY_ANLPAR_10);
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miiphy_read (devname, addr, PHY_1000BTCR, &btcr);
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btcr &= ~(0x00FF | PHY_1000BTCR_1000FD | PHY_1000BTCR_1000HD);
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if (bmsr & PHY_BMSR_100T4)
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anar |= PHY_ANLPAR_T4;
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if (bmsr & PHY_BMSR_100TXF)
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anar |= PHY_ANLPAR_TXFD;
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if (bmsr & PHY_BMSR_100TXH)
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anar |= PHY_ANLPAR_TX;
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if (bmsr & PHY_BMSR_10TF)
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anar |= PHY_ANLPAR_10FD;
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if (bmsr & PHY_BMSR_10TH)
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anar |= PHY_ANLPAR_10;
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miiphy_write (devname, addr, PHY_ANAR, anar);
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#if defined(CONFIG_PHY_GIGE)
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if (exsr & PHY_EXSR_1000TF)
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btcr |= PHY_1000BTCR_1000FD;
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if (exsr & PHY_EXSR_1000TH)
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btcr |= PHY_1000BTCR_1000HD;
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miiphy_write (devname, addr, PHY_1000BTCR, btcr);
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#endif
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}
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#else /* defined(CONFIG_PHY_DYNAMIC_ANEG) */
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/*
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* Set up standard advertisement
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*/
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u16 adv;
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/* Setup standard advertise */
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miiphy_read (devname, addr, PHY_ANAR, &adv);
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adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 |
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PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
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@ -95,15 +152,16 @@ int phy_setup_aneg (char *devname, unsigned char addr)
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adv |= (0x0300);
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miiphy_write (devname, addr, PHY_1000BTCR, adv);
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#endif /* defined(CONFIG_PHY_DYNAMIC_ANEG) */
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/* Start/Restart aneg */
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miiphy_read (devname, addr, PHY_BMCR, &ctl);
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ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
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miiphy_write (devname, addr, PHY_BMCR, ctl);
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miiphy_read (devname, addr, PHY_BMCR, &bmcr);
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bmcr |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
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miiphy_write (devname, addr, PHY_BMCR, bmcr);
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return 0;
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}
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/***********************************************************/
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/* read a phy reg and return the value with a rc */
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/***********************************************************/
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@ -116,19 +174,23 @@ unsigned int miiphy_getemac_offset (void)
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/* Need to find out which mdi port we're using */
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zmii = in_be32((void *)ZMII_FER);
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if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0))) {
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if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0)))
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/* using port 0 */
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eoffset = 0;
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} else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1))) {
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else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1)))
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/* using port 1 */
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eoffset = 0x100;
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} else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2))) {
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else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2)))
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/* using port 2 */
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eoffset = 0x400;
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} else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3))) {
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else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3)))
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/* using port 3 */
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eoffset = 0x600;
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} else {
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else {
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/* None of the mdi ports are enabled! */
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/* enable port 0 */
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zmii |= ZMII_FER_MDI << ZMII_FER_V (0);
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@ -156,21 +218,20 @@ unsigned int miiphy_getemac_offset (void)
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#endif
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}
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int emac4xx_miiphy_read (char *devname, unsigned char addr,
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unsigned char reg, unsigned short *value)
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int emac4xx_miiphy_read (char *devname, unsigned char addr, unsigned char reg,
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unsigned short *value)
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{
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unsigned long sta_reg; /* STA scratch area */
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unsigned long i;
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unsigned long emac_reg;
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emac_reg = miiphy_getemac_offset ();
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/* see if it is ready for 1000 nsec */
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i = 0;
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/* see if it is ready for sec */
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while ((in_be32((void *)EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
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while ((in_be32((void *)EMAC_STACR + emac_reg) & EMAC_STACR_OC) ==
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EMAC_STACR_OC_MASK) {
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udelay (7);
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if (i > 5) {
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#ifdef ET_DEBUG
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@ -187,10 +248,10 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr,
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#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_405EX)
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#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */
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sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_READ;
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#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */
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sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_READ;
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#else
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sta_reg |= EMAC_STACR_READ;
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sta_reg |= EMAC_STACR_READ;
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#endif
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#else
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sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
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@ -211,37 +272,34 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr,
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sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
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#ifdef ET_DEBUG
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printf ("a21: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
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printf ("a21: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
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#endif
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i = 0;
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while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
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udelay (7);
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if (i > 5) {
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if (i > 5)
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return -1;
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}
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i++;
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sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
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#ifdef ET_DEBUG
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printf ("a22: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
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#endif
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}
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if ((sta_reg & EMAC_STACR_PHYE) != 0) {
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if ((sta_reg & EMAC_STACR_PHYE) != 0)
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return -1;
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}
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*value = *(short *) (&sta_reg);
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*value = *(short *)(&sta_reg);
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return 0;
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} /* phy_read */
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/***********************************************************/
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/* write a phy reg and return the value with a rc */
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/***********************************************************/
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int emac4xx_miiphy_write (char *devname, unsigned char addr,
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unsigned char reg, unsigned short value)
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int emac4xx_miiphy_write (char *devname, unsigned char addr, unsigned char reg,
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unsigned short value)
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{
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unsigned long sta_reg; /* STA scratch area */
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unsigned long i;
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@ -251,9 +309,11 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr,
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/* see if it is ready for 1000 nsec */
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i = 0;
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while ((in_be32((void *)EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
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while ((in_be32((void *)EMAC_STACR + emac_reg) & EMAC_STACR_OC) ==
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EMAC_STACR_OC_MASK) {
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if (i > 5)
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return -1;
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udelay (7);
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i++;
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}
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@ -263,10 +323,10 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr,
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#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_405EX)
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#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */
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sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_WRITE;
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#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */
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sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_WRITE;
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#else
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sta_reg |= EMAC_STACR_WRITE;
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sta_reg |= EMAC_STACR_WRITE;
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#endif
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#else
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sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
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@ -278,8 +338,8 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr,
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!defined(CONFIG_405EX)
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sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */
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#endif
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sta_reg = sta_reg | ((unsigned long) addr << 5);/* Phy address */
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sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */
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sta_reg = sta_reg | ((unsigned long)addr << 5); /* Phy address */
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sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */
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memcpy (&sta_reg, &value, 2); /* put in data */
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out_be32((void *)EMAC_STACR + emac_reg, sta_reg);
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@ -288,12 +348,13 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr,
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i = 0;
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sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
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#ifdef ET_DEBUG
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printf ("a31: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
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printf ("a31: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
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#endif
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while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
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udelay (7);
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if (i > 5)
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return -1;
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i++;
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sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
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#ifdef ET_DEBUG
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@ -303,6 +364,7 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr,
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if ((sta_reg & EMAC_STACR_PHYE) != 0)
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return -1;
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return 0;
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} /* phy_write */
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} /* phy_write */
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