stm32mp1: migrate USBOTG device to driver model
Use the DWC2 device driver with DM_USB_GADGET support and cleanup the USB support in STM32MP1 board. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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995d228bce
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c31000c534
@ -11,6 +11,7 @@
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aliases {
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i2c3 = &i2c4;
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mmc0 = &sdmmc1;
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usb0 = &usbotg_hs;
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};
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config {
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u-boot,boot-led = "heartbeat";
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@ -190,7 +191,7 @@
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};
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&usbotg_hs {
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usb1600;
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force-b-session-valid;
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hnp-srp-disable;
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};
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@ -249,11 +249,25 @@
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status = "okay";
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};
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&usbphyc {
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vdd3v3-supply = <&vdd_usb>;
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&usbotg_hs {
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dr_mode = "peripheral";
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phys = <&usbphyc_port1 0>;
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phy-names = "usb2-phy";
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status = "okay";
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};
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&usbphyc {
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status = "okay";
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};
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&usbphyc_port0 {
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phy-supply = <&vdd_usb>;
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};
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&usbphyc_port1 {
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phy-supply = <&vdd_usb>;
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};
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&vrefbuf {
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2500000>;
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@ -12,6 +12,7 @@
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i2c4 = &i2c5;
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pinctrl2 = &stmfx_pinctrl;
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spi0 = &qspi;
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usb0 = &usbotg_hs;
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};
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};
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@ -825,7 +825,7 @@
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};
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usbotg_hs: usb-otg@49000000 {
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compatible = "snps,dwc2";
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compatible = "st,stm32mp1-hsotg", "snps,dwc2";
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reg = <0x49000000 0x10000>;
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clocks = <&rcc USBO_K>;
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clock-names = "otg";
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@ -7,18 +7,17 @@
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#include <config.h>
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#include <clk.h>
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#include <dm.h>
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#include <g_dnl.h>
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#include <generic-phy.h>
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#include <led.h>
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#include <misc.h>
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#include <phy.h>
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#include <reset.h>
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#include <syscon.h>
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#include <usb.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/stm32.h>
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#include <power/regulator.h>
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#include <usb/dwc2_udc.h>
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/* SYSCFG registers */
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#define SYSCFG_BOOTR 0x00
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@ -58,11 +57,6 @@
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*/
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DECLARE_GLOBAL_DATA_PTR;
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#define STM32MP_GUSBCFG 0x40002407
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#define STM32MP_GGPIO 0x38
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#define STM32MP_GGPIO_VBUS_SENSING BIT(21)
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#define USB_WARNING_LOW_THRESHOLD_UV 660000
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#define USB_START_LOW_THRESHOLD_UV 1230000
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#define USB_START_HIGH_THRESHOLD_UV 2100000
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@ -155,149 +149,22 @@ static void board_key_check(void)
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#endif
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}
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static struct dwc2_plat_otg_data stm32mp_otg_data = {
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.usb_gusbcfg = STM32MP_GUSBCFG,
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};
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#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
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static struct reset_ctl usbotg_reset;
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int board_usb_init(int index, enum usb_init_type init)
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int g_dnl_board_usb_cable_connected(void)
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{
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struct fdtdec_phandle_args args;
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struct udevice *dev;
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const void *blob = gd->fdt_blob;
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struct clk clk;
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struct phy phy;
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int node;
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int phy_provider;
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struct udevice *dwc2_udc_otg;
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int ret;
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/* find the usb otg node */
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node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2");
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if (node < 0) {
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debug("Not found usb_otg device\n");
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return -ENODEV;
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}
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if (!fdtdec_get_is_enabled(blob, node)) {
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debug("stm32 usbotg is disabled in the device tree\n");
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return -ENODEV;
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}
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/* Enable clock */
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ret = fdtdec_parse_phandle_with_args(blob, node, "clocks",
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"#clock-cells", 0, 0, &args);
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if (ret) {
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debug("usbotg has no clocks defined in the device tree\n");
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return ret;
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}
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ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &dev);
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if (ret)
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return ret;
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if (args.args_count != 1) {
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debug("Can't find clock ID in the device tree\n");
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return -ENODATA;
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}
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clk.dev = dev;
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clk.id = args.args[0];
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ret = clk_enable(&clk);
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if (ret) {
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debug("Failed to enable usbotg clock\n");
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return ret;
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}
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/* Reset */
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ret = fdtdec_parse_phandle_with_args(blob, node, "resets",
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"#reset-cells", 0, 0, &args);
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if (ret) {
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debug("usbotg has no resets defined in the device tree\n");
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goto clk_err;
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}
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ret = uclass_get_device_by_of_offset(UCLASS_RESET, args.node, &dev);
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if (ret || args.args_count != 1)
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goto clk_err;
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usbotg_reset.dev = dev;
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usbotg_reset.id = args.args[0];
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reset_assert(&usbotg_reset);
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udelay(2);
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reset_deassert(&usbotg_reset);
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/* Get USB PHY */
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ret = fdtdec_parse_phandle_with_args(blob, node, "phys",
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"#phy-cells", 0, 0, &args);
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if (!ret) {
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phy_provider = fdt_parent_offset(blob, args.node);
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ret = uclass_get_device_by_of_offset(UCLASS_PHY,
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phy_provider, &dev);
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if (ret)
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goto clk_err;
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phy.dev = dev;
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phy.id = fdtdec_get_uint(blob, args.node, "reg", -1);
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ret = generic_phy_power_on(&phy);
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if (ret) {
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debug("unable to power on the phy\n");
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goto clk_err;
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}
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ret = generic_phy_init(&phy);
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if (ret) {
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debug("failed to init usb phy\n");
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goto phy_power_err;
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}
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}
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/* Parse and store data needed for gadget */
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stm32mp_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
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if (stm32mp_otg_data.regs_otg == FDT_ADDR_T_NONE) {
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debug("usbotg: can't get base address\n");
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ret = -ENODATA;
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goto phy_init_err;
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}
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stm32mp_otg_data.rx_fifo_sz = fdtdec_get_int(blob, node,
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"g-rx-fifo-size", 0);
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stm32mp_otg_data.np_tx_fifo_sz = fdtdec_get_int(blob, node,
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"g-np-tx-fifo-size", 0);
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stm32mp_otg_data.tx_fifo_sz = fdtdec_get_int(blob, node,
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"g-tx-fifo-size", 0);
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/* Enable voltage level detector */
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if (!(fdtdec_parse_phandle_with_args(blob, node, "usb33d-supply",
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NULL, 0, 0, &args))) {
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if (!uclass_get_device_by_of_offset(UCLASS_REGULATOR,
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args.node, &dev)) {
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ret = regulator_set_enable(dev, true);
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if (ret) {
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debug("Failed to enable usb33d\n");
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goto phy_init_err;
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}
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}
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}
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/* Enable vbus sensing */
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setbits_le32(stm32mp_otg_data.regs_otg + STM32MP_GGPIO,
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STM32MP_GGPIO_VBUS_SENSING);
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return dwc2_udc_probe(&stm32mp_otg_data);
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phy_init_err:
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generic_phy_exit(&phy);
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phy_power_err:
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generic_phy_power_off(&phy);
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clk_err:
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clk_disable(&clk);
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return ret;
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ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC,
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DM_GET_DRIVER(dwc2_udc_otg),
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&dwc2_udc_otg);
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if (!ret)
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debug("dwc2_udc_otg init failed\n");
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return dwc2_udc_B_session_valid(dwc2_udc_otg);
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}
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#endif /* CONFIG_USB_GADGET */
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static int get_led(struct udevice **dev, char *led_string)
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{
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@ -438,16 +305,6 @@ static int board_check_usb_power(void)
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return 0;
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}
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int board_usb_cleanup(int index, enum usb_init_type init)
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{
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/* Reset usbotg */
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reset_assert(&usbotg_reset);
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udelay(2);
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reset_deassert(&usbotg_reset);
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return 0;
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}
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static void sysconf_init(void)
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{
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#ifndef CONFIG_STM32MP1_TRUSTED
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@ -69,6 +69,7 @@ CONFIG_SERIAL_RX_BUFFER=y
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CONFIG_STM32_SERIAL=y
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CONFIG_USB=y
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CONFIG_DM_USB=y
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CONFIG_DM_USB_GADGET=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_GENERIC=y
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CONFIG_USB_GADGET=y
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CONFIG_STM32_SERIAL=y
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CONFIG_USB=y
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CONFIG_DM_USB=y
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CONFIG_DM_USB_GADGET=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_GENERIC=y
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CONFIG_USB_GADGET=y
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