board/spear/common: move code to arch/arm/cpu/arm926ejs/spear/
The code in board/spear/common/ is not board-specific but SoC-specific. Therefore, boards from other vendors than "spear" may want to re-use this code, which is currently difficult with the code being placed in board/spear/common/. Since this code really is SoC-specific, this commit moves it to arch/arm/cpu/arm926ejs/spear/, with the rest of the SPEAr related code. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
This commit is contained in:
Thomas Petazzoni
committed by
Tom Rini
Tom Rini
parent
fc6adebbc1
commit
c25c4fd010
@@ -16,6 +16,8 @@ obj-$(CONFIG_DDR_MT47H64M16) += spr600_mt47h64m16_3_333_cl5_psync.o
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obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o
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obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_37e_166_cl4_sync.o
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obj-$(CONFIG_DDR_MT47H128M8) += spr600_mt47h128m8_3_266_cl5_async.o
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else
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obj-y += spr_misc.o spr_lowlevel_init.o
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endif
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extra-$(CONFIG_SPL_BUILD) := start.o
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174
arch/arm/cpu/arm926ejs/spear/spr_lowlevel_init.S
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174
arch/arm/cpu/arm926ejs/spear/spr_lowlevel_init.S
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@@ -0,0 +1,174 @@
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/*
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* (C) Copyright 2006
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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/*
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* platform specific initializations are already done in Xloader
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* Initializations already done include
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* DDR, PLLs, IP's clock enable and reset release etc
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*/
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.globl lowlevel_init
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lowlevel_init:
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mov pc, lr
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/* void setfreq(unsigned int device, unsigned int frequency) */
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.global setfreq
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setfreq:
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stmfd sp!,{r14}
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stmfd sp!,{r0-r12}
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mov r8,sp
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ldr sp,SRAM_STACK_V
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/* Saving the function arguements for later use */
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mov r4,r0
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mov r5,r1
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/* Putting DDR into self refresh */
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ldr r0,DDR_07_V
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ldr r1,[r0]
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ldr r2,DDR_ACTIVE_V
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bic r1, r1, r2
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str r1,[r0]
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ldr r0,DDR_57_V
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ldr r1,[r0]
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ldr r2,CYCLES_MASK_V
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bic r1, r1, r2
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ldr r2,REFRESH_CYCLES_V
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orr r1, r1, r2, lsl #16
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str r1,[r0]
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ldr r0,DDR_07_V
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ldr r1,[r0]
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ldr r2,SREFRESH_MASK_V
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orr r1, r1, r2
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str r1,[r0]
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/* flush pipeline */
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b flush
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.align 5
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flush:
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/* Delay to ensure self refresh mode */
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ldr r0,SREFRESH_DELAY_V
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delay:
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sub r0,r0,#1
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cmp r0,#0
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bne delay
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/* Putting system in slow mode */
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ldr r0,SCCTRL_V
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mov r1,#2
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str r1,[r0]
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/* Changing PLL(1/2) frequency */
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mov r0,r4
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mov r1,r5
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cmp r4,#0
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beq pll1_freq
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/* Change PLL2 (DDR frequency) */
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ldr r6,PLL2_FREQ_V
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ldr r7,PLL2_CNTL_V
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b pll2_freq
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pll1_freq:
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/* Change PLL1 (CPU frequency) */
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ldr r6,PLL1_FREQ_V
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ldr r7,PLL1_CNTL_V
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pll2_freq:
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mov r0,r6
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ldr r1,[r0]
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ldr r2,PLLFREQ_MASK_V
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bic r1,r1,r2
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mov r2,r5,lsr#1
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orr r1,r1,r2,lsl#24
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str r1,[r0]
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mov r0,r7
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ldr r1,P1C0A_V
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str r1,[r0]
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ldr r1,P1C0E_V
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str r1,[r0]
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ldr r1,P1C06_V
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str r1,[r0]
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ldr r1,P1C0E_V
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str r1,[r0]
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lock:
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ldr r1,[r0]
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and r1,r1,#1
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cmp r1,#0
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beq lock
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/* Putting system back to normal mode */
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ldr r0,SCCTRL_V
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mov r1,#4
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str r1,[r0]
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/* Putting DDR back to normal */
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ldr r0,DDR_07_V
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ldr r1,[R0]
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ldr r2,SREFRESH_MASK_V
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bic r1, r1, r2
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str r1,[r0]
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ldr r2,DDR_ACTIVE_V
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orr r1, r1, r2
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str r1,[r0]
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/* Delay to ensure self refresh mode */
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ldr r0,SREFRESH_DELAY_V
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1:
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sub r0,r0,#1
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cmp r0,#0
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bne 1b
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mov sp,r8
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/* Resuming back to code */
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ldmia sp!,{r0-r12}
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ldmia sp!,{pc}
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SCCTRL_V:
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.word 0xfca00000
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PLL1_FREQ_V:
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.word 0xfca8000C
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PLL1_CNTL_V:
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.word 0xfca80008
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PLL2_FREQ_V:
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.word 0xfca80018
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PLL2_CNTL_V:
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.word 0xfca80014
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PLLFREQ_MASK_V:
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.word 0xff000000
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P1C0A_V:
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.word 0x1C0A
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P1C0E_V:
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.word 0x1C0E
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P1C06_V:
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.word 0x1C06
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SREFRESH_DELAY_V:
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.word 0x9999
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SRAM_STACK_V:
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.word 0xD2800600
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DDR_07_V:
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.word 0xfc60001c
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DDR_ACTIVE_V:
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.word 0x01000000
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DDR_57_V:
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.word 0xfc6000e4
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CYCLES_MASK_V:
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.word 0xffff0000
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REFRESH_CYCLES_V:
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.word 0xf0f0
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SREFRESH_MASK_V:
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.word 0x00010000
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.global setfreq_sz
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setfreq_sz:
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.word setfreq_sz - setfreq
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249
arch/arm/cpu/arm926ejs/spear/spr_misc.c
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249
arch/arm/cpu/arm926ejs/spear/spr_misc.c
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@@ -0,0 +1,249 @@
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/*
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* (C) Copyright 2009
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <i2c.h>
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#include <net.h>
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#include <linux/mtd/st_smi.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/spr_emi.h>
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#include <asm/arch/spr_defs.h>
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#define CPU 0
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#define DDR 1
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#define SRAM_REL 0xD2801000
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_CMD_NET)
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static int i2c_read_mac(uchar *buffer);
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#endif
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int dram_init(void)
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{
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/* Store complete RAM size and return */
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gd->ram_size = get_ram_size(PHYS_SDRAM_1, PHYS_SDRAM_1_MAXSIZE);
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = gd->ram_size;
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return 0;
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}
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int board_early_init_f()
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{
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#if defined(CONFIG_ST_SMI)
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smi_init();
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#endif
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return 0;
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}
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int misc_init_r(void)
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{
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#if defined(CONFIG_CMD_NET)
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uchar mac_id[6];
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if (!eth_env_get_enetaddr("ethaddr", mac_id) && !i2c_read_mac(mac_id))
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eth_env_set_enetaddr("ethaddr", mac_id);
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#endif
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env_set("verify", "n");
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#if defined(CONFIG_SPEAR_USBTTY)
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env_set("stdin", "usbtty");
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env_set("stdout", "usbtty");
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env_set("stderr", "usbtty");
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#ifndef CONFIG_SYS_NO_DCACHE
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dcache_enable();
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#endif
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#endif
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return 0;
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}
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#ifdef CONFIG_SPEAR_EMI
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struct cust_emi_para {
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unsigned int tap;
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unsigned int tsdp;
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unsigned int tdpw;
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unsigned int tdpr;
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unsigned int tdcs;
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};
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/* EMI timing setting of m28w640hc of linux kernel */
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const struct cust_emi_para emi_timing_m28w640hc = {
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.tap = 0x10,
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.tsdp = 0x05,
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.tdpw = 0x0a,
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.tdpr = 0x0a,
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.tdcs = 0x05,
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};
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/* EMI timing setting of bootrom */
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const struct cust_emi_para emi_timing_bootrom = {
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.tap = 0xf,
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.tsdp = 0x0,
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.tdpw = 0xff,
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.tdpr = 0x111,
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.tdcs = 0x02,
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};
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void spear_emi_init(void)
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{
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const struct cust_emi_para *p = &emi_timing_m28w640hc;
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struct emi_regs *emi_regs_p = (struct emi_regs *)CONFIG_SPEAR_EMIBASE;
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unsigned int cs;
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unsigned int val, tmp;
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val = readl(CONFIG_SPEAR_RASBASE);
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if (val & EMI_ACKMSK)
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tmp = 0x3f;
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else
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tmp = 0x0;
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writel(tmp, &emi_regs_p->ack);
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for (cs = 0; cs < CONFIG_SYS_MAX_FLASH_BANKS; cs++) {
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writel(p->tap, &emi_regs_p->bank_regs[cs].tap);
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writel(p->tsdp, &emi_regs_p->bank_regs[cs].tsdp);
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writel(p->tdpw, &emi_regs_p->bank_regs[cs].tdpw);
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writel(p->tdpr, &emi_regs_p->bank_regs[cs].tdpr);
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writel(p->tdcs, &emi_regs_p->bank_regs[cs].tdcs);
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writel(EMI_CNTL_ENBBYTERW | ((val & 0x18) >> 3),
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&emi_regs_p->bank_regs[cs].control);
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}
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}
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#endif
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int spear_board_init(ulong mach_type)
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{
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gd->bd->bi_arch_number = mach_type;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR;
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#ifdef CONFIG_SPEAR_EMI
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spear_emi_init();
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#endif
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return 0;
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}
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#if defined(CONFIG_CMD_NET)
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static int i2c_read_mac(uchar *buffer)
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{
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u8 buf[2];
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i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
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/* Check if mac in i2c memory is valid */
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if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) {
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/* Valid mac address is saved in i2c eeprom */
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i2c_read(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, buffer, MAC_LEN);
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return 0;
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}
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return -1;
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}
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static int write_mac(uchar *mac)
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{
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u8 buf[2];
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buf[0] = (u8)MAGIC_BYTE0;
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buf[1] = (u8)MAGIC_BYTE1;
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i2c_write(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
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buf[0] = (u8)~MAGIC_BYTE0;
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buf[1] = (u8)~MAGIC_BYTE1;
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i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
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/* check if valid MAC address is saved in I2C EEPROM or not? */
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if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) {
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i2c_write(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, mac, MAC_LEN);
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puts("I2C EEPROM written with mac address \n");
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return 0;
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}
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puts("I2C EEPROM writing failed\n");
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return -1;
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}
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#endif
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int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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void (*sram_setfreq) (unsigned int, unsigned int);
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unsigned int frequency;
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#if defined(CONFIG_CMD_NET)
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unsigned char mac[6];
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#endif
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if ((argc > 3) || (argc < 2))
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return cmd_usage(cmdtp);
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if ((!strcmp(argv[1], "cpufreq")) || (!strcmp(argv[1], "ddrfreq"))) {
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frequency = simple_strtoul(argv[2], NULL, 0);
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if (frequency > 333) {
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printf("Frequency is limited to 333MHz\n");
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return 1;
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}
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sram_setfreq = memcpy((void *)SRAM_REL, setfreq, setfreq_sz);
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if (!strcmp(argv[1], "cpufreq")) {
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sram_setfreq(CPU, frequency);
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printf("CPU frequency changed to %u\n", frequency);
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} else {
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sram_setfreq(DDR, frequency);
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printf("DDR frequency changed to %u\n", frequency);
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}
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return 0;
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#if defined(CONFIG_CMD_NET)
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} else if (!strcmp(argv[1], "ethaddr")) {
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u32 reg;
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char *e, *s = argv[2];
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for (reg = 0; reg < 6; ++reg) {
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mac[reg] = s ? simple_strtoul(s, &e, 16) : 0;
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if (s)
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s = (*e) ? e + 1 : e;
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}
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write_mac(mac);
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return 0;
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#endif
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} else if (!strcmp(argv[1], "print")) {
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#if defined(CONFIG_CMD_NET)
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if (!i2c_read_mac(mac)) {
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printf("Ethaddr (from i2c mem) = %pM\n", mac);
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} else {
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printf("Ethaddr (from i2c mem) = Not set\n");
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}
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#endif
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return 0;
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}
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return cmd_usage(cmdtp);
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}
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U_BOOT_CMD(chip_config, 3, 1, do_chip_config,
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"configure chip",
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"chip_config cpufreq/ddrfreq frequency\n"
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#if defined(CONFIG_CMD_NET)
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"chip_config ethaddr XX:XX:XX:XX:XX:XX\n"
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#endif
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"chip_config print");
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