Convert CONFIG_SYS_DDR_RAW_TIMING to Kconfig

This converts the following to Kconfig:
   CONFIG_SYS_DDR_RAW_TIMING

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
2022-06-15 12:03:55 -04:00
parent bca4509d57
commit c24e8e2bb3
55 changed files with 54 additions and 18 deletions

View File

@@ -82,6 +82,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_TPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

View File

@@ -49,6 +49,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_COMMON_INIT_DDR=y
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y

View File

@@ -71,6 +71,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

View File

@@ -74,6 +74,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

View File

@@ -81,6 +81,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_TPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

View File

@@ -48,6 +48,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_COMMON_INIT_DDR=y
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y

View File

@@ -70,6 +70,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

View File

@@ -73,6 +73,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

View File

@@ -83,6 +83,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_TPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

View File

@@ -50,6 +50,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_COMMON_INIT_DDR=y
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y

View File

@@ -72,6 +72,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

View File

@@ -75,6 +75,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

View File

@@ -82,6 +82,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_TPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

View File

@@ -49,6 +49,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_COMMON_INIT_DDR=y
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y

View File

@@ -71,6 +71,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

View File

@@ -74,6 +74,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

View File

@@ -80,6 +80,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFF800C21
CONFIG_SYS_OR0_PRELIM=0xFFFF8396

View File

@@ -70,6 +70,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7

View File

@@ -73,6 +73,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7

View File

@@ -49,6 +49,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7

View File

@@ -79,6 +79,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFF800C21
CONFIG_SYS_OR0_PRELIM=0xFFFF8396

View File

@@ -69,6 +69,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7

View File

@@ -72,6 +72,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7

View File

@@ -48,6 +48,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7

View File

@@ -82,6 +82,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=2
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFF800C21
CONFIG_SYS_OR0_PRELIM=0xFFFF8796

View File

@@ -72,6 +72,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=2
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEC001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7

View File

@@ -75,6 +75,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=2
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEC001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7

View File

@@ -51,6 +51,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=2
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEC001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7

View File

@@ -84,6 +84,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFF800C21
CONFIG_SYS_OR0_PRELIM=0xFFFF8396

View File

@@ -74,6 +74,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7

View File

@@ -77,6 +77,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7

View File

@@ -53,6 +53,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7

View File

@@ -83,6 +83,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFF800C21
CONFIG_SYS_OR0_PRELIM=0xFFFF8396

View File

@@ -73,6 +73,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7

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@@ -76,6 +76,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7

View File

@@ -52,6 +52,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7

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@@ -95,6 +95,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

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@@ -62,6 +62,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

View File

@@ -65,6 +65,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

View File

@@ -65,6 +65,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

View File

@@ -62,6 +62,7 @@ CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

View File

@@ -93,6 +93,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

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@@ -89,6 +89,7 @@ CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

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@@ -45,6 +45,7 @@ CONFIG_ETHPRIME="FM1@DTSEC3"
CONFIG_DM=y
# CONFIG_DDR_SPD is not set
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

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@@ -49,6 +49,7 @@ CONFIG_DM=y
CONFIG_FSL_CAAM=y
# CONFIG_DDR_SPD is not set
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

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@@ -44,6 +44,7 @@ CONFIG_ETHPRIME="FM1@DTSEC3"
CONFIG_DM=y
# CONFIG_DDR_SPD is not set
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

View File

@@ -51,6 +51,7 @@ CONFIG_DM=y
CONFIG_FSL_CAAM=y
# CONFIG_DDR_SPD is not set
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y