Merge branch 'master' of git://git.denx.de/u-boot-rockchip

arch/arm/Kconfig

@@ -618,6 +618,11 @@ config ARCH_MX6
 	select SYS_FSL_SEC_LE
 	select SYS_THUMB_BUILD if SPL
 
+if ARCH_MX6
+config SPL_LDSCRIPT
+        default "arch/arm/mach-omap2/u-boot-spl.lds"
+endif
+
 config ARCH_MX5
 	bool "Freescale MX5"
 	select CPU_V7
@@ -1233,3 +1238,10 @@ source "board/zipitz2/Kconfig"
 source "arch/arm/Kconfig.debug"
 
 endmenu
+
+config SPL_LDSCRIPT
+        default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if TARGET_APX4DEVKIT || TARGET_BG0900 || TARGET_M28EVK || TARGET_MX23_OLINUXINO || TARGET_MX23EVK || TARGET_MX28EVK || TARGET_SANSA_FUZE_PLUS || TARGET_SC_SPS_1 || TARGET_TS4600 || TARGET_XFI3
+        default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
+	default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64
+
+

arch/arm/cpu/armv8/Makefile

@@ -8,7 +8,9 @@
 extra-y	:= start.o
 
 obj-y	+= cpu.o
+ifndef CONFIG_$(SPL_TPL_)TIMER
 obj-y	+= generic_timer.o
+endif
 obj-y	+= cache_v8.o
 obj-y	+= exceptions.o
 obj-y	+= cache.o

arch/arm/cpu/armv8/cache.S

@@ -22,6 +22,7 @@
  * x1: 0 clean & invalidate, 1 invalidate only
  * x2~x9: clobbered
  */
+.pushsection .text.__asm_dcache_level, "ax"
 ENTRY(__asm_dcache_level)
 	lsl	x12, x0, #1
 	msr	csselr_el1, x12		/* select cache level */
@@ -58,6 +59,7 @@ loop_way:
 
 	ret
 ENDPROC(__asm_dcache_level)
+.popsection
 
 /*
  * void __asm_flush_dcache_all(int invalidate_only)
@@ -66,6 +68,7 @@ ENDPROC(__asm_dcache_level)
  *
  * flush or invalidate all data cache by SET/WAY.
  */
+.pushsection .text.__asm_dcache_all, "ax"
 ENTRY(__asm_dcache_all)
 	mov	x1, x0
 	dsb	sy
@@ -102,16 +105,21 @@ skip:
 finished:
 	ret
 ENDPROC(__asm_dcache_all)
+.popsection
 
+.pushsection .text.__asm_flush_dcache_all, "ax"
 ENTRY(__asm_flush_dcache_all)
 	mov	x0, #0
 	b	__asm_dcache_all
 ENDPROC(__asm_flush_dcache_all)
+.popsection
 
+.pushsection .text.__asm_invalidate_dcache_all, "ax"
 ENTRY(__asm_invalidate_dcache_all)
 	mov	x0, #0x1
 	b	__asm_dcache_all
 ENDPROC(__asm_invalidate_dcache_all)
+.popsection
 
 /*
  * void __asm_flush_dcache_range(start, end)
@@ -121,6 +129,7 @@ ENDPROC(__asm_invalidate_dcache_all)
  * x0: start address
  * x1: end address
  */
+.pushsection .text.__asm_flush_dcache_range, "ax"
 ENTRY(__asm_flush_dcache_range)
 	mrs	x3, ctr_el0
 	lsr	x3, x3, #16
@@ -138,6 +147,7 @@ ENTRY(__asm_flush_dcache_range)
 	dsb	sy
 	ret
 ENDPROC(__asm_flush_dcache_range)
+.popsection
 /*
  * void __asm_invalidate_dcache_range(start, end)
  *
@@ -146,6 +156,7 @@ ENDPROC(__asm_flush_dcache_range)
  * x0: start address
  * x1: end address
  */
+.pushsection .text.__asm_invalidate_dcache_range, "ax"
 ENTRY(__asm_invalidate_dcache_range)
 	mrs	x3, ctr_el0
 	ubfm	x3, x3, #16, #19
@@ -162,41 +173,51 @@ ENTRY(__asm_invalidate_dcache_range)
 	dsb	sy
 	ret
 ENDPROC(__asm_invalidate_dcache_range)
+.popsection
 
 /*
  * void __asm_invalidate_icache_all(void)
  *
  * invalidate all tlb entries.
  */
+.pushsection .text.__asm_invalidate_icache_all, "ax"
 ENTRY(__asm_invalidate_icache_all)
 	ic	ialluis
 	isb	sy
 	ret
 ENDPROC(__asm_invalidate_icache_all)
+.popsection
 
+.pushsection .text.__asm_invalidate_l3_dcache, "ax"
 ENTRY(__asm_invalidate_l3_dcache)
 	mov	x0, #0			/* return status as success */
 	ret
 ENDPROC(__asm_invalidate_l3_dcache)
 	.weak	__asm_invalidate_l3_dcache
+.popsection
 
+.pushsection .text.__asm_flush_l3_dcache, "ax"
 ENTRY(__asm_flush_l3_dcache)
 	mov	x0, #0			/* return status as success */
 	ret
 ENDPROC(__asm_flush_l3_dcache)
 	.weak	__asm_flush_l3_dcache
+.popsection
 
+.pushsection .text.__asm_invalidate_l3_icache, "ax"
 ENTRY(__asm_invalidate_l3_icache)
 	mov	x0, #0			/* return status as success */
 	ret
 ENDPROC(__asm_invalidate_l3_icache)
 	.weak	__asm_invalidate_l3_icache
+.popsection
 
 /*
  * void __asm_switch_ttbr(ulong new_ttbr)
  *
  * Safely switches to a new page table.
  */
+.pushsection .text.__asm_switch_ttbr, "ax"
 ENTRY(__asm_switch_ttbr)
 	/* x2 = SCTLR (alive throghout the function) */
 	switch_el x4, 3f, 2f, 1f
@@ -244,3 +265,4 @@ ENTRY(__asm_switch_ttbr)
 
 	ret	x3
 ENDPROC(__asm_switch_ttbr)
+.popsection

arch/arm/cpu/armv8/fsl-layerscape/Kconfig

@@ -393,3 +393,6 @@ config SYS_MC_RSV_MEM_ALIGN
 	help
 	  Reserved memory needs to be aligned for MC to use. Default value
 	  is 512MB.
+
+config SPL_LDSCRIPT
+	default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A

arch/arm/cpu/armv8/tlb.S

@@ -14,7 +14,8 @@
  * void __asm_invalidate_tlb_all(void)
  *
  * invalidate all tlb entries.
- */
+*/
+.pushsection .text.__asm_invalidate_tlb_all, "ax"
 ENTRY(__asm_invalidate_tlb_all)
 	switch_el x9, 3f, 2f, 1f
 3:	tlbi	alle3
@@ -31,3 +32,4 @@ ENTRY(__asm_invalidate_tlb_all)
 0:
 	ret
 ENDPROC(__asm_invalidate_tlb_all)
+.popsection

arch/arm/cpu/armv8/transition.S

@@ -10,6 +10,7 @@
 #include <linux/linkage.h>
 #include <asm/macro.h>
 
+.pushsection .text.armv8_switch_to_el2, "ax"
 ENTRY(armv8_switch_to_el2)
 	switch_el x6, 1f, 0f, 0f
 0:
@@ -30,7 +31,9 @@ ENTRY(armv8_switch_to_el2)
 	br x4
 1:	armv8_switch_to_el2_m x4, x5, x6
 ENDPROC(armv8_switch_to_el2)
+.popsection
 
+.pushsection .text.armv8_switch_to_el1, "ax"
 ENTRY(armv8_switch_to_el1)
 	switch_el x6, 0f, 1f, 0f
 0:
@@ -40,7 +43,10 @@ ENTRY(armv8_switch_to_el1)
 	br x4
 1:	armv8_switch_to_el1_m x4, x5, x6
 ENDPROC(armv8_switch_to_el1)
+.popsection
 
+.pushsection .text.armv8_el2_to_aarch32, "ax"
 WEAK(armv8_el2_to_aarch32)
 	ret
 ENDPROC(armv8_el2_to_aarch32)
+.popsection

arch/arm/dts/Makefile

@@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rk3288-veyron-mickey.dtb \
 	rk3288-veyron-minnie.dtb \
 	rk3328-evb.dtb \
+	rk3368-lion.dtb \
 	rk3368-sheep.dtb \
 	rk3368-geekbox.dtb \
 	rk3368-px5-evb.dtb \

arch/arm/dts/rk3229-evb.dts

@@ -72,6 +72,17 @@
 	status = "okay";
 };
 
+&sdmmc {
+	status = "okay";
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	card-detect-delay = <200>;
+	disable-wp;
+	num-slots = <1>;
+	supports-sd;
+};
+
 &uart2 {
 	status = "okay";
 };

arch/arm/dts/rk322x.dtsi

@@ -21,6 +21,8 @@
 		serial0 = &uart0;
 		serial1 = &uart1;
 		serial2 = &uart2;
+		mmc0 = &emmc;
+		mmc1 = &sdmmc;
 	};
 
 	cpus {
@@ -383,12 +385,38 @@
 		status = "disabled";
 	};
 
+	sdmmc: dwmmc@30000000 {
+		compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
+		reg = <0x30000000 0x4000>;
+		max-frequency = <150000000>;
+		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+		clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+		fifo-depth = <0x100>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
+		status = "disabled";
+	};
+
+	sdio: dwmmc@30010000 {
+		compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
+		reg = <0x30010000 0x4000>;
+		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
+			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+		clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+		fifo-depth = <0x100>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
+		status = "disabled";
+	};
+
 	emmc: dwmmc@30020000 {
 		compatible = "rockchip,rk3288-dw-mshc";
 		reg = <0x30020000 0x4000>;
+		max-frequency = <150000000>;
 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <37500000>;
-		max-frequency = <37500000>;
 		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 		clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
@@ -520,6 +548,40 @@
 			drive-strength = <12>;
 		};
 
+		sdmmc {
+			sdmmc_clk: sdmmc-clk {
+				rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
+			};
+
+			sdmmc_cmd: sdmmc-cmd {
+				rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
+			};
+
+			sdmmc_bus4: sdmmc-bus4 {
+				rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+						<1 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+						<1 20 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+						<1 21 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
+			};
+		};
+
+		sdio {
+			sdio_clk: sdio-clk {
+				rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
+			};
+
+			sdio_cmd: sdio-cmd {
+				rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
+			};
+
+			sdio_bus4: sdio-bus4 {
+				rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+						<3 3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+						<3 4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+						<3 5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
+			};
+		};
+
 		emmc {
 			emmc_clk: emmc-clk {
 				rockchip,pins = <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>;

arch/arm/dts/rk3368-geekbox-u-boot.dtsi

@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier:     GPL-2.0+	X11
+ */
+
+&pinctrl {
+	u-boot,dm-pre-reloc;
+};
+
+&service_msch {
+	u-boot,dm-pre-reloc;
+};
+
+&dmc {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&pmugrf {
+	u-boot,dm-pre-reloc;
+};
+
+&cru {
+	u-boot,dm-pre-reloc;
+};
+
+&grf {
+	u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+	u-boot,dm-pre-reloc;
+};

arch/arm/dts/rk3368-lion-u-boot.dtsi

@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier:     GPL-2.0+	X11
+ */
+
+/ {
+	config {
+		u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */
+		u-boot,mmc-env-offset = <0x4000>;      /* @  16KB */
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		u-boot,spl-boot-order = &emmc, &sdmmc;
+	};
+
+};
+
+&pinctrl {
+	u-boot,dm-pre-reloc;
+};
+
+&service_msch {
+	u-boot,dm-pre-reloc;
+};
+
+&dmc {
+	u-boot,dm-pre-reloc;
+
+	/*
+	 * Validation of throughput using SPEC2000 shows the following
+	 * relative performance for the different memory schedules:
+	 *  - CBDR: 30.1
+	 *  - CBRD: 29.8
+	 *  - CRBD: 29.9
+	 * Note that the best performance for any given application workload
+	 * may vary from the default configured here (e.g. 164.gzip is fastest
+	 * with CBRD, whereas 252.eon and 186.crafty are fastest with CRBD).
+	 *
+	 * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for
+	 * details on the 'rockchip,memory-schedule' property and how it
+	 * affects the physical-address to device-address mapping.
+	 */
+	rockchip,memory-schedule = <DMC_MSCH_CBDR>;
+	rockchip,ddr-frequency = <800000000>;
+	rockchip,ddr-speed-bin = <DDR3_1600K>;
+
+	status = "okay";
+};
+
+&pmugrf {
+	u-boot,dm-pre-reloc;
+};
+
+&sgrf {
+        u-boot,dm-pre-reloc;
+};
+
+&cru {
+	u-boot,dm-pre-reloc;
+};
+
+&grf {
+	u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+};
+
+&emmc {
+	u-boot,dm-pre-reloc;
+};
+
+&sdmmc {
+	u-boot,dm-pre-reloc;
+};
+
+&spi1 {
+	u-boot,dm-pre-reloc;
+
+	spiflash: w25q32dw@0 {
+		u-boot,dm-pre-reloc;
+	};
+};
+
+&timer0 {
+	u-boot,dm-pre-reloc;
+	clock-frequency = <24000000>;
+};
+
+

arch/arm/dts/rk3368-lion.dts

@@ -0,0 +1,195 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier:     GPL-2.0+	X11
+ */
+
+/dts-v1/;
+#include "rk3368.dtsi"
+#include "rk3368-lion-u-boot.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "Theobroma Systems RK3368-uQ7 SoM";
+	compatible = "tsd,rk3368-uq7", "tsd,lion", "rockchip,rk3368";
+
+	aliases {
+		mmc0 = &emmc;
+		mmc1 = &sdmmc;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+
+	ext_gmac: gmac-clk {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "ext_gmac";
+		#clock-cells = <0>;
+	};
+
+	vcc_sys: vcc-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&emmc {
+	status = "okay";
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	clock-frequency = <150000000>;
+	disable-wp;
+	keep-power-in-suspend;
+	non-removable;
+	num-slots = <1>;
+	vmmc-supply = <&vcc33_io>;
+	vqmmc-supply = <&vcc18_io>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>;
+};
+
+&sdmmc {
+	status = "okay";
+};
+
+&gmac {
+	status = "okay";
+	phy-supply = <&vcc33_io>;
+	phy-mode = "rgmii";
+	clock_in_out = "input";
+	snps,reset-gpio = <&gpio3 11 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <2 10000 50000>;
+	assigned-clocks = <&cru SCLK_MAC>;
+	assigned-clock-parents = <&ext_gmac>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>;
+	tx_delay = <0x10>;
+	rx_delay = <0x10>;
+};
+
+&i2c0 {
+	status = "okay";
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+		rockchip,system-power-controller;
+		vcc1-supply = <&vcc_sys>;
+		vcc2-supply = <&vcc_sys>;
+		vcc3-supply = <&vcc_sys>;
+		vcc4-supply = <&vcc_sys>;
+		vcc6-supply = <&vcc_sys>;
+		vcc7-supply = <&vcc_sys>;
+		vcc8-supply = <&vcc_sys>;
+		vcc9-supply = <&vcc_sys>;
+		vcc10-supply = <&vcc_sys>;
+		vcc11-supply = <&vcc_sys>;
+		vcc12-supply = <&vcc_sys>;
+		clock-output-names = "xin32k", "rk808-clkout2";
+		#clock-cells = <1>;
+
+		regulators {
+			vdd_cpu: DCDC_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-name = "vdd_cpu";
+			};
+
+			vdd_log: DCDC_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-name = "vdd_log";
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc_ddr";
+			};
+
+			vcc33_io: DCDC_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc33_io";
+			};
+
+			vcc33_video: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc33_video";
+			};
+
+			vdd10_pll: LDO_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-name = "vdd10_pll";
+			};
+
+			vcc18_io: LDO_REG4 {
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc18_io";
+			};
+
+			vdd10_video: LDO_REG6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-name = "vdd10_video";
+			};
+
+			vcc18_video: LDO_REG8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc18_video";
+			};
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&spi1 {
+	status = "okay";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	spiflash: w25q32dw@0 {
+		compatible = "spi-flash";
+		reg = <0>;
+		spi-max-frequency = <49500000>;
+		spi-cpol;
+		spi-cpha;
+	};
+};

arch/arm/dts/rk3368-px5-evb-u-boot.dtsi

@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier:     GPL-2.0+	X11
+ */
+
+&pinctrl {
+	u-boot,dm-pre-reloc;
+};
+
+&service_msch {
+	u-boot,dm-pre-reloc;
+};
+
+&dmc {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&pmugrf {
+	u-boot,dm-pre-reloc;
+};
+
+&cru {
+	u-boot,dm-pre-reloc;
+};
+
+&grf {
+	u-boot,dm-pre-reloc;
+};
+
+&uart4 {
+	u-boot,dm-pre-reloc;
+};

arch/arm/dts/rk3368-sheep-u-boot.dtsi

@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier:     GPL-2.0+	X11
+ */
+
+&pinctrl {
+	u-boot,dm-pre-reloc;
+};
+
+&service_msch {
+	u-boot,dm-pre-reloc;
+};
+
+&dmc {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&pmugrf {
+	u-boot,dm-pre-reloc;
+};
+
+&cru {
+	u-boot,dm-pre-reloc;
+};
+
+&grf {
+	u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+	u-boot,dm-pre-reloc;
+};

arch/arm/dts/rk3368.dtsi

@@ -46,6 +46,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/pinctrl/rockchip.h>
 #include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/memory/rk3368-dmc.h>
 
 / {
 	compatible = "rockchip,rk3368";
@@ -227,6 +228,21 @@
 		#clock-cells = <0>;
 	};
 
+	dmc: dmc@ff610000 {
+		compatible = "rockchip,rk3368-dmc", "syscon";
+		rockchip,cru = <&cru>;
+		rockchip,grf = <&grf>;
+		rockchip,msch = <&service_msch>;
+		reg = <0 0xff610000 0 0x400
+		       0 0xff620000 0 0x400>;
+	};
+
+	service_msch: syscon@ffac0000 {
+		compatible = "rockchip,rk3368-msch", "syscon";
+		reg = <0x0 0xffac0000 0x0 0x2000>;
+		status = "okay";
+	};
+
 	sdmmc: dwmmc@ff0c0000 {
 		compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 		reg = <0x0 0xff0c0000 0x0 0x4000>;
@@ -546,12 +562,6 @@
 		status = "disabled";
 	};
 
-	dmc: dmc@ff610000 {
-		u-boot,dm-pre-reloc;
-		compatible = "rockchip,rk3368-dmc", "syscon";
-		reg = <0x0 0xff610000 0x0 0x1000>;
-	};
-
 	i2c0: i2c@ff650000 {
 		compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 		reg = <0x0 0xff650000 0x0 0x1000>;
@@ -647,11 +657,15 @@
 	};
 
 	pmugrf: syscon@ff738000 {
-		u-boot,dm-pre-reloc;
 		compatible = "rockchip,rk3368-pmugrf", "syscon";
 		reg = <0x0 0xff738000 0x0 0x1000>;
 	};
 
+	sgrf: syscon@ff740000 {
+	        compatible = "rockchip,rk3368-sgrf", "syscon";
+		reg = <0x0 0xff740000 0x0 0x1000>;
+	};
+
 	cru: clock-controller@ff760000 {
 		compatible = "rockchip,rk3368-cru";
 		reg = <0x0 0xff760000 0x0 0x1000>;
@@ -673,7 +687,7 @@
 		status = "disabled";
 	};
 
-	timer@ff810000 {
+	timer0: timer@ff810000 {
 		compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
 		reg = <0x0 0xff810000 0x0 0x20>;
 		interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;

arch/arm/include/asm/arch-rockchip/cru_rk3288.h

@@ -85,7 +85,7 @@ enum {
 	EMMC_PLL_SELECT_24MHZ,
 
 	EMMC_DIV_SHIFT		= 8,
-	EMMC_DIV_MASK		= 0x3f < EMMC_DIV_SHIFT,
+	EMMC_DIV_MASK		= 0x3f << EMMC_DIV_SHIFT,
 
 	SDIO0_PLL_SHIFT		= 6,
 	SDIO0_PLL_MASK		= 3 << SDIO0_PLL_SHIFT,

arch/arm/include/asm/arch-rockchip/cru_rk3368.h

@@ -89,19 +89,26 @@ enum {
 	MCU_CLK_DIV_SHIFT		= 0,
 	MCU_CLK_DIV_MASK		= GENMASK(4, 0),
 
+	/* CLKSEL43_CON */
+	GMAC_MUX_SEL_EXTCLK             = BIT(8),
+
 	/* CLKSEL51_CON */
 	MMC_PLL_SEL_SHIFT		= 8,
 	MMC_PLL_SEL_MASK		= GENMASK(9, 8),
-	MMC_PLL_SEL_CPLL		= 0,
-	MMC_PLL_SEL_GPLL,
-	MMC_PLL_SEL_USBPHY_480M,
-	MMC_PLL_SEL_24M,
+	MMC_PLL_SEL_CPLL		= (0 << MMC_PLL_SEL_SHIFT),
+	MMC_PLL_SEL_GPLL                = (1 << MMC_PLL_SEL_SHIFT),
+	MMC_PLL_SEL_USBPHY_480M         = (2 << MMC_PLL_SEL_SHIFT),
+	MMC_PLL_SEL_24M                 = (3 << MMC_PLL_SEL_SHIFT),
 	MMC_CLK_DIV_SHIFT		= 0,
 	MMC_CLK_DIV_MASK		= GENMASK(6, 0),
 
 	/* SOFTRST1_CON */
 	MCU_PO_SRST_MASK		= BIT(13),
 	MCU_SYS_SRST_MASK		= BIT(12),
+	DMA1_SRST_REQ                   = BIT(2),
+
+	/* SOFTRST4_CON */
+	DMA2_SRST_REQ                   = BIT(0),
 
 	/* GLB_RST_CON */
 	PMU_GLB_SRST_CTRL_SHIFT		= 2,

arch/arm/include/asm/arch-rockchip/ddr_rk3368.h

@@ -0,0 +1,187 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __ASM_ARCH_DDR_RK3368_H__
+#define __ASM_ARCH_DDR_RK3368_H__
+
+/*
+ * The RK3368 DDR PCTL differs from the incarnation in the RK3288 only
+ * in a few details. Most notably, it has an additional field to track
+ * tREFI in controller cycles (i.e. trefi_mem_ddr3).
+ */
+struct rk3368_ddr_pctl {
+	u32 scfg;
+	u32 sctl;
+	u32 stat;
+	u32 intrstat;
+	u32 reserved0[12];
+	u32 mcmd;
+	u32 powctl;
+	u32 powstat;
+	u32 cmdtstat;
+	u32 cmdtstaten;
+	u32 reserved1[3];
+	u32 mrrcfg0;
+	u32 mrrstat0;
+	u32 mrrstat1;
+	u32 reserved2[4];
+	u32 mcfg1;
+	u32 mcfg;
+	u32 ppcfg;
+	u32 mstat;
+	u32 lpddr2zqcfg;
+	u32 reserved3;
+	u32 dtupdes;
+	u32 dtuna;
+	u32 dtune;
+	u32 dtuprd0;
+	u32 dtuprd1;
+	u32 dtuprd2;
+	u32 dtuprd3;
+	u32 dtuawdt;
+	u32 reserved4[3];
+	u32 togcnt1u;
+	u32 tinit;
+	u32 trsth;
+	u32 togcnt100n;
+	u32 trefi;
+	u32 tmrd;
+	u32 trfc;
+	u32 trp;
+	u32 trtw;
+	u32 tal;
+	u32 tcl;
+	u32 tcwl;
+	u32 tras;
+	u32 trc;
+	u32 trcd;
+	u32 trrd;
+	u32 trtp;
+	u32 twr;
+	u32 twtr;
+	u32 texsr;
+	u32 txp;
+	u32 txpdll;
+	u32 tzqcs;
+	u32 tzqcsi;
+	u32 tdqs;
+	u32 tcksre;
+	u32 tcksrx;
+	u32 tcke;
+	u32 tmod;
+	u32 trstl;
+	u32 tzqcl;
+	u32 tmrr;
+	u32 tckesr;
+	u32 tdpd;
+	u32 trefi_mem_ddr3;
+	u32 reserved5[45];
+	u32 dtuwactl;
+	u32 dturactl;
+	u32 dtucfg;
+	u32 dtuectl;
+	u32 dtuwd0;
+	u32 dtuwd1;
+	u32 dtuwd2;
+	u32 dtuwd3;
+	u32 dtuwdm;
+	u32 dturd0;
+	u32 dturd1;
+	u32 dturd2;
+	u32 dturd3;
+	u32 dtulfsrwd;
+	u32 dtulfsrrd;
+	u32 dtueaf;
+	u32 dfitctrldelay;
+	u32 dfiodtcfg;
+	u32 dfiodtcfg1;
+	u32 dfiodtrankmap;
+	u32 dfitphywrdata;
+	u32 dfitphywrlat;
+	u32 reserved7[2];
+	u32 dfitrddataen;
+	u32 dfitphyrdlat;
+	u32 reserved8[2];
+	u32 dfitphyupdtype0;
+	u32 dfitphyupdtype1;
+	u32 dfitphyupdtype2;
+	u32 dfitphyupdtype3;
+	u32 dfitctrlupdmin;
+	u32 dfitctrlupdmax;
+	u32 dfitctrlupddly;
+	u32 reserved9;
+	u32 dfiupdcfg;
+	u32 dfitrefmski;
+	u32 dfitctrlupdi;
+	u32 reserved10[4];
+	u32 dfitrcfg0;
+	u32 dfitrstat0;
+	u32 dfitrwrlvlen;
+	u32 dfitrrdlvlen;
+	u32 dfitrrdlvlgateen;
+	u32 dfiststat0;
+	u32 dfistcfg0;
+	u32 dfistcfg1;
+	u32 reserved11;
+	u32 dfitdramclken;
+	u32 dfitdramclkdis;
+	u32 dfistcfg2;
+	u32 dfistparclr;
+	u32 dfistparlog;
+	u32 reserved12[3];
+	u32 dfilpcfg0;
+	u32 reserved13[3];
+	u32 dfitrwrlvlresp0;
+	u32 dfitrwrlvlresp1;
+	u32 dfitrwrlvlresp2;
+	u32 dfitrrdlvlresp0;
+	u32 dfitrrdlvlresp1;
+	u32 dfitrrdlvlresp2;
+	u32 dfitrwrlvldelay0;
+	u32 dfitrwrlvldelay1;
+	u32 dfitrwrlvldelay2;
+	u32 dfitrrdlvldelay0;
+	u32 dfitrrdlvldelay1;
+	u32 dfitrrdlvldelay2;
+	u32 dfitrrdlvlgatedelay0;
+	u32 dfitrrdlvlgatedelay1;
+	u32 dfitrrdlvlgatedelay2;
+	u32 dfitrcmd;
+	u32 reserved14[46];
+	u32 ipvr;
+	u32 iptr;
+};
+check_member(rk3368_ddr_pctl, iptr, 0x03fc);
+
+struct rk3368_ddrphy {
+	u32 reg[0x100];
+};
+check_member(rk3368_ddrphy, reg[0xff], 0x03fc);
+
+struct rk3368_msch {
+	u32 coreid;
+	u32 revisionid;
+	u32 ddrconf;
+	u32 ddrtiming;
+	u32 ddrmode;
+	u32 readlatency;
+	u32 reserved1[8];
+	u32 activate;
+	u32 devtodev;
+};
+check_member(rk3368_msch, devtodev, 0x003c);
+
+/* GRF_SOC_CON0 */
+enum {
+	NOC_RSP_ERR_STALL = BIT(9),
+	MOBILE_DDR_SEL = BIT(4),
+	DDR0_16BIT_EN = BIT(3),
+	MSCH0_MAINDDR3_DDR3 = BIT(2),
+	MSCH0_MAINPARTIALPOP = BIT(1),
+	UPCTL_C_ACTIVE = BIT(0),
+};
+
+#endif

arch/arm/include/asm/arch-rockchip/grf_rk3368.h

@@ -1,4 +1,6 @@
-/* (C) Copyright 2016 Rockchip Electronics Co., Ltd
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
  *
  * SPDX-License-Identifier:     GPL-2.0+
  */
@@ -74,8 +76,11 @@ struct rk3368_grf {
 	u32 soc_con15;
 	u32 soc_con16;
 	u32 soc_con17;
+	u32 reserved5[0x6e];
+	u32 ddrc0_con0;
 };
 check_member(rk3368_grf, soc_con17, 0x444);
+check_member(rk3368_grf, ddrc0_con0, 0x600);
 
 struct rk3368_pmu_grf {
 	u32 gpio0a_iomux;
@@ -92,323 +97,11 @@ struct rk3368_pmu_grf {
 	u32 gpio0d_drv;
 	u32 gpio0l_sr;
 	u32 gpio0h_sr;
-	u32 reserved[(0x200 - 0x34) / 4 - 1];
+	u32 reserved[0x72];
 	u32 os_reg[4];
 };
-check_member(rk3368_pmu_grf, os_reg[3], 0x20c);
-
-/*GRF_GPIO0C_IOMUX*/
-enum {
-	GPIO0C7_SHIFT		= 14,
-	GPIO0C7_MASK		= 3 << GPIO0C7_SHIFT,
-	GPIO0C7_GPIO		= 0,
-	GPIO0C7_LCDC_D19,
-	GPIO0C7_TRACE_D9,
-	GPIO0C7_UART1_RTSN,
-
-	GPIO0C6_SHIFT           = 12,
-	GPIO0C6_MASK            = 3 << GPIO0C6_SHIFT,
-	GPIO0C6_GPIO            = 0,
-	GPIO0C6_LCDC_D18,
-	GPIO0C6_TRACE_D8,
-	GPIO0C6_UART1_CTSN,
-
-	GPIO0C5_SHIFT           = 10,
-	GPIO0C5_MASK            = 3 << GPIO0C5_SHIFT,
-	GPIO0C5_GPIO            = 0,
-	GPIO0C5_LCDC_D17,
-	GPIO0C5_TRACE_D7,
-	GPIO0C5_UART1_SOUT,
-
-	GPIO0C4_SHIFT           = 8,
-	GPIO0C4_MASK            = 3 << GPIO0C4_SHIFT,
-	GPIO0C4_GPIO            = 0,
-	GPIO0C4_LCDC_D16,
-	GPIO0C4_TRACE_D6,
-	GPIO0C4_UART1_SIN,
-
-	GPIO0C3_SHIFT           = 6,
-	GPIO0C3_MASK            = 3 << GPIO0C3_SHIFT,
-	GPIO0C3_GPIO            = 0,
-	GPIO0C3_LCDC_D15,
-	GPIO0C3_TRACE_D5,
-	GPIO0C3_MCU_JTAG_TDO,
-
-	GPIO0C2_SHIFT           = 4,
-	GPIO0C2_MASK            = 3 << GPIO0C2_SHIFT,
-	GPIO0C2_GPIO            = 0,
-	GPIO0C2_LCDC_D14,
-	GPIO0C2_TRACE_D4,
-	GPIO0C2_MCU_JTAG_TDI,
-
-	GPIO0C1_SHIFT           = 2,
-	GPIO0C1_MASK            = 3 << GPIO0C1_SHIFT,
-	GPIO0C1_GPIO            = 0,
-	GPIO0C1_LCDC_D13,
-	GPIO0C1_TRACE_D3,
-	GPIO0C1_MCU_JTAG_TRTSN,
-
-	GPIO0C0_SHIFT           = 0,
-	GPIO0C0_MASK            = 3 << GPIO0C0_SHIFT,
-	GPIO0C0_GPIO            = 0,
-	GPIO0C0_LCDC_D12,
-	GPIO0C0_TRACE_D2,
-	GPIO0C0_MCU_JTAG_TDO,
-};
-
-/*GRF_GPIO0D_IOMUX*/
-enum {
-	GPIO0D7_SHIFT           = 14,
-	GPIO0D7_MASK            = 3 << GPIO0D7_SHIFT,
-	GPIO0D7_GPIO            = 0,
-	GPIO0D7_LCDC_DCLK,
-	GPIO0D7_TRACE_CTL,
-	GPIO0D7_PMU_DEBUG5,
-
-	GPIO0D6_SHIFT           = 12,
-	GPIO0D6_MASK            = 3 << GPIO0D6_SHIFT,
-	GPIO0D6_GPIO            = 0,
-	GPIO0D6_LCDC_DEN,
-	GPIO0D6_TRACE_CLK,
-	GPIO0D6_PMU_DEBUG4,
-
-	GPIO0D5_SHIFT           = 10,
-	GPIO0D5_MASK            = 3 << GPIO0D5_SHIFT,
-	GPIO0D5_GPIO            = 0,
-	GPIO0D5_LCDC_VSYNC,
-	GPIO0D5_TRACE_D15,
-	GPIO0D5_PMU_DEBUG3,
-
-	GPIO0D4_SHIFT           = 8,
-	GPIO0D4_MASK            = 3 << GPIO0D4_SHIFT,
-	GPIO0D4_GPIO            = 0,
-	GPIO0D4_LCDC_HSYNC,
-	GPIO0D4_TRACE_D14,
-	GPIO0D4_PMU_DEBUG2,
-
-	GPIO0D3_SHIFT           = 6,
-	GPIO0D3_MASK            = 3 << GPIO0D3_SHIFT,
-	GPIO0D3_GPIO            = 0,
-	GPIO0D3_LCDC_D23,
-	GPIO0D3_TRACE_D13,
-	GPIO0D3_UART4_SIN,
-
-	GPIO0D2_SHIFT           = 4,
-	GPIO0D2_MASK            = 3 << GPIO0D2_SHIFT,
-	GPIO0D2_GPIO            = 0,
-	GPIO0D2_LCDC_D22,
-	GPIO0D2_TRACE_D12,
-	GPIO0D2_UART4_SOUT,
-
-	GPIO0D1_SHIFT           = 2,
-	GPIO0D1_MASK            = 3 << GPIO0D1_SHIFT,
-	GPIO0D1_GPIO            = 0,
-	GPIO0D1_LCDC_D21,
-	GPIO0D1_TRACE_D11,
-	GPIO0D1_UART4_RTSN,
-
-	GPIO0D0_SHIFT           = 0,
-	GPIO0D0_MASK            = 3 << GPIO0D0_SHIFT,
-	GPIO0D0_GPIO            = 0,
-	GPIO0D0_LCDC_D20,
-	GPIO0D0_TRACE_D10,
-	GPIO0D0_UART4_CTSN,
-};
-
-/*GRF_GPIO2A_IOMUX*/
-enum {
-	GPIO2A7_SHIFT           = 14,
-	GPIO2A7_MASK            = 3 << GPIO2A7_SHIFT,
-	GPIO2A7_GPIO            = 0,
-	GPIO2A7_SDMMC0_D2,
-	GPIO2A7_JTAG_TCK,
-
-	GPIO2A6_SHIFT           = 12,
-	GPIO2A6_MASK            = 3 << GPIO2A6_SHIFT,
-	GPIO2A6_GPIO            = 0,
-	GPIO2A6_SDMMC0_D1,
-	GPIO2A6_UART2_SIN,
-
-	GPIO2A5_SHIFT           = 10,
-	GPIO2A5_MASK            = 3 << GPIO2A5_SHIFT,
-	GPIO2A5_GPIO            = 0,
-	GPIO2A5_SDMMC0_D0,
-	GPIO2A5_UART2_SOUT,
-
-	GPIO2A4_SHIFT           = 8,
-	GPIO2A4_MASK            = 3 << GPIO2A4_SHIFT,
-	GPIO2A4_GPIO            = 0,
-	GPIO2A4_FLASH_DQS,
-	GPIO2A4_EMMC_CLKO,
-
-	GPIO2A3_SHIFT           = 6,
-	GPIO2A3_MASK            = 3 << GPIO2A3_SHIFT,
-	GPIO2A3_GPIO            = 0,
-	GPIO2A3_FLASH_CSN3,
-	GPIO2A3_EMMC_RSTNO,
-
-	GPIO2A2_SHIFT           = 4,
-	GPIO2A2_MASK            = 3 << GPIO2A2_SHIFT,
-	GPIO2A2_GPIO           = 0,
-	GPIO2A2_FLASH_CSN2,
-
-	GPIO2A1_SHIFT           = 2,
-	GPIO2A1_MASK            = 3 << GPIO2A1_SHIFT,
-	GPIO2A1_GPIO            = 0,
-	GPIO2A1_FLASH_CSN1,
-
-	GPIO2A0_SHIFT           = 0,
-	GPIO2A0_MASK            = 3 << GPIO2A0_SHIFT,
-	GPIO2A0_GPIO            = 0,
-	GPIO2A0_FLASH_CSN0,
-};
-
-/*GRF_GPIO2D_IOMUX*/
-enum {
-	GPIO2D7_SHIFT           = 14,
-	GPIO2D7_MASK            = 3 << GPIO2D7_SHIFT,
-	GPIO2D7_GPIO            = 0,
-	GPIO2D7_SDIO0_D3,
-
-	GPIO2D6_SHIFT           = 12,
-	GPIO2D6_MASK            = 3 << GPIO2D6_SHIFT,
-	GPIO2D6_GPIO            = 0,
-	GPIO2D6_SDIO0_D2,
-
-	GPIO2D5_SHIFT           = 10,
-	GPIO2D5_MASK            = 3 << GPIO2D5_SHIFT,
-	GPIO2D5_GPIO            = 0,
-	GPIO2D5_SDIO0_D1,
-
-	GPIO2D4_SHIFT           = 8,
-	GPIO2D4_MASK            = 3 << GPIO2D4_SHIFT,
-	GPIO2D4_GPIO            = 0,
-	GPIO2D4_SDIO0_D0,
-
-	GPIO2D3_SHIFT           = 6,
-	GPIO2D3_MASK            = 3 << GPIO2D3_SHIFT,
-	GPIO2D3_GPIO            = 0,
-	GPIO2D3_UART0_RTS0,
-
-	GPIO2D2_SHIFT           = 4,
-	GPIO2D2_MASK            = 3 << GPIO2D2_SHIFT,
-	GPIO2D2_GPIO            = 0,
-	GPIO2D2_UART0_CTS0,
-
-	GPIO2D1_SHIFT           = 2,
-	GPIO2D1_MASK            = 3 << GPIO2D1_SHIFT,
-	GPIO2D1_GPIO            = 0,
-	GPIO2D1_UART0_SOUT,
-
-	GPIO2D0_SHIFT           = 0,
-	GPIO2D0_MASK            = 3 << GPIO2D0_SHIFT,
-	GPIO2D0_GPIO            = 0,
-	GPIO2D0_UART0_SIN,
-};
-
-/*GRF_GPIO3C_IOMUX*/
-enum {
-	GPIO3C7_SHIFT           = 14,
-	GPIO3C7_MASK            = 3 << GPIO3C7_SHIFT,
-	GPIO3C7_GPIO            = 0,
-	GPIO3C7_EDPHDMI_CECINOUT,
-	GPIO3C7_ISP_FLASHTRIGIN,
-
-	GPIO3C6_SHIFT           = 12,
-	GPIO3C6_MASK            = 3 << GPIO3C6_SHIFT,
-	GPIO3C6_GPIO            = 0,
-	GPIO3C6_MAC_CLK,
-	GPIO3C6_ISP_SHUTTERTRIG,
-
-	GPIO3C5_SHIFT           = 10,
-	GPIO3C5_MASK            = 3 << GPIO3C5_SHIFT,
-	GPIO3C5_GPIO            = 0,
-	GPIO3C5_MAC_RXER,
-	GPIO3C5_ISP_PRELIGHTTRIG,
-
-	GPIO3C4_SHIFT           = 8,
-	GPIO3C4_MASK            = 3 << GPIO3C4_SHIFT,
-	GPIO3C4_GPIO            = 0,
-	GPIO3C4_MAC_RXDV,
-	GPIO3C4_ISP_FLASHTRIGOUT,
-
-	GPIO3C3_SHIFT           = 6,
-	GPIO3C3_MASK            = 3 << GPIO3C3_SHIFT,
-	GPIO3C3_GPIO            = 0,
-	GPIO3C3_MAC_RXDV,
-	GPIO3C3_EMMC_RSTNO,
-
-	GPIO3C2_SHIFT           = 4,
-	GPIO3C2_MASK            = 3 << GPIO3C2_SHIFT,
-	GPIO3C2_MAC_MDC            = 0,
-	GPIO3C2_ISP_SHUTTEREN,
-
-	GPIO3C1_SHIFT           = 2,
-	GPIO3C1_MASK            = 3 << GPIO3C1_SHIFT,
-	GPIO3C1_GPIO            = 0,
-	GPIO3C1_MAC_RXD2,
-	GPIO3C1_UART3_RTSN,
-
-	GPIO3C0_SHIFT           = 0,
-	GPIO3C0_MASK            = 3 << GPIO3C0_SHIFT,
-	GPIO3C0_GPIO            = 0,
-	GPIO3C0_MAC_RXD1,
-	GPIO3C0_UART3_CTSN,
-	GPIO3C0_GPS_RFCLK,
-};
-
-/*GRF_GPIO3D_IOMUX*/
-enum {
-	GPIO3D7_SHIFT           = 14,
-	GPIO3D7_MASK            = 3 << GPIO3D7_SHIFT,
-	GPIO3D7_GPIO            = 0,
-	GPIO3D7_SC_VCC18V,
-	GPIO3D7_I2C2_SDA,
-	GPIO3D7_GPUJTAG_TCK,
-
-	GPIO3D6_SHIFT           = 12,
-	GPIO3D6_MASK            = 3 << GPIO3D6_SHIFT,
-	GPIO3D6_GPIO            = 0,
-	GPIO3D6_IR_TX,
-	GPIO3D6_UART3_SOUT,
-	GPIO3D6_PWM3,
-
-	GPIO3D5_SHIFT           = 10,
-	GPIO3D5_MASK            = 3 << GPIO3D5_SHIFT,
-	GPIO3D5_GPIO            = 0,
-	GPIO3D5_IR_RX,
-	GPIO3D5_UART3_SIN,
-
-	GPIO3D4_SHIFT           = 8,
-	GPIO3D4_MASK            = 3 << GPIO3D4_SHIFT,
-	GPIO3D4_GPIO            = 0,
-	GPIO3D4_MAC_TXCLKOUT,
-	GPIO3D4_SPI1_CSN1,
-
-	GPIO3D3_SHIFT           = 6,
-	GPIO3D3_MASK            = 3 << GPIO3D3_SHIFT,
-	GPIO3D3_GPIO            = 0,
-	GPIO3D3_HDMII2C_SCL,
-	GPIO3D3_I2C5_SCL,
-
-	GPIO3D2_SHIFT           = 4,
-	GPIO3D2_MASK            = 3 << GPIO3D2_SHIFT,
-	GPIO3D2_GPIO            = 0,
-	GPIO3D2_HDMII2C_SDA,
-	GPIO3D2_I2C5_SDA,
-
-	GPIO3D1_SHIFT           = 2,
-	GPIO3D1_MASK            = 3 << GPIO3D1_SHIFT,
-	GPIO3D1_GPIO            = 0,
-	GPIO3D1_MAC_RXCLKIN,
-	GPIO3D1_I2C4_SCL,
-
-	GPIO3D0_SHIFT           = 0,
-	GPIO3D0_MASK            = 3 << GPIO3D0_SHIFT,
-	GPIO3D0_GPIO            = 0,
-	GPIO3D0_MAC_MDIO,
-	GPIO3D0_I2C4_SDA,
-};
+check_member(rk3368_pmu_grf, gpio0h_sr, 0x34);
+check_member(rk3368_pmu_grf, os_reg[0], 0x200);
 
 /*GRF_SOC_CON11/12/13*/
 enum {
@@ -439,4 +132,5 @@ enum {
 	MCU_CODE_BASE_BIT31_BIT28_SHIFT		= 0,
 	MCU_CODE_BASE_BIT31_BIT28_MASK		= GENMASK(3, 0),
 };
+
 #endif

arch/arm/include/asm/spl.h

@@ -30,6 +30,7 @@ enum {
 	BOOT_DEVICE_BOARD,
 	BOOT_DEVICE_DFU,
 	BOOT_DEVICE_XIP,
+	BOOT_DEVICE_BOOTROM,
 	BOOT_DEVICE_NONE
 };
 #endif

arch/arm/lib/crt0_64.S

@@ -69,7 +69,9 @@ ENTRY(_main)
 /*
  * Set up initial C runtime environment and call board_init_f(0).
  */
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+#if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_NEEDS_SEPARATE_STACK)
+	ldr	x0, =(CONFIG_TPL_STACK)
+#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
 	ldr	x0, =(CONFIG_SPL_STACK)
 #else
 	ldr	x0, =(CONFIG_SYS_INIT_SP_ADDR)

arch/arm/mach-at91/Kconfig

@@ -199,4 +199,8 @@ source "board/siemens/corvus/Kconfig"
 source "board/siemens/taurus/Kconfig"
 source "board/siemens/smartweb/Kconfig"
 
+config SPL_LDSCRIPT
+	default "arch/arm/mach-at91/arm926ejs/u-boot-spl.lds" if CPU_ARM926EJS
+	default "arch/arm/mach-at91/armv7/u-boot-spl.lds" if CPU_V7
+
 endif

arch/arm/mach-davinci/Kconfig

@@ -53,4 +53,8 @@ source "board/davinci/ea20/Kconfig"
 source "board/omicron/calimain/Kconfig"
 source "board/lego/ev3/Kconfig"
 
+config SPL_LDSCRIPT
+	default "board/$(BOARDDIR)/u-boot-spl-ipam390.lds" if TARGET_IPAM390
+	default "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
+
 endif

arch/arm/mach-exynos/Kconfig

@@ -161,4 +161,7 @@ source "board/samsung/smdk5250/Kconfig"
 source "board/samsung/smdk5420/Kconfig"
 source "board/samsung/espresso7420/Kconfig"
 
+config SPL_LDSCRIPT
+	default "board/samsung/common/exynos-uboot-spl.lds" if ARCH_EXYNOS5 || ARCH_EXYNOS4
+
 endif

arch/arm/mach-omap2/Kconfig

@@ -170,4 +170,7 @@ source "board/ti/am335x/Kconfig"
 source "board/compulab/cm_t335/Kconfig"
 source "board/compulab/cm_t43/Kconfig"
 
+config SPL_LDSCRIPT
+        default "arch/arm/mach-omap2/u-boot-spl.lds"
+
 endif

arch/arm/mach-orion5x/Kconfig

@@ -15,4 +15,7 @@ config SYS_SOC
 
 source "board/LaCie/edminiv2/Kconfig"
 
+config SPL_LDSCRIPT
+	default "$(CPUDIR)/orion5x/u-boot-spl.lds" if ORION5X
+
 endif

arch/arm/mach-rockchip/Kconfig

@@ -67,14 +67,42 @@ config ROCKCHIP_RK3328
 config ROCKCHIP_RK3368
 	bool "Support Rockchip RK3368"
 	select ARM64
+	select SUPPORT_SPL
+	select SUPPORT_TPL
+	select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
+	select TPL_NEEDS_SEPARATE_STACK if TPL
+	imply SPL_SEPARATE_BSS
+	imply SPL_SERIAL_SUPPORT
+	imply TPL_SERIAL_SUPPORT
+	select ENABLE_ARM_SOC_BOOT0_HOOK
+	select DEBUG_UART_BOARD_INIT
 	select SYS_NS16550
 	help
-	  The Rockchip RK3328 is a ARM-based SoC with a octa-core Cortex-A53.
-	  including NEON and GPU, 512KB L2 cache for big cluster and 256 KB
-	  L2 cache for little cluser, PowerVR G6110 based graphics, one video
-	  output processor supporting LVDS、HDMI、eDP, several DDR3 options
-	  and video codec support. Peripherals include Gigabit Ethernet,
-	  USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
+	  The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
+	  into a big and little cluster with 4 cores each) Cortex-A53 including
+	  AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
+	  (for the little cluster), PowerVR G6110 based graphics, one video
+	  output processor supporting LVDS/HDMI/eDP, several DDR3 options and
+	  video codec support.
+
+	  On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
+	  I2S, UARTs, SPI, I2C and PWMs.
+
+if ROCKCHIP_RK3368
+
+config TPL_LDSCRIPT
+	default "arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds"
+
+config TPL_TEXT_BASE
+        default 0xff8c1000
+
+config TPL_MAX_SIZE
+        default 28672
+
+config TPL_STACK
+        default 0xff8cffff
+
+endif
 
 config ROCKCHIP_RK3399
 	bool "Support Rockchip RK3399"
@@ -101,10 +129,21 @@ config ROCKCHIP_RV1108
 	  The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
 	  and a DSP.
 
-config ROCKCHIP_SPL_BACK_TO_BROM
+config SPL_ROCKCHIP_BACK_TO_BROM
 	bool "SPL returns to bootrom"
 	default y if ROCKCHIP_RK3036
 	select ROCKCHIP_BROM_HELPER
+	depends on SPL
+	help
+	  Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
+          SPL will return to the boot rom, which will then load the U-Boot
+          binary to keep going on.
+
+config TPL_ROCKCHIP_BACK_TO_BROM
+	bool "TPL returns to bootrom"
+	default y if ROCKCHIP_RK3368
+	select ROCKCHIP_BROM_HELPER
+	depends on TPL
 	help
 	  Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
           SPL will return to the boot rom, which will then load the U-Boot
@@ -122,7 +161,7 @@ config ROCKCHIP_BROM_HELPER
 	bool
 
 config SPL_MMC_SUPPORT
-	default y if !ROCKCHIP_SPL_BACK_TO_BROM
+	default y if !SPL_ROCKCHIP_BACK_TO_BROM
 
 source "arch/arm/mach-rockchip/rk3036/Kconfig"
 source "arch/arm/mach-rockchip/rk3188/Kconfig"

arch/arm/mach-rockchip/Makefile

@@ -4,39 +4,50 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
+# We don't want the bootrom-helper present in a full U-Boot build, as
+# this may have entered from ATF with the stack-pointer pointing to
+# inaccessible/protected memory (and the bootrom-helper assumes that
+# the stack-pointer is valid before switching to the U-Boot stack).
+obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o
+obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o
 
-ifdef CONFIG_TPL_BUILD
-obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o
-obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o
-else ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
-obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
-obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o
-obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
-obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o
-obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o
-else
+obj-tpl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o
+obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o
+
+obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
+obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
+obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o
+obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
+obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o
+obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o
+
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
 obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
 obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
 obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
-ifdef CONFIG_RAM
-obj-y += sdram_common.o
-endif
 endif
+
+obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o
+
 ifndef CONFIG_ARM64
 obj-y += rk_timer.o
 endif
-obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
 
+obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
 ifndef CONFIG_TPL_BUILD
 obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
 endif
-
 obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x/
 obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
 obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
 obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
 obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
 obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/
+
+# Clear out SPL objects, in case this is a TPL build
+obj-spl-$(CONFIG_TPL_BUILD) =
+
+# Now add SPL/TPL objects back into the main build
+obj-$(CONFIG_SPL_BUILD) += $(obj-spl-y)
+obj-$(CONFIG_TPL_BUILD) += $(obj-tpl-y)

arch/arm/mach-rockchip/bootrom.c

@@ -9,8 +9,8 @@
 
 void back_to_bootrom(void)
 {
-#if defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && !defined(CONFIG_TPL_BUILD)
-	puts("Returning to boot ROM...");
+#if CONFIG_IS_ENABLED(LIBCOMMON_SUPPORT)
+	puts("Returning to boot ROM...\n");
 #endif
 	_back_to_bootrom_s();
 }

arch/arm/mach-rockchip/rk3188-board-spl.c

@@ -167,8 +167,7 @@ void board_init_f(ulong dummy)
 	}
 
 	setup_arm_clock();
-
-#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
 	back_to_bootrom();
 #endif
 }
@@ -229,7 +228,7 @@ void spl_board_init(void)
 	}
 
 	preloader_console_init();
-#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
 	back_to_bootrom();
 #endif
 	return;

arch/arm/mach-rockchip/rk3188-board.c

@@ -39,7 +39,7 @@ int board_late_init(void)
 
 int board_init(void)
 {
-#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM)
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
 	struct udevice *pinctrl;
 	int ret;
 

arch/arm/mach-rockchip/rk3188/Kconfig

@@ -30,9 +30,6 @@ config TPL_LIBCOMMON_SUPPORT
 config TPL_LIBGENERIC_SUPPORT
 	default y
 
-config TPL_SERIAL_SUPPORT
-	default y
-
 source "board/radxa/rock/Kconfig"
 
 endif

arch/arm/mach-rockchip/rk322x-board-spl.c

@@ -41,6 +41,8 @@ static struct rk322x_grf * const grf = (void *)GRF_BASE;
 		     CON_IOMUX_UART2SEL_MASK,
 		     CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
 }
+
+#define SGRF_DDR_CON0 0x10150000
 void board_init_f(ulong dummy)
 {
 	struct udevice *dev;
@@ -71,6 +73,8 @@ void board_init_f(ulong dummy)
 		return;
 	}
 
+	/* Disable the ddr secure region setting to make it non-secure */
+	rk_clrreg(SGRF_DDR_CON0, 0x4000);
 #if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
 	back_to_bootrom();
 #endif

arch/arm/mach-rockchip/rk3288-board-spl.c

@@ -249,7 +249,7 @@ void board_init_f(ulong dummy)
 		debug("DRAM init failed: %d\n", ret);
 		return;
 	}
-#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
 	back_to_bootrom();
 #endif
 }
@@ -316,7 +316,7 @@ void spl_board_init(void)
 	}
 
 	preloader_console_init();
-#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
 	back_to_bootrom();
 #endif
 	return;

arch/arm/mach-rockchip/rk3288-board.c

@@ -78,7 +78,7 @@ int board_late_init(void)
 	return rk_board_late_init();
 }
 
-#ifndef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
 static int veyron_init(void)
 {
 	struct udevice *dev;
@@ -115,7 +115,7 @@ static int veyron_init(void)
 
 int board_init(void)
 {
-#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
 	struct udevice *pinctrl;
 	int ret;
 

arch/arm/mach-rockchip/rk3368-board-spl.c

@@ -0,0 +1,78 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <ram.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/cru_rk3368.h>
+#include <asm/arch/grf_rk3368.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/timer.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_debug_uart_init(void)
+{
+}
+
+void board_init_f(ulong dummy)
+{
+	struct udevice *pinctrl;
+	struct udevice *dev;
+	int ret;
+
+	ret = spl_early_init();
+	if (ret) {
+		debug("spl_early_init() failed: %d\n", ret);
+		hang();
+	}
+
+	/* Set up our preloader console */
+	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
+	if (ret) {
+		error("%s: pinctrl init failed: %d\n", __func__, ret);
+		hang();
+	}
+
+	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART0);
+	if (ret) {
+		error("%s: failed to set up console UART\n", __func__);
+		hang();
+	}
+
+	preloader_console_init();
+
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret) {
+		debug("DRAM init failed: %d\n", ret);
+		return;
+	}
+}
+
+u32 spl_boot_mode(const u32 boot_device)
+{
+	return MMCSD_MODE_RAW;
+}
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_MMC1;
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif

arch/arm/mach-rockchip/rk3368-board-tpl.c

@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <ram.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/bootrom.h>
+#include <asm/arch/cru_rk3368.h>
+#include <asm/arch/grf_rk3368.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/timer.h>
+#include <syscon.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * The SPL (and also the full U-Boot stage on the RK3368) will run in
+ * secure mode (i.e. EL3) and an ATF will eventually be booted before
+ * starting up the operating system... so we can initialize the SGRF
+ * here and rely on the ATF installing the final (secure) policy
+ * later.
+ */
+static inline uintptr_t sgrf_soc_con_addr(unsigned no)
+{
+	const uintptr_t SGRF_BASE =
+		(uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
+
+	return SGRF_BASE + sizeof(u32) * no;
+}
+
+static inline uintptr_t sgrf_busdmac_addr(unsigned no)
+{
+	const uintptr_t SGRF_BASE =
+		(uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
+	const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100;
+	const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET;
+
+	return SGRF_BUSDMAC_BASE + sizeof(u32) * no;
+}
+
+static void sgrf_init(void)
+{
+	struct rk3368_cru * const cru =
+		(struct rk3368_cru * const)rockchip_get_cru();
+	const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0);
+	const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2);
+	const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12);
+
+	/* Set all configurable IP to 'non secure'-mode */
+	rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC);
+	rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC);
+	rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC);
+
+	/*
+	 * From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c
+	 * Original comment: "ddr space set no secure mode"
+	 */
+	rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC);
+	rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC);
+	rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC);
+
+	/* Set 'secure dma' to 'non secure'-mode */
+	rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC);
+	rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC);
+
+	dsb();  /* barrier */
+
+	rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ);
+	rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ);
+
+	dsb();  /* barrier */
+	udelay(10);
+
+	rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ);
+	rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ);
+}
+
+void board_debug_uart_init(void)
+{
+	/*
+	 * N.B.: This is called before the device-model has been
+	 *       initialised. For this reason, we can not access
+	 *       the GRF address range using the syscon API.
+	 */
+	struct rk3368_grf * const grf =
+		(struct rk3368_grf * const)0xff770000;
+
+	enum {
+		GPIO2D1_MASK            = GENMASK(3, 2),
+		GPIO2D1_GPIO            = 0,
+		GPIO2D1_UART0_SOUT      = (1 << 2),
+
+		GPIO2D0_MASK            = GENMASK(1, 0),
+		GPIO2D0_GPIO            = 0,
+		GPIO2D0_UART0_SIN       = (1 << 0),
+	};
+
+#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
+	/* Enable early UART0 on the RK3368 */
+	rk_clrsetreg(&grf->gpio2d_iomux,
+		     GPIO2D0_MASK, GPIO2D0_UART0_SIN);
+	rk_clrsetreg(&grf->gpio2d_iomux,
+		     GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
+#endif
+}
+
+void board_init_f(ulong dummy)
+{
+	struct udevice *dev;
+	int ret;
+
+#define EARLY_UART
+#ifdef EARLY_UART
+	/*
+	 * Debug UART can be used from here if required:
+	 *
+	 * debug_uart_init();
+	 * printch('a');
+	 * printhex8(0x1234);
+	 * printascii("string");
+	 */
+	debug_uart_init();
+	printascii("U-Boot TPL board init\n");
+#endif
+
+	ret = spl_early_init();
+	if (ret) {
+		debug("spl_early_init() failed: %d\n", ret);
+		hang();
+	}
+
+	/* Reset security, so we can use DMA in the MMC drivers */
+	sgrf_init();
+
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret) {
+		debug("DRAM init failed: %d\n", ret);
+		return;
+	}
+}
+
+void board_return_to_bootrom(void)
+{
+	back_to_bootrom();
+}
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_BOOTROM;
+}

arch/arm/mach-rockchip/rk3368/Kconfig

@@ -3,6 +3,26 @@ if ROCKCHIP_RK3368
 choice
 	prompt "RK3368 board"
 
+config TARGET_LION_RK3368
+        bool "Theobroma Systems RK3368-uQ7 (Lion) module"
+	help
+	  The RK3368-uQ7 is a micro-Qseven form-factor (40mm x 70mm,
+	  MXM-230 connector) system-on-module designed by Theobroma
+	  Systems for industrial applications.
+
+	  It provides the following features:
+	   - 8x Cortex-A53 (in 2 clusters of 4 cores each)
+	   - (on-module) up to 4GB of DDR3 memory
+	   - (on-module) SPI-NOR flash
+	   - (on-module) eMMC
+	   - Gigabit Ethernet (with an on-module KSZ9031 PHY)
+	   - USB
+	   - HDMI
+	   - MIPI-DSI/single-channel LVDS (muxed on the 'LVDS-A' pin-group)
+	   - various 'slow' interfaces (e.g. UART, SPI, I2C, I2S, ...)
+	   - on-module STM32 providing CAN, RTC and fan-control
+	   - (optional on-module) EAL4+-certified security module
+
 config TARGET_SHEEP
 	bool "Sheep board"
 	help
@@ -25,8 +45,12 @@ endchoice
 config SYS_SOC
 	default "rockchip"
 
+source "board/theobroma-systems/lion_rk3368/Kconfig"
 source "board/rockchip/sheep_rk3368/Kconfig"
 source "board/geekbuying/geekbox/Kconfig"
 source "board/rockchip/evb_px5/Kconfig"
 
+config SPL_LDSCRIPT
+	default "arch/arm/cpu/armv8/u-boot-spl.lds"
+
 endif

arch/arm/mach-rockchip/rk3368/Makefile

@@ -5,5 +5,4 @@
 #
 obj-y		+= clk_rk3368.o
 obj-y		+= rk3368.o
-obj-y 		+= sdram_rk3368.o
 obj-y 		+= syscon_rk3368.o

arch/arm/mach-rockchip/rk3368/sdram_rk3368.c

@@ -1,60 +0,0 @@
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd.
- *
- * SPDX-License-Identifier:     GPL-2.0
- */
-
-#include <common.h>
-#include <dm.h>
-#include <ram.h>
-#include <syscon.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/grf_rk3368.h>
-#include <asm/arch/sdram_common.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-struct dram_info {
-	struct ram_info info;
-	struct rk3368_pmu_grf *pmugrf;
-};
-
-static int rk3368_dmc_probe(struct udevice *dev)
-{
-	struct dram_info *priv = dev_get_priv(dev);
-
-	priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
-	debug("%s: grf=%p\n", __func__, priv->pmugrf);
-	priv->info.base = CONFIG_SYS_SDRAM_BASE;
-	priv->info.size = rockchip_sdram_size(
-			(phys_addr_t)&priv->pmugrf->os_reg[2]);
-
-	return 0;
-}
-
-static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info)
-{
-	struct dram_info *priv = dev_get_priv(dev);
-
-	*info = priv->info;
-
-	return 0;
-}
-
-static struct ram_ops rk3368_dmc_ops = {
-	.get_info = rk3368_dmc_get_info,
-};
-
-
-static const struct udevice_id rk3368_dmc_ids[] = {
-	{ .compatible = "rockchip,rk3368-dmc" },
-	{ }
-};
-
-U_BOOT_DRIVER(dmc_rk3368) = {
-	.name = "rockchip_rk3368_dmc",
-	.id = UCLASS_RAM,
-	.of_match = rk3368_dmc_ids,
-	.ops = &rk3368_dmc_ops,
-	.probe = rk3368_dmc_probe,
-	.priv_auto_alloc_size = sizeof(struct dram_info),
-};

arch/arm/mach-rockchip/rk3368/syscon_rk3368.c

@@ -1,6 +1,8 @@
 /*
  * (C) Copyright 2017 Rockchip Electronics Co., Ltd
  * Author: Andy Yan <andy.yan@rock-chips.com>
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
@@ -14,6 +16,10 @@ static const struct udevice_id rk3368_syscon_ids[] = {
 	  .data = ROCKCHIP_SYSCON_GRF },
 	{ .compatible = "rockchip,rk3368-pmugrf",
 	  .data = ROCKCHIP_SYSCON_PMUGRF },
+	{ .compatible = "rockchip,rk3368-msch",
+	  .data = ROCKCHIP_SYSCON_MSCH },
+	{ .compatible = "rockchip,rk3368-sgrf",
+	  .data = ROCKCHIP_SYSCON_SGRF },
 	{ }
 };
 
@@ -22,3 +28,41 @@ U_BOOT_DRIVER(syscon_rk3368) = {
 	.id = UCLASS_SYSCON,
 	.of_match = rk3368_syscon_ids,
 };
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+static int rk3368_syscon_bind_of_platdata(struct udevice *dev)
+{
+	dev->driver_data = dev->driver->of_match->data;
+	debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
+
+	return 0;
+}
+
+U_BOOT_DRIVER(rockchip_rk3368_grf) = {
+	.name = "rockchip_rk3368_grf",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3368_syscon_ids,
+	.bind = rk3368_syscon_bind_of_platdata,
+};
+
+U_BOOT_DRIVER(rockchip_rk3368_pmugrf) = {
+	.name = "rockchip_rk3368_pmugrf",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3368_syscon_ids + 1,
+	.bind = rk3368_syscon_bind_of_platdata,
+};
+
+U_BOOT_DRIVER(rockchip_rk3368_msch) = {
+	.name = "rockchip_rk3368_msch",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3368_syscon_ids + 2,
+	.bind = rk3368_syscon_bind_of_platdata,
+};
+
+U_BOOT_DRIVER(rockchip_rk3368_sgrf) = {
+	.name = "rockchip_rk3368_sgrf",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3368_syscon_ids + 3,
+	.bind = rk3368_syscon_bind_of_platdata,
+};
+#endif

arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds

@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#undef CONFIG_SPL_TEXT_BASE
+#define CONFIG_SPL_TEXT_BASE CONFIG_TPL_TEXT_BASE
+
+#undef CONFIG_SPL_MAX_SIZE
+#define CONFIG_SPL_MAX_SIZE CONFIG_TPL_MAX_SIZE
+
+#include "../../cpu/armv8/u-boot-spl.lds"

arch/arm/mach-rockchip/rk3399-board-spl.c

@@ -8,9 +8,6 @@
 #include <debug_uart.h>
 #include <dm.h>
 #include <fdtdec.h>
-#include <led.h>
-#include <malloc.h>
-#include <mmc.h>
 #include <ram.h>
 #include <spl.h>
 #include <asm/gpio.h>
@@ -21,111 +18,10 @@
 #include <asm/arch/sdram.h>
 #include <asm/arch/timer.h>
 #include <dm/pinctrl.h>
-#include <dm/root.h>
-#include <dm/test.h>
-#include <dm/util.h>
 #include <power/regulator.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OF_CONTROL)
-static int spl_node_to_boot_device(int node)
-{
-	struct udevice *parent;
-
-	/*
-	 * This should eventually move into the SPL code, once SPL becomes
-	 * aware of the block-device layer.  Until then (and to avoid unneeded
-	 * delays in getting this feature out, it lives at the board-level).
-	 */
-	if (!uclass_get_device_by_of_offset(UCLASS_MMC, node, &parent)) {
-		struct udevice *dev;
-		struct blk_desc *desc = NULL;
-
-		for (device_find_first_child(parent, &dev);
-		     dev;
-		     device_find_next_child(&dev)) {
-			if (device_get_uclass_id(dev) == UCLASS_BLK) {
-				desc = dev_get_uclass_platdata(dev);
-				break;
-			}
-		}
-
-		if (!desc)
-			return -ENOENT;
-
-		switch (desc->devnum) {
-		case 0:
-			return BOOT_DEVICE_MMC1;
-		case 1:
-			return BOOT_DEVICE_MMC2;
-		default:
-			return -ENOSYS;
-		}
-	}
-
-	/*
-	 * SPL doesn't differentiate SPI flashes, so we keep the detection
-	 * brief and inaccurate... hopefully, the common SPL layer can be
-	 * extended with awareness of the BLK layer (and matching OF_CONTROL)
-	 * soon.
-	 */
-	if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent))
-		return BOOT_DEVICE_SPI;
-
-	return -1;
-}
-
-void board_boot_order(u32 *spl_boot_list)
-{
-	const void *blob = gd->fdt_blob;
-	int chosen_node = fdt_path_offset(blob, "/chosen");
-	int idx = 0;
-	int elem;
-	int boot_device;
-	int node;
-	const char *conf;
-
-	if (chosen_node < 0) {
-		debug("%s: /chosen not found, using spl_boot_device()\n",
-		      __func__);
-		spl_boot_list[0] = spl_boot_device();
-		return;
-	}
-
-	for (elem = 0;
-	     (conf = fdt_stringlist_get(blob, chosen_node,
-					"u-boot,spl-boot-order", elem, NULL));
-	     elem++) {
-		/* First check if the list element is an alias */
-		const char *alias = fdt_get_alias(blob, conf);
-		if (alias)
-			conf = alias;
-
-		/* Try to resolve the config item (or alias) as a path */
-		node = fdt_path_offset(blob, conf);
-		if (node < 0) {
-			debug("%s: could not find %s in FDT", __func__, conf);
-			continue;
-		}
-
-		/* Try to map this back onto SPL boot devices */
-		boot_device = spl_node_to_boot_device(node);
-		if (boot_device < 0) {
-			debug("%s: could not map node @%x to a boot-device\n",
-			      __func__, node);
-			continue;
-		}
-
-		spl_boot_list[idx++] = boot_device;
-	}
-
-	/* If we had no matches, fall back to spl_boot_device */
-	if (idx == 0)
-		spl_boot_list[0] = spl_boot_device();
-}
-#endif
-
 u32 spl_boot_device(void)
 {
 	return BOOT_DEVICE_MMC1;
@@ -263,7 +159,7 @@ void spl_board_init(void)
 	}
 
 	preloader_console_init();
-#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
 	back_to_bootrom();
 #endif
 

arch/arm/mach-rockchip/save_boot_param.S

@@ -1,11 +1,47 @@
 /*
  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
  *
  * SPDX-License-Identifier:     GPL-2.0+
  */
 
 #include <linux/linkage.h>
 
+#if defined(CONFIG_ARM64)
+.globl	SAVE_SP_ADDR
+SAVE_SP_ADDR:
+	.quad 0
+
+ENTRY(save_boot_params)
+	sub	sp, sp, #0x60
+	stp	x29, x30, [sp, #0x50]
+	stp	x27, x28, [sp, #0x40]
+	stp	x25, x26, [sp, #0x30]
+	stp	x23, x24, [sp, #0x20]
+	stp	x21, x22, [sp, #0x10]
+	stp	x19, x20, [sp, #0]
+	ldr	x8, =SAVE_SP_ADDR
+	mov	x9, sp
+	str	x9, [x8]
+	b	save_boot_params_ret  /* back to my caller */
+ENDPROC(save_boot_params)
+
+.globl _back_to_bootrom_s
+ENTRY(_back_to_bootrom_s)
+	ldr	x0, =SAVE_SP_ADDR
+	ldr	x0, [x0]
+	mov	sp, x0
+	ldp	x29, x30, [sp, #0x50]
+	ldp	x27, x28, [sp, #0x40]
+	ldp	x25, x26, [sp, #0x30]
+	ldp	x23, x24, [sp, #0x20]
+	ldp	x21, x22, [sp, #0x10]
+	ldp	x19, x20, [sp]
+	add	sp, sp, #0x60
+	mov	x0, xzr
+	ret
+ENDPROC(_back_to_bootrom_s)
+#else
 .globl	SAVE_SP_ADDR
 SAVE_SP_ADDR:
 	.word 0
@@ -30,3 +66,4 @@ ENTRY(_back_to_bootrom_s)
 	mov	r0, #0
 	pop	{r1-r12, pc}
 ENDPROC(_back_to_bootrom_s)
+#endif

arch/arm/mach-rockchip/spl-boot-order.c

@@ -0,0 +1,108 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <mmc.h>
+#include <spl.h>
+
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+static int spl_node_to_boot_device(int node)
+{
+	struct udevice *parent;
+
+	/*
+	 * This should eventually move into the SPL code, once SPL becomes
+	 * aware of the block-device layer.  Until then (and to avoid unneeded
+	 * delays in getting this feature out, it lives at the board-level).
+	 */
+	if (!uclass_get_device_by_of_offset(UCLASS_MMC, node, &parent)) {
+		struct udevice *dev;
+		struct blk_desc *desc = NULL;
+
+		for (device_find_first_child(parent, &dev);
+		     dev;
+		     device_find_next_child(&dev)) {
+			if (device_get_uclass_id(dev) == UCLASS_BLK) {
+				desc = dev_get_uclass_platdata(dev);
+				break;
+			}
+		}
+
+		if (!desc)
+			return -ENOENT;
+
+		switch (desc->devnum) {
+		case 0:
+			return BOOT_DEVICE_MMC1;
+		case 1:
+			return BOOT_DEVICE_MMC2;
+		default:
+			return -ENOSYS;
+		}
+	}
+
+	/*
+	 * SPL doesn't differentiate SPI flashes, so we keep the detection
+	 * brief and inaccurate... hopefully, the common SPL layer can be
+	 * extended with awareness of the BLK layer (and matching OF_CONTROL)
+	 * soon.
+	 */
+	if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent))
+		return BOOT_DEVICE_SPI;
+
+	return -1;
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	const void *blob = gd->fdt_blob;
+	int chosen_node = fdt_path_offset(blob, "/chosen");
+	int idx = 0;
+	int elem;
+	int boot_device;
+	int node;
+	const char *conf;
+
+	if (chosen_node < 0) {
+		debug("%s: /chosen not found, using spl_boot_device()\n",
+		      __func__);
+		spl_boot_list[0] = spl_boot_device();
+		return;
+	}
+
+	for (elem = 0;
+	     (conf = fdt_stringlist_get(blob, chosen_node,
+					"u-boot,spl-boot-order", elem, NULL));
+	     elem++) {
+		/* First check if the list element is an alias */
+		const char *alias = fdt_get_alias(blob, conf);
+		if (alias)
+			conf = alias;
+
+		/* Try to resolve the config item (or alias) as a path */
+		node = fdt_path_offset(blob, conf);
+		if (node < 0) {
+			debug("%s: could not find %s in FDT", __func__, conf);
+			continue;
+		}
+
+		/* Try to map this back onto SPL boot devices */
+		boot_device = spl_node_to_boot_device(node);
+		if (boot_device < 0) {
+			debug("%s: could not map node @%x to a boot-device\n",
+			      __func__, node);
+			continue;
+		}
+
+		spl_boot_list[idx++] = boot_device;
+	}
+
+	/* If we had no matches, fall back to spl_boot_device */
+	if (idx == 0)
+		spl_boot_list[0] = spl_boot_device();
+}
+#endif

arch/arm/mach-sunxi/Kconfig

@@ -1,5 +1,8 @@
 if ARCH_SUNXI
 
+config SPL_LDSCRIPT
+	default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
+
 config IDENT_STRING
 	default " Allwinner Technology"
 

arch/arm/mach-zynq/Kconfig

@@ -1,5 +1,8 @@
 if ARCH_ZYNQ
 
+config SPL_LDSCRIPT
+	default "arch/arm/mach-zynq/u-boot-spl.lds"
+
 config SPL_FAT_SUPPORT
 	default y