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imx8mp_evk: Update LPDDR4 timing for new FW 202006

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After switching to new LPDDR4 firmware 202006 version, have to
update the LPDDR4 timing accordingly from RPA tool.

Signed-off-by: Ye Li <ye.li@nxp.com>
Tested-by: Sherry Sun <sherry.sun@nxp.com>
Tested-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Ye Li
2021-03-19 15:57:00 +08:00
committed by Stefano Babic
parent 31c878f76e
commit c0c78d24bd
1 changed files with 99 additions and 90 deletions
Download Patch File Download Diff File Expand all files Collapse all files

189
board/freescale/imx8mp_evk/lpddr4_timing.c
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@@ -15,14 +15,17 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d400024, 0x1e84800 }, { 0x3d400024, 0x1e84800 },
{ 0x3d400064, 0x7a0118 }, { 0x3d400064, 0x7a0118 },
#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC #ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
{ 0x3d400070, 0x01027f44 }, { 0x3d400070, 0x1027f54 },
#else
{ 0x3d400070, 0x1027f10 },
#endif #endif
{ 0x3d400074, 0x7b0 },
{ 0x3d4000d0, 0xc00307a3 }, { 0x3d4000d0, 0xc00307a3 },
{ 0x3d4000d4, 0xc50000 }, { 0x3d4000d4, 0xc50000 },
{ 0x3d4000dc, 0xf4003f }, { 0x3d4000dc, 0xf4003f },
{ 0x3d4000e0, 0x330000 }, { 0x3d4000e0, 0x330000 },
{ 0x3d4000e8, 0x460048 }, { 0x3d4000e8, 0x660048 },
{ 0x3d4000ec, 0x150048 }, { 0x3d4000ec, 0x160048 },
{ 0x3d400100, 0x2028222a }, { 0x3d400100, 0x2028222a },
{ 0x3d400104, 0x807bf }, { 0x3d400104, 0x807bf },
{ 0x3d40010c, 0xe0e000 }, { 0x3d40010c, 0xe0e000 },
@@ -64,26 +67,26 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d400218, 0x68070707 }, { 0x3d400218, 0x68070707 },
#endif #endif
{ 0x3d40021c, 0xf08 }, { 0x3d40021c, 0xf08 },
{ 0x3d400250, 0x00001705 }, { 0x3d400250, 0x1705 },
{ 0x3d400254, 0x2c }, { 0x3d400254, 0x2c },
{ 0x3d40025c, 0x4000030 }, { 0x3d40025c, 0x4000030 },
{ 0x3d400264, 0x900093e7 }, { 0x3d400264, 0x900093e7 },
{ 0x3d40026c, 0x2005574 }, { 0x3d40026c, 0x2005574 },
{ 0x3d400400, 0x111 }, { 0x3d400400, 0x111 },
{ 0x3d400404, 0x72ff }, { 0x3d400404, 0x72ff },
{ 0x3d400408, 0x72ff }, { 0x3d400408, 0x72ff },
{ 0x3d400494, 0x2100e07 }, { 0x3d400494, 0x2100e07 },
{ 0x3d400498, 0x620096 }, { 0x3d400498, 0x620096 },
{ 0x3d40049c, 0x1100e07 }, { 0x3d40049c, 0x1100e07 },
{ 0x3d4004a0, 0xc8012c }, { 0x3d4004a0, 0xc8012c },
{ 0x3d402020, 0x21 }, { 0x3d402020, 0x1021 },
{ 0x3d402024, 0x7d00 }, { 0x3d402024, 0x30d400 },
{ 0x3d402050, 0x20d040 }, { 0x3d402050, 0x20d000 },
{ 0x3d402064, 0xc001c }, { 0x3d402064, 0xc001c },
{ 0x3d4020dc, 0x840000 }, { 0x3d4020dc, 0x840000 },
{ 0x3d4020e0, 0x310000 }, { 0x3d4020e0, 0x330000 },
{ 0x3d4020e8, 0x66004d }, { 0x3d4020e8, 0x660048 },
{ 0x3d4020ec, 0x16004d }, { 0x3d4020ec, 0x160048 },
{ 0x3d402100, 0xa040305 }, { 0x3d402100, 0xa040305 },
{ 0x3d402104, 0x30407 }, { 0x3d402104, 0x30407 },
{ 0x3d402108, 0x203060b }, { 0x3d402108, 0x203060b },
@@ -101,14 +104,14 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d402194, 0x80303 }, { 0x3d402194, 0x80303 },
{ 0x3d4021b4, 0x100 }, { 0x3d4021b4, 0x100 },
{ 0x3d4020f4, 0xc99 }, { 0x3d4020f4, 0xc99 },
{ 0x3d403020, 0x21 }, { 0x3d403020, 0x1021 },
{ 0x3d403024, 0x30d400 }, { 0x3d403024, 0xc3500 },
{ 0x3d403050, 0x20d040 }, { 0x3d403050, 0x20d000 },
{ 0x3d403064, 0x30007 }, { 0x3d403064, 0x30007 },
{ 0x3d4030dc, 0x840000 }, { 0x3d4030dc, 0x840000 },
{ 0x3d4030e0, 0x310000 }, { 0x3d4030e0, 0x330000 },
{ 0x3d4030e8, 0x66004d }, { 0x3d4030e8, 0x660048 },
{ 0x3d4030ec, 0x16004d }, { 0x3d4030ec, 0x160048 },
{ 0x3d403100, 0xa010102 }, { 0x3d403100, 0xa010102 },
{ 0x3d403104, 0x30404 }, { 0x3d403104, 0x30404 },
{ 0x3d403108, 0x203060b }, { 0x3d403108, 0x203060b },
@@ -125,6 +128,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d403190, 0x3818200 }, { 0x3d403190, 0x3818200 },
{ 0x3d403194, 0x80303 }, { 0x3d403194, 0x80303 },
{ 0x3d4031b4, 0x100 }, { 0x3d4031b4, 0x100 },
{ 0x3d4030f4, 0xc99 },
{ 0x3d400028, 0x0 }, { 0x3d400028, 0x0 },
}; };
@@ -1114,28 +1118,28 @@ struct dram_cfg_param ddr_fsp1_cfg[] = {
{ 0x54012, 0x310 }, { 0x54012, 0x310 },
{ 0x54019, 0x84 }, { 0x54019, 0x84 },
{ 0x5401a, 0x33 }, { 0x5401a, 0x33 },
{ 0x5401b, 0x4846 }, { 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 }, { 0x5401c, 0x4800 },
{ 0x5401e, 0x15 }, { 0x5401e, 0x16 },
{ 0x5401f, 0x84 }, { 0x5401f, 0x84 },
{ 0x54020, 0x33 }, { 0x54020, 0x33 },
{ 0x54021, 0x4846 }, { 0x54021, 0x4866 },
{ 0x54022, 0x4800 }, { 0x54022, 0x4800 },
{ 0x54024, 0x15 }, { 0x54024, 0x16 },
{ 0x5402b, 0x1000 }, { 0x5402b, 0x1000 },
{ 0x5402c, 0x3 }, { 0x5402c, 0x3 },
{ 0x54032, 0x8400 }, { 0x54032, 0x8400 },
{ 0x54033, 0x3300 }, { 0x54033, 0x3300 },
{ 0x54034, 0x4600 }, { 0x54034, 0x6600 },
{ 0x54035, 0x48 }, { 0x54035, 0x48 },
{ 0x54036, 0x48 }, { 0x54036, 0x48 },
{ 0x54037, 0x1500 }, { 0x54037, 0x1600 },
{ 0x54038, 0x8400 }, { 0x54038, 0x8400 },
{ 0x54039, 0x3300 }, { 0x54039, 0x3300 },
{ 0x5403a, 0x4600 }, { 0x5403a, 0x6600 },
{ 0x5403b, 0x48 }, { 0x5403b, 0x48 },
{ 0x5403c, 0x48 }, { 0x5403c, 0x48 },
{ 0x5403d, 0x1500 }, { 0x5403d, 0x1600 },
{ 0xd0000, 0x1 }, { 0xd0000, 0x1 },
}; };
@@ -1154,28 +1158,28 @@ struct dram_cfg_param ddr_fsp2_cfg[] = {
{ 0x54012, 0x310 }, { 0x54012, 0x310 },
{ 0x54019, 0x84 }, { 0x54019, 0x84 },
{ 0x5401a, 0x33 }, { 0x5401a, 0x33 },
{ 0x5401b, 0x4846 }, { 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 }, { 0x5401c, 0x4800 },
{ 0x5401e, 0x15 }, { 0x5401e, 0x16 },
{ 0x5401f, 0x84 }, { 0x5401f, 0x84 },
{ 0x54020, 0x33 }, { 0x54020, 0x33 },
{ 0x54021, 0x4846 }, { 0x54021, 0x4866 },
{ 0x54022, 0x4800 }, { 0x54022, 0x4800 },
{ 0x54024, 0x15 }, { 0x54024, 0x16 },
{ 0x5402b, 0x1000 }, { 0x5402b, 0x1000 },
{ 0x5402c, 0x3 }, { 0x5402c, 0x3 },
{ 0x54032, 0x8400 }, { 0x54032, 0x8400 },
{ 0x54033, 0x3300 }, { 0x54033, 0x3300 },
{ 0x54034, 0x4600 }, { 0x54034, 0x6600 },
{ 0x54035, 0x48 }, { 0x54035, 0x48 },
{ 0x54036, 0x48 }, { 0x54036, 0x48 },
{ 0x54037, 0x1500 }, { 0x54037, 0x1600 },
{ 0x54038, 0x8400 }, { 0x54038, 0x8400 },
{ 0x54039, 0x3300 }, { 0x54039, 0x3300 },
{ 0x5403a, 0x4600 }, { 0x5403a, 0x6600 },
{ 0x5403b, 0x48 }, { 0x5403b, 0x48 },
{ 0x5403c, 0x48 }, { 0x5403c, 0x48 },
{ 0x5403d, 0x1500 }, { 0x5403d, 0x1600 },
{ 0xd0000, 0x1 }, { 0xd0000, 0x1 },
}; };
@@ -1640,67 +1644,58 @@ struct dram_cfg_param ddr_phy_pie[] = {
{ 0x90155, 0x20 }, { 0x90155, 0x20 },
{ 0x90156, 0x2aa }, { 0x90156, 0x2aa },
{ 0x90157, 0x9 }, { 0x90157, 0x9 },
{ 0x90158, 0x0 }, { 0x90158, 0x8 },
{ 0x90159, 0x400 }, { 0x90159, 0xe8 },
{ 0x9015a, 0x10e }, { 0x9015a, 0x109 },
{ 0x9015b, 0x8 }, { 0x9015b, 0x0 },
{ 0x9015c, 0xe8 }, { 0x9015c, 0x8140 },
{ 0x9015d, 0x109 }, { 0x9015d, 0x10c },
{ 0x9015e, 0x0 }, { 0x9015e, 0x10 },
{ 0x9015f, 0x8140 }, { 0x9015f, 0x8138 },
{ 0x90160, 0x10c }, { 0x90160, 0x104 },
{ 0x90161, 0x10 }, { 0x90161, 0x8 },
{ 0x90162, 0x8138 }, { 0x90162, 0x448 },
{ 0x90163, 0x10c }, { 0x90163, 0x109 },
{ 0x90164, 0x8 }, { 0x90164, 0xf },
{ 0x90165, 0x7c8 }, { 0x90165, 0x7c0 },
{ 0x90166, 0x101 }, { 0x90166, 0x109 },
{ 0x90167, 0x8 }, { 0x90167, 0x0 },
{ 0x90168, 0x448 }, { 0x90168, 0xe8 },
{ 0x90169, 0x109 }, { 0x90169, 0x109 },
{ 0x9016a, 0xf }, { 0x9016a, 0x47 },
{ 0x9016b, 0x7c0 }, { 0x9016b, 0x630 },
{ 0x9016c, 0x109 }, { 0x9016c, 0x109 },
{ 0x9016d, 0x0 }, { 0x9016d, 0x8 },
{ 0x9016e, 0xe8 }, { 0x9016e, 0x618 },
{ 0x9016f, 0x109 }, { 0x9016f, 0x109 },
{ 0x90170, 0x47 }, { 0x90170, 0x8 },
{ 0x90171, 0x630 }, { 0x90171, 0xe0 },
{ 0x90172, 0x109 }, { 0x90172, 0x109 },
{ 0x90173, 0x8 }, { 0x90173, 0x0 },
{ 0x90174, 0x618 }, { 0x90174, 0x7c8 },
{ 0x90175, 0x109 }, { 0x90175, 0x109 },
{ 0x90176, 0x8 }, { 0x90176, 0x8 },
{ 0x90177, 0xe0 }, { 0x90177, 0x8140 },
{ 0x90178, 0x109 }, { 0x90178, 0x10c },
{ 0x90179, 0x0 }, { 0x90179, 0x0 },
{ 0x9017a, 0x7c8 }, { 0x9017a, 0x478 },
{ 0x9017b, 0x109 }, { 0x9017b, 0x109 },
{ 0x9017c, 0x8 }, { 0x9017c, 0x0 },
{ 0x9017d, 0x8140 }, { 0x9017d, 0x1 },
{ 0x9017e, 0x10c }, { 0x9017e, 0x8 },
{ 0x9017f, 0x0 }, { 0x9017f, 0x8 },
{ 0x90180, 0x478 }, { 0x90180, 0x4 },
{ 0x90181, 0x109 }, { 0x90181, 0x0 },
{ 0x90182, 0x0 }, { 0x90006, 0x8 },
{ 0x90183, 0x1 }, { 0x90007, 0x7c8 },
{ 0x90184, 0x8 }, { 0x90008, 0x109 },
{ 0x90185, 0x8 },
{ 0x90186, 0x4 },
{ 0x90187, 0x8 },
{ 0x90188, 0x8 },
{ 0x90189, 0x7c8 },
{ 0x9018a, 0x101 },
{ 0x90006, 0x0 },
{ 0x90007, 0x0 },
{ 0x90008, 0x8 },
{ 0x90009, 0x0 }, { 0x90009, 0x0 },
{ 0x9000a, 0x0 }, { 0x9000a, 0x400 },
{ 0x9000b, 0x0 }, { 0x9000b, 0x106 },
{ 0xd00e7, 0x400 }, { 0xd00e7, 0x400 },
{ 0x90017, 0x0 }, { 0x90017, 0x0 },
{ 0x9001f, 0x29 }, { 0x9001f, 0x29 },
{ 0x90026, 0x6a }, { 0x90026, 0x68 },
{ 0x400d0, 0x0 }, { 0x400d0, 0x0 },
{ 0x400d1, 0x101 }, { 0x400d1, 0x101 },
{ 0x400d2, 0x105 }, { 0x400d2, 0x105 },
@@ -1710,6 +1705,7 @@ struct dram_cfg_param ddr_phy_pie[] = {
{ 0x400d6, 0x20a }, { 0x400d6, 0x20a },
{ 0x400d7, 0x20b }, { 0x400d7, 0x20b },
{ 0x2003a, 0x2 }, { 0x2003a, 0x2 },
{ 0x200be, 0x3 },
{ 0x2000b, 0x7d }, { 0x2000b, 0x7d },
{ 0x2000c, 0xfa }, { 0x2000c, 0xfa },
{ 0x2000d, 0x9c4 }, { 0x2000d, 0x9c4 },
@@ -1862,14 +1858,27 @@ struct dram_timing_info dram_timing = {
#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC #ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
void board_dram_ecc_scrub(void) void board_dram_ecc_scrub(void)
{ {
/* add inline scrb function MPlus spcific */ ddrc_inline_ecc_scrub(0x0, 0x3ffffff);
/* scrub 0-1.75G */ ddrc_inline_ecc_scrub(0x20000000, 0x23ffffff);
ddrc_inline_ecc_scrub(0x0, 0x1bffffff); ddrc_inline_ecc_scrub(0x40000000, 0x43ffffff);
/* scrub 2-3.75G */ ddrc_inline_ecc_scrub(0x4000000, 0x7ffffff);
ddrc_inline_ecc_scrub(0x20000000, 0x3bffffff); ddrc_inline_ecc_scrub(0x24000000, 0x27ffffff);
/* scrub 4-5.75G */ ddrc_inline_ecc_scrub(0x44000000, 0x47ffffff);
ddrc_inline_ecc_scrub(0x40000000, 0x5bffffff); ddrc_inline_ecc_scrub(0x8000000, 0xbffffff);
/* set scruber read range 0-6G */ ddrc_inline_ecc_scrub(0x28000000, 0x2bffffff);
ddrc_inline_ecc_scrub(0x48000000, 0x4bffffff);
ddrc_inline_ecc_scrub(0xc000000, 0xfffffff);
ddrc_inline_ecc_scrub(0x2c000000, 0x2fffffff);
ddrc_inline_ecc_scrub(0x4c000000, 0x4fffffff);
ddrc_inline_ecc_scrub(0x10000000, 0x13ffffff);
ddrc_inline_ecc_scrub(0x30000000, 0x33ffffff);
ddrc_inline_ecc_scrub(0x50000000, 0x53ffffff);
ddrc_inline_ecc_scrub(0x14000000, 0x17ffffff);
ddrc_inline_ecc_scrub(0x34000000, 0x37ffffff);
ddrc_inline_ecc_scrub(0x54000000, 0x57ffffff);
ddrc_inline_ecc_scrub(0x18000000, 0x1bffffff);
ddrc_inline_ecc_scrub(0x38000000, 0x3bffffff);
ddrc_inline_ecc_scrub(0x58000000, 0x5bffffff);
ddrc_inline_ecc_scrub_end(0x0, 0x5fffffff); ddrc_inline_ecc_scrub_end(0x0, 0x5fffffff);
} }
#endif #endif