Merge branch 'master' of git://git.denx.de/u-boot-coldfire
This commit is contained in:
Wolfgang Denk
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o mii.o
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COBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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@@ -1,304 +0,0 @@
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/*
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||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
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*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
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#include <common.h>
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#include <asm/fec.h>
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#include <asm/immap.h>
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#include <config.h>
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#include <net.h>
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||||
DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
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#undef MII_DEBUG
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#undef ET_DEBUG
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||||
int fecpin_setclear(struct eth_device *dev, int setclear)
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||||
{
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if (setclear) {
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MCFGPIO_PASPAR |= 0x0F00;
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MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
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} else {
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MCFGPIO_PASPAR &= 0xF0FF;
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MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
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}
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return 0;
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}
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#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
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#include <miiphy.h>
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/* Make MII read/write commands for the FEC. */
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#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
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#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
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/* PHY identification */
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#define PHY_ID_LXT970 0x78100000 /* LXT970 */
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#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
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#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
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#define PHY_ID_QS6612 0x01814400 /* QS6612 */
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#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
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#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */
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||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
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||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
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||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
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#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
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#define STR_ID_LXT970 "LXT970"
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#define STR_ID_LXT971 "LXT971"
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#define STR_ID_82555 "Intel82555"
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#define STR_ID_QS6612 "QS6612"
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#define STR_ID_AMD79C784 "AMD79C784"
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#define STR_ID_AMD79C874VC "AMD79C874VC"
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#define STR_ID_LSI80225 "LSI80225"
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#define STR_ID_LSI80225B "LSI80225/B"
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#define STR_ID_DP83848VV "N83848"
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#define STR_ID_DP83849 "N83849"
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/****************************************************************************
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* mii_init -- Initialize the MII for MII command without ethernet
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* This function is a subset of eth_init
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****************************************************************************
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*/
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void mii_reset(struct fec_info_s *info)
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{
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volatile fec_t *fecp = (fec_t *) (info->miibase);
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int i;
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fecp->ecr = FEC_ECR_RESET;
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for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
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udelay(1);
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}
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if (i == FEC_RESET_DELAY) {
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printf("FEC_RESET_DELAY timeout\n");
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}
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}
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/* send command to phy using mii, wait for result */
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uint mii_send(uint mii_cmd)
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{
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struct fec_info_s *info;
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struct eth_device *dev;
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volatile fec_t *ep;
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uint mii_reply;
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int j = 0;
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/* retrieve from register structure */
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dev = eth_get_dev();
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info = dev->priv;
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ep = (fec_t *) info->miibase;
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ep->mmfr = mii_cmd; /* command to phy */
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/* wait for mii complete */
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while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
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udelay(1);
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j++;
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}
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if (j >= MCFFEC_TOUT_LOOP) {
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printf("MII not complete\n");
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return -1;
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}
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mii_reply = ep->mmfr; /* result from phy */
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ep->eir = FEC_EIR_MII; /* clear MII complete */
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#ifdef ET_DEBUG
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printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
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__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
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#endif
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return (mii_reply & 0xffff); /* data read from phy */
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}
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#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
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#if defined(CONFIG_SYS_DISCOVER_PHY)
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int mii_discover_phy(struct eth_device *dev)
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{
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#define MAX_PHY_PASSES 11
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struct fec_info_s *info = dev->priv;
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int phyaddr, pass;
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uint phyno, phytype;
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if (info->phyname_init)
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return info->phy_addr;
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phyaddr = -1; /* didn't find a PHY yet */
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for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
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if (pass > 1) {
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/* PHY may need more time to recover from reset.
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* The LXT970 needs 50ms typical, no maximum is
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* specified, so wait 10ms before try again.
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* With 11 passes this gives it 100ms to wake up.
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*/
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udelay(10000); /* wait 10ms */
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}
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for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
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phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
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#ifdef ET_DEBUG
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printf("PHY type 0x%x pass %d type\n", phytype, pass);
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#endif
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if (phytype != 0xffff) {
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phyaddr = phyno;
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phytype <<= 16;
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phytype |=
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mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
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switch (phytype & 0xffffffff) {
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case PHY_ID_AMD79C874VC:
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strcpy(info->phy_name,
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STR_ID_AMD79C874VC);
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info->phyname_init = 1;
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break;
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default:
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strcpy(info->phy_name, "unknown");
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info->phyname_init = 1;
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break;
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}
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#ifdef ET_DEBUG
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printf("PHY @ 0x%x pass %d type ", phyno, pass);
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switch (phytype & 0xffffffff) {
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case PHY_ID_AMD79C874VC:
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printf(STR_ID_AMD79C874VC);
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break;
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default:
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printf("0x%08x\n", phytype);
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break;
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}
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#endif
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}
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}
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}
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if (phyaddr < 0)
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printf("No PHY device found.\n");
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return phyaddr;
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}
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#endif /* CONFIG_SYS_DISCOVER_PHY */
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void mii_init(void) __attribute__((weak,alias("__mii_init")));
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void __mii_init(void)
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{
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volatile fec_t *fecp;
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struct fec_info_s *info;
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struct eth_device *dev;
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int miispd = 0, i = 0;
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u16 autoneg = 0;
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/* retrieve from register structure */
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dev = eth_get_dev();
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info = dev->priv;
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fecp = (fec_t *) info->miibase;
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fecpin_setclear(dev, 1);
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mii_reset(info);
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/* We use strictly polling mode only */
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fecp->eimr = 0;
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/* Clear any pending interrupt */
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fecp->eir = 0xffffffff;
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/* Set MII speed */
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miispd = (gd->bus_clk / 1000000) / 5;
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fecp->mscr = miispd << 1;
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info->phy_addr = mii_discover_phy(dev);
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#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
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while (i < MCFFEC_TOUT_LOOP) {
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autoneg = 0;
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miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
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i++;
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if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
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break;
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udelay(500);
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}
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if (i >= MCFFEC_TOUT_LOOP) {
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printf("Auto Negotiation not complete\n");
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}
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||||
/* adapt to the half/full speed settings */
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info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
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info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
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}
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/*****************************************************************************
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||||
* Read and write a MII PHY register, routines used by MII Utilities
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||||
*
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||||
* FIXME: These routines are expected to return 0 on success, but mii_send
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* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
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||||
* no PHY connected...
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||||
* For now always return 0.
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||||
* FIXME: These routines only work after calling eth_init() at least once!
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* Otherwise they hang in mii_send() !!! Sorry!
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||||
*****************************************************************************/
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int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
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||||
unsigned short *value)
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||||
{
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||||
short rdreg; /* register working value */
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||||
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||||
#ifdef MII_DEBUG
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||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
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||||
#endif
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||||
rdreg = mii_send(mk_mii_read(addr, reg));
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||||
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||||
*value = rdreg;
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||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
||||
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o flash.o mii.o
|
||||
COBJS = $(BOARD).o flash.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
@@ -1,303 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
|
||||
if (setclear) {
|
||||
gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
|
||||
} else {
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_AMD79C874VC "AMD79C874VC"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_AMD79C874VC:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_AMD79C874VC);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_AMD79C874VC:
|
||||
printf(STR_ID_AMD79C874VC);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY */
|
||||
|
||||
void mii_init(void) __attribute__((weak,alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
||||
@@ -22,4 +22,6 @@
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
TEXT_BASE = 0
|
||||
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
|
||||
|
||||
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
|
||||
|
||||
@@ -38,8 +38,18 @@ int checkboard(void)
|
||||
|
||||
phys_size_t initdram(int board_type)
|
||||
{
|
||||
u32 dramsize;
|
||||
|
||||
#ifdef CONFIG_CF_SBF
|
||||
/*
|
||||
* Serial Boot: The dram is already initialized in start.S
|
||||
* only require to return DRAM size
|
||||
*/
|
||||
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
|
||||
#else
|
||||
volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
|
||||
u32 dramsize, i;
|
||||
volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
|
||||
u32 i;
|
||||
|
||||
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
|
||||
|
||||
@@ -49,6 +59,8 @@ phys_size_t initdram(int board_type)
|
||||
}
|
||||
i--;
|
||||
|
||||
gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
|
||||
|
||||
sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
|
||||
|
||||
sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
|
||||
@@ -56,24 +68,30 @@ phys_size_t initdram(int board_type)
|
||||
|
||||
/* Issue PALL */
|
||||
sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
|
||||
__asm__("nop");
|
||||
|
||||
/* Issue LEMR */
|
||||
/*sdram->sdmr = CONFIG_SYS_SDRAM_EMOD; */
|
||||
sdram->sdmr = CONFIG_SYS_SDRAM_MODE;
|
||||
__asm__("nop");
|
||||
sdram->sdmr = CONFIG_SYS_SDRAM_EMOD;
|
||||
__asm__("nop");
|
||||
|
||||
udelay(1000);
|
||||
|
||||
/* Issue PALL */
|
||||
sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
|
||||
__asm__("nop");
|
||||
|
||||
/* Perform two refresh cycles */
|
||||
sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
|
||||
__asm__("nop");
|
||||
sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
|
||||
__asm__("nop");
|
||||
|
||||
sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
|
||||
sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000C00;
|
||||
|
||||
udelay(100);
|
||||
|
||||
#endif
|
||||
return (dramsize);
|
||||
};
|
||||
|
||||
|
||||
@@ -33,11 +33,11 @@ SECTIONS
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
@@ -55,15 +55,7 @@ SECTIONS
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/mcf523x/start.o (.text)
|
||||
cpu/mcf523x/cpu_init.o (.text)
|
||||
lib_m68k/traps.o (.text)
|
||||
lib_m68k/interrupts.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
. = DEFINED(env_offset) ? env_offset : .;
|
||||
common/env_embedded.o (.text)
|
||||
cpu/mcf5227x/start.o (.text)
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
@@ -129,7 +121,7 @@ SECTIONS
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss (NOLOAD) :
|
||||
.bss :
|
||||
{
|
||||
_sbss = .;
|
||||
*(.sbss) *(.scommon)
|
||||
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o mii.o
|
||||
COBJS = $(BOARD).o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
@@ -1,307 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
|
||||
if (setclear) {
|
||||
gpio->par_feci2c |=
|
||||
(GPIO_PAR_FECI2C_EMDC_FECEMDC | GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
|
||||
} else {
|
||||
gpio->par_feci2c &=
|
||||
~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
#define STR_ID_KS8721BL "KS8721BL"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_KS8721BL:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_KS8721BL);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_KS8721BL:
|
||||
printf(STR_ID_KS8721BL);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY */
|
||||
|
||||
void mii_init(void) __attribute__((weak,alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
||||
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o mii.o
|
||||
COBJS = $(BOARD).o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
@@ -1,303 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
if (setclear) {
|
||||
/* Enable Ethernet pins */
|
||||
mbar_writeByte(MCF_GPIO_PAR_FECI2C, CONFIG_SYS_FECI2C);
|
||||
} else {
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
#define STR_ID_KS8721BL "KS8721BL"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_KS8721BL:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_KS8721BL);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_KS8721BL:
|
||||
printf(STR_ID_KS8721BL);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY */
|
||||
|
||||
void mii_init(void) __attribute__((weak,alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
||||
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o flash.o mii.o
|
||||
COBJS = $(BOARD).o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
@@ -1,378 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2000-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
|
||||
#define FLASH_BANK_SIZE 0x200000
|
||||
|
||||
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
|
||||
|
||||
void flash_print_info (flash_info_t * info)
|
||||
{
|
||||
int i;
|
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case (AMD_MANUFACT & FLASH_VENDMASK):
|
||||
printf ("AMD: ");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Vendor ");
|
||||
break;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case (AMD_ID_PL160CB & FLASH_TYPEMASK):
|
||||
printf ("AM29PL160CB (16Mbit)\n");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Chip Type\n");
|
||||
goto Done;
|
||||
break;
|
||||
}
|
||||
|
||||
printf (" Size: %ld MB in %d Sectors\n",
|
||||
info->size >> 20, info->sector_count);
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
if ((i % 5) == 0) {
|
||||
printf ("\n ");
|
||||
}
|
||||
printf (" %08lX%s", info->start[i],
|
||||
info->protect[i] ? " (RO)" : " ");
|
||||
}
|
||||
printf ("\n");
|
||||
|
||||
Done:
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
int i, j;
|
||||
ulong size = 0;
|
||||
|
||||
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
|
||||
ulong flashbase = 0;
|
||||
|
||||
flash_info[i].flash_id =
|
||||
(AMD_MANUFACT & FLASH_VENDMASK) |
|
||||
(AMD_ID_PL160CB & FLASH_TYPEMASK);
|
||||
flash_info[i].size = FLASH_BANK_SIZE;
|
||||
flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
|
||||
memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
|
||||
if (i == 0)
|
||||
flashbase = PHYS_FLASH_1;
|
||||
else
|
||||
panic ("configured to many flash banks!\n");
|
||||
|
||||
for (j = 0; j < flash_info[i].sector_count; j++) {
|
||||
if (j == 0) {
|
||||
/* 1st is 16 KiB */
|
||||
flash_info[i].start[j] = flashbase;
|
||||
}
|
||||
if ((j >= 1) && (j <= 2)) {
|
||||
/* 2nd and 3rd are 8 KiB */
|
||||
flash_info[i].start[j] =
|
||||
flashbase + 0x4000 + 0x2000 * (j - 1);
|
||||
}
|
||||
if (j == 3) {
|
||||
/* 4th is 224 KiB */
|
||||
flash_info[i].start[j] = flashbase + 0x8000;
|
||||
}
|
||||
if ((j >= 4) && (j <= 10)) {
|
||||
/* rest is 256 KiB */
|
||||
flash_info[i].start[j] =
|
||||
flashbase + 0x40000 + 0x40000 * (j -
|
||||
4);
|
||||
}
|
||||
}
|
||||
size += flash_info[i].size;
|
||||
}
|
||||
|
||||
flash_protect (FLAG_PROTECT_SET,
|
||||
CONFIG_SYS_FLASH_BASE,
|
||||
CONFIG_SYS_FLASH_BASE + 0x3ffff, &flash_info[0]);
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
|
||||
#define CMD_READ_ARRAY 0x00F0
|
||||
#define CMD_UNLOCK1 0x00AA
|
||||
#define CMD_UNLOCK2 0x0055
|
||||
#define CMD_ERASE_SETUP 0x0080
|
||||
#define CMD_ERASE_CONFIRM 0x0030
|
||||
#define CMD_PROGRAM 0x00A0
|
||||
#define CMD_UNLOCK_BYPASS 0x0020
|
||||
|
||||
#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555<<1)))
|
||||
#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA<<1)))
|
||||
|
||||
#define BIT_ERASE_DONE 0x0080
|
||||
#define BIT_RDY_MASK 0x0080
|
||||
#define BIT_PROGRAM_ERROR 0x0020
|
||||
#define BIT_TIMEOUT 0x80000000 /* our flag */
|
||||
|
||||
#define READY 1
|
||||
#define ERR 2
|
||||
#define TMO 4
|
||||
|
||||
|
||||
int flash_erase (flash_info_t * info, int s_first, int s_last)
|
||||
{
|
||||
ulong result;
|
||||
int iflag, cflag, prot, sect;
|
||||
int rc = ERR_OK;
|
||||
int chip1;
|
||||
|
||||
/* first look for protection bits */
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN)
|
||||
return ERR_UNKNOWN_FLASH_TYPE;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
return ERR_INVAL;
|
||||
}
|
||||
|
||||
if ((info->flash_id & FLASH_VENDMASK) !=
|
||||
(AMD_MANUFACT & FLASH_VENDMASK)) {
|
||||
return ERR_UNKNOWN_FLASH_VENDOR;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect = s_first; sect <= s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
if (prot)
|
||||
return ERR_PROTECTED;
|
||||
|
||||
/*
|
||||
* Disable interrupts which might cause a timeout
|
||||
* here. Remember that our exception vectors are
|
||||
* at address 0 in the flash, and we don't want a
|
||||
* (ticker) exception to happen while the flash
|
||||
* chip is in programming mode.
|
||||
*/
|
||||
|
||||
cflag = icache_status ();
|
||||
icache_disable ();
|
||||
iflag = disable_interrupts ();
|
||||
|
||||
printf ("\n");
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
|
||||
printf ("Erasing sector %2d ... ", sect);
|
||||
|
||||
/* arm simple, non interrupt dependent timer */
|
||||
set_timer (0);
|
||||
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
volatile u16 *addr =
|
||||
(volatile u16 *) (info->start[sect]);
|
||||
|
||||
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
|
||||
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
|
||||
MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
|
||||
|
||||
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
|
||||
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
|
||||
*addr = CMD_ERASE_CONFIRM;
|
||||
|
||||
/* wait until flash is ready */
|
||||
chip1 = 0;
|
||||
|
||||
do {
|
||||
result = *addr;
|
||||
|
||||
/* check timeout */
|
||||
if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
|
||||
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
|
||||
chip1 = TMO;
|
||||
break;
|
||||
}
|
||||
|
||||
if (!chip1
|
||||
&& (result & 0xFFFF) & BIT_ERASE_DONE)
|
||||
chip1 = READY;
|
||||
|
||||
} while (!chip1);
|
||||
|
||||
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
|
||||
|
||||
if (chip1 == ERR) {
|
||||
rc = ERR_PROG_ERROR;
|
||||
goto outahere;
|
||||
}
|
||||
if (chip1 == TMO) {
|
||||
rc = ERR_TIMOUT;
|
||||
goto outahere;
|
||||
}
|
||||
|
||||
printf ("ok.\n");
|
||||
} else { /* it was protected */
|
||||
|
||||
printf ("protected!\n");
|
||||
}
|
||||
}
|
||||
|
||||
if (ctrlc ())
|
||||
printf ("User Interrupt!\n");
|
||||
|
||||
outahere:
|
||||
/* allow flash to settle - wait 10 ms */
|
||||
udelay (10000);
|
||||
|
||||
if (iflag)
|
||||
enable_interrupts ();
|
||||
|
||||
if (cflag)
|
||||
icache_enable ();
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int write_word (flash_info_t * info, ulong dest, ulong data)
|
||||
{
|
||||
volatile u16 *addr = (volatile u16 *) dest;
|
||||
ulong result;
|
||||
int rc = ERR_OK;
|
||||
int cflag, iflag;
|
||||
int chip1;
|
||||
|
||||
/*
|
||||
* Check if Flash is (sufficiently) erased
|
||||
*/
|
||||
result = *addr;
|
||||
if ((result & data) != data)
|
||||
return ERR_NOT_ERASED;
|
||||
|
||||
|
||||
/*
|
||||
* Disable interrupts which might cause a timeout
|
||||
* here. Remember that our exception vectors are
|
||||
* at address 0 in the flash, and we don't want a
|
||||
* (ticker) exception to happen while the flash
|
||||
* chip is in programming mode.
|
||||
*/
|
||||
|
||||
cflag = icache_status ();
|
||||
icache_disable ();
|
||||
iflag = disable_interrupts ();
|
||||
|
||||
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
|
||||
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
|
||||
MEM_FLASH_ADDR1 = CMD_PROGRAM;
|
||||
*addr = data;
|
||||
|
||||
/* arm simple, non interrupt dependent timer */
|
||||
set_timer (0);
|
||||
|
||||
/* wait until flash is ready */
|
||||
chip1 = 0;
|
||||
do {
|
||||
result = *addr;
|
||||
|
||||
/* check timeout */
|
||||
if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
|
||||
chip1 = ERR | TMO;
|
||||
break;
|
||||
}
|
||||
if (!chip1 && ((result & 0x80) == (data & 0x80)))
|
||||
chip1 = READY;
|
||||
|
||||
} while (!chip1);
|
||||
|
||||
*addr = CMD_READ_ARRAY;
|
||||
|
||||
if (chip1 == ERR || *addr != data)
|
||||
rc = ERR_PROG_ERROR;
|
||||
|
||||
if (iflag)
|
||||
enable_interrupts ();
|
||||
|
||||
if (cflag)
|
||||
icache_enable ();
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
||||
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong wp, data;
|
||||
int rc;
|
||||
|
||||
if (addr & 1) {
|
||||
printf ("unaligned destination not supported\n");
|
||||
return ERR_ALIGN;
|
||||
}
|
||||
|
||||
#if 0
|
||||
if (cnt & 1) {
|
||||
printf ("odd transfer sizes not supported\n");
|
||||
return ERR_ALIGN;
|
||||
}
|
||||
#endif
|
||||
|
||||
wp = addr;
|
||||
|
||||
if (addr & 1) {
|
||||
data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *)
|
||||
src);
|
||||
if ((rc = write_word (info, wp - 1, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
src += 1;
|
||||
wp += 1;
|
||||
cnt -= 1;
|
||||
}
|
||||
|
||||
while (cnt >= 2) {
|
||||
data = *((volatile u16 *) src);
|
||||
if ((rc = write_word (info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
src += 2;
|
||||
wp += 2;
|
||||
cnt -= 2;
|
||||
}
|
||||
|
||||
if (cnt == 1) {
|
||||
data = (*((volatile u8 *) src) << 8) |
|
||||
*((volatile u8 *) (wp + 1));
|
||||
if ((rc = write_word (info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
src += 1;
|
||||
wp += 1;
|
||||
cnt -= 1;
|
||||
}
|
||||
|
||||
return ERR_OK;
|
||||
}
|
||||
@@ -1,303 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
|
||||
if (setclear) {
|
||||
gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
|
||||
} else {
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_AMD79C874VC "AMD79C874VC"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_AMD79C874VC:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_AMD79C874VC);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_AMD79C874VC:
|
||||
printf(STR_ID_AMD79C874VC);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY */
|
||||
|
||||
void mii_init(void) __attribute__((weak,alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
||||
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o mii.o
|
||||
COBJS = $(BOARD).o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
@@ -1,319 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
struct fec_info_s *info = (struct fec_info_s *) dev->priv;
|
||||
volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
|
||||
|
||||
if (setclear) {
|
||||
/* Enable Ethernet pins */
|
||||
if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
|
||||
gpio->par_feci2c |= 0x0F00;
|
||||
gpio->par_fec0hl |= 0xC0;
|
||||
} else {
|
||||
gpio->par_feci2c |= 0x00A0;
|
||||
gpio->par_fec1hl |= 0xC0;
|
||||
}
|
||||
} else {
|
||||
if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
|
||||
gpio->par_feci2c &= ~0x0F00;
|
||||
gpio->par_fec0hl &= ~0xC0;
|
||||
} else {
|
||||
gpio->par_feci2c &= ~0x00A0;
|
||||
gpio->par_fec1hl &= ~0xC0;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
#define STR_ID_KS8721BL "KS8721BL"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_KS8721BL:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_KS8721BL);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_KS8721BL:
|
||||
printf(STR_ID_KS8721BL);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY */
|
||||
|
||||
void mii_init(void) __attribute__((weak,alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
||||
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o mii.o
|
||||
COBJS = $(BOARD).o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
@@ -1,304 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
if (setclear) {
|
||||
MCFGPIO_PASPAR |= 0x0F00;
|
||||
MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
|
||||
} else {
|
||||
MCFGPIO_PASPAR &= 0xF0FF;
|
||||
MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_AMD79C874VC "AMD79C874VC"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_AMD79C874VC:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_AMD79C874VC);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_AMD79C874VC:
|
||||
printf(STR_ID_AMD79C874VC);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY */
|
||||
|
||||
void mii_init(void) __attribute__((weak,alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
||||
44
board/freescale/m53017evb/Makefile
Normal file
44
board/freescale/m53017evb/Makefile
Normal file
@@ -0,0 +1,44 @@
|
||||
#
|
||||
# (C) Copyright 2000-2003
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
25
board/freescale/m53017evb/config.mk
Normal file
25
board/freescale/m53017evb/config.mk
Normal file
@@ -0,0 +1,25 @@
|
||||
#
|
||||
# (C) Copyright 2000-2003
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
TEXT_BASE = 0
|
||||
94
board/freescale/m53017evb/m53017evb.c
Normal file
94
board/freescale/m53017evb/m53017evb.c
Normal file
@@ -0,0 +1,94 @@
|
||||
/*
|
||||
* (C) Copyright 2000-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: ");
|
||||
puts("Freescale M53017EVB\n");
|
||||
return 0;
|
||||
};
|
||||
|
||||
phys_size_t initdram(int board_type)
|
||||
{
|
||||
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
|
||||
u32 dramsize, i;
|
||||
|
||||
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
|
||||
|
||||
for (i = 0x13; i < 0x20; i++) {
|
||||
if (dramsize == (1 << i))
|
||||
break;
|
||||
}
|
||||
i--;
|
||||
|
||||
sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
|
||||
#ifdef CONFIG_SYS_SDRAM_BASE1
|
||||
sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i);
|
||||
#endif
|
||||
sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
|
||||
sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
|
||||
|
||||
udelay(500);
|
||||
|
||||
/* Issue PALL */
|
||||
sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
|
||||
asm("nop");
|
||||
|
||||
/* Perform two refresh cycles */
|
||||
sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
|
||||
sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
|
||||
asm("nop");
|
||||
|
||||
/* Issue LEMR */
|
||||
sdram->mode = CONFIG_SYS_SDRAM_MODE;
|
||||
asm("nop");
|
||||
sdram->mode = CONFIG_SYS_SDRAM_EMOD;
|
||||
asm("nop");
|
||||
|
||||
sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
|
||||
asm("nop");
|
||||
|
||||
sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
|
||||
asm("nop");
|
||||
|
||||
udelay(100);
|
||||
|
||||
return dramsize;
|
||||
};
|
||||
|
||||
int testdram(void)
|
||||
{
|
||||
/* TODO: XXX XXX XXX */
|
||||
printf("DRAM test not implemented!\n");
|
||||
|
||||
return (0);
|
||||
}
|
||||
@@ -55,9 +55,9 @@ SECTIONS
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/mcf5445x/start.o (.text)
|
||||
lib_m68k/traps.o (.text)
|
||||
lib_m68k/interrupts.o (.text)
|
||||
cpu/mcf532x/start.o (.text)
|
||||
cpu/mcf532x/libmcf532x.a (.text)
|
||||
lib_m68k/libm68k.a (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o mii.o nand.o
|
||||
COBJS = $(BOARD).o nand.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
@@ -1,306 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
|
||||
if (setclear) {
|
||||
gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
|
||||
gpio->par_feci2c |=
|
||||
GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO;
|
||||
} else {
|
||||
gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
|
||||
gpio->par_feci2c &=
|
||||
~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_DP83848VV:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_DP83848VV);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_DP83848VV:
|
||||
printf(STR_ID_DP83848VV);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY */
|
||||
|
||||
void mii_init(void) __attribute__((weak,alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
||||
@@ -36,56 +36,42 @@ DECLARE_GLOBAL_DATA_PTR;
|
||||
#include <linux/mtd/mtd.h>
|
||||
|
||||
#define SET_CLE 0x10
|
||||
#define CLR_CLE ~SET_CLE
|
||||
#define SET_ALE 0x08
|
||||
#define CLR_ALE ~SET_ALE
|
||||
|
||||
static void nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
|
||||
static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
|
||||
{
|
||||
struct nand_chip *this = mtdinfo->priv;
|
||||
/* volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; TODO: handle wp */
|
||||
u32 nand_baseaddr = (u32) this->IO_ADDR_W;
|
||||
volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
|
||||
|
||||
if (ctrl & NAND_CTRL_CHANGE) {
|
||||
if ( ctrl & NAND_CLE )
|
||||
nand_baseaddr |= SET_CLE;
|
||||
else
|
||||
nand_baseaddr &= CLR_CLE;
|
||||
if ( ctrl & NAND_ALE )
|
||||
nand_baseaddr |= SET_ALE;
|
||||
else
|
||||
nand_baseaddr &= CLR_ALE;
|
||||
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
|
||||
|
||||
IO_ADDR_W &= ~(SET_ALE | SET_CLE);
|
||||
*nCE &= 0xFFFB;
|
||||
|
||||
if (ctrl & NAND_NCE)
|
||||
*nCE |= 0x0004;
|
||||
if (ctrl & NAND_CLE)
|
||||
IO_ADDR_W |= SET_CLE;
|
||||
if (ctrl & NAND_ALE)
|
||||
IO_ADDR_W |= SET_ALE;
|
||||
|
||||
this->IO_ADDR_W = (void *)IO_ADDR_W;
|
||||
}
|
||||
this->IO_ADDR_W = (void __iomem *)(nand_baseaddr);
|
||||
|
||||
if (cmd != NAND_CMD_NONE)
|
||||
writeb(cmd, this->IO_ADDR_W);
|
||||
}
|
||||
|
||||
static void nand_write_byte(struct mtd_info *mtdinfo, u_char byte)
|
||||
{
|
||||
struct nand_chip *this = mtdinfo->priv;
|
||||
*((volatile u8 *)(this->IO_ADDR_W)) = byte;
|
||||
}
|
||||
|
||||
static u8 nand_read_byte(struct mtd_info *mtdinfo)
|
||||
{
|
||||
struct nand_chip *this = mtdinfo->priv;
|
||||
return (u8) (*((volatile u8 *)this->IO_ADDR_R));
|
||||
}
|
||||
|
||||
static int nand_dev_ready(struct mtd_info *mtdinfo)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
int board_nand_init(struct nand_chip *nand)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
|
||||
*((volatile u16 *)CONFIG_SYS_LATCH_ADDR) |= 0x0004;
|
||||
|
||||
/* set up pin configuration */
|
||||
/*
|
||||
* set up pin configuration - enabled 2nd output buffer's signals
|
||||
* (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
|
||||
* to use nCE signal
|
||||
*/
|
||||
gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
|
||||
gpio->pddr_timer |= 0x08;
|
||||
gpio->ppd_timer |= 0x08;
|
||||
@@ -95,9 +81,6 @@ int board_nand_init(struct nand_chip *nand)
|
||||
nand->chip_delay = 50;
|
||||
nand->ecc.mode = NAND_ECC_SOFT;
|
||||
nand->cmd_ctrl = nand_hwcontrol;
|
||||
nand->read_byte = nand_read_byte;
|
||||
nand->write_byte = nand_write_byte;
|
||||
nand->dev_ready = nand_dev_ready;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o mii.o nand.o
|
||||
COBJS = $(BOARD).o nand.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
@@ -1,306 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
|
||||
if (setclear) {
|
||||
gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
|
||||
gpio->par_feci2c |=
|
||||
GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO;
|
||||
} else {
|
||||
gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
|
||||
gpio->par_feci2c &=
|
||||
~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_DP83848VV:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_DP83848VV);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_DP83848VV:
|
||||
printf(STR_ID_DP83848VV);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY */
|
||||
|
||||
void mii_init(void) __attribute__((weak,alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
||||
@@ -41,19 +41,21 @@ DECLARE_GLOBAL_DATA_PTR;
|
||||
static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
|
||||
{
|
||||
struct nand_chip *this = mtdinfo->priv;
|
||||
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
|
||||
u32 nand_baseaddr = (u32) this->IO_ADDR_W;
|
||||
volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
|
||||
|
||||
if (ctrl & NAND_CTRL_CHANGE) {
|
||||
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
|
||||
IO_ADDR_W &= ~(SET_ALE | SE_CLE);
|
||||
|
||||
IO_ADDR_W &= ~(SET_ALE | SET_CLE);
|
||||
*nCE &= 0xFFFB;
|
||||
|
||||
if (ctrl & NAND_NCE)
|
||||
*nCE |= 0x0004;
|
||||
if (ctrl & NAND_CLE)
|
||||
IO_ADDR_W |= SET_CLE;
|
||||
if (ctrl & NAND_ALE)
|
||||
IO_ADDR_W |= SET_ALE;
|
||||
|
||||
at91_set_gpio_value(AT91_PIN_PD15, !(ctrl & NAND_NCE));
|
||||
this->IO_ADDR_W = (void *)IO_ADDR_W;
|
||||
|
||||
}
|
||||
@@ -67,10 +69,13 @@ int board_nand_init(struct nand_chip *nand)
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
|
||||
|
||||
*((volatile u16 *)CONFIG_SYS_LATCH_ADDR) |= 0x0004;
|
||||
fbcs->csmr2 &= ~FBCS_CSMR_WP;
|
||||
|
||||
/* set up pin configuration */
|
||||
/*
|
||||
* set up pin configuration - enabled 2nd output buffer's signals
|
||||
* (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
|
||||
* to use nCE signal
|
||||
*/
|
||||
gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
|
||||
gpio->pddr_timer |= 0x08;
|
||||
gpio->ppd_timer |= 0x08;
|
||||
|
||||
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o mii.o
|
||||
COBJS = $(BOARD).o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
@@ -1,303 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
struct fec_info_s *info = (struct fec_info_s *)dev->priv;
|
||||
|
||||
if (setclear) {
|
||||
gpio->par_feci2c |=
|
||||
(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
|
||||
|
||||
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
|
||||
gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
|
||||
else
|
||||
gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA;
|
||||
} else {
|
||||
gpio->par_feci2c &=
|
||||
~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
|
||||
|
||||
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
|
||||
gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK;
|
||||
else
|
||||
gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_KSZ8041NL 0x00221512
|
||||
#define STR_ID_KSZ8041NL "KSZ8041NL"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
struct eth_device *dev;
|
||||
int i, miispd;
|
||||
u16 rst = 0;
|
||||
|
||||
dev = eth_get_dev();
|
||||
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
miiphy_write(dev->name, info->phy_addr, PHY_BMCR, PHY_BMCR_RESET);
|
||||
for (i = 0; i < FEC_RESET_DELAY; ++i) {
|
||||
udelay(500);
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMCR, &rst);
|
||||
if ((rst & PHY_BMCR_RESET) == 0)
|
||||
break;
|
||||
}
|
||||
if (i == FEC_RESET_DELAY)
|
||||
printf("Mii reset timeout %d\n", i);
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_KSZ8041NL:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_KSZ8041NL);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_KSZ8041NL:
|
||||
printf(STR_ID_KSZ8041NL);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY */
|
||||
|
||||
void mii_init(void) __attribute__ ((weak, alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
||||
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o mii.o
|
||||
COBJS = $(BOARD).o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
@@ -1,324 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
struct fec_info_s *info = (struct fec_info_s *)dev->priv;
|
||||
|
||||
if (setclear) {
|
||||
gpio->par_feci2c |=
|
||||
(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
|
||||
|
||||
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
|
||||
gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
|
||||
else
|
||||
gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA;
|
||||
} else {
|
||||
gpio->par_feci2c &=
|
||||
~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
|
||||
|
||||
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
|
||||
gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK;
|
||||
else
|
||||
gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
struct eth_device *dev;
|
||||
int i, miispd;
|
||||
u16 rst = 0;
|
||||
|
||||
dev = eth_get_dev();
|
||||
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
miiphy_write(dev->name, info->phy_addr, PHY_BMCR, PHY_BMCR_RESET);
|
||||
for (i = 0; i < FEC_RESET_DELAY; ++i) {
|
||||
udelay(500);
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMCR, &rst);
|
||||
if ((rst & PHY_BMCR_RESET) == 0)
|
||||
break;
|
||||
}
|
||||
if (i == FEC_RESET_DELAY)
|
||||
printf("Mii reset timeout %d\n", i);
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_DP83848VV:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_DP83848VV);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_DP83848VV:
|
||||
printf(STR_ID_DP83848VV);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY */
|
||||
|
||||
void mii_init(void) __attribute__((weak,alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
||||
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o mii.o
|
||||
COBJS = $(BOARD).o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
@@ -1,322 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
#include <asm/immap.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/fsl_mcdmafec.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
struct fec_info_dma *info = (struct fec_info_dma *)dev->priv;
|
||||
|
||||
if (setclear) {
|
||||
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
|
||||
gpio->par_feci2cirq |= 0xF000;
|
||||
else
|
||||
gpio->par_feci2cirq |= 0x0FC0;
|
||||
} else {
|
||||
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
|
||||
gpio->par_feci2cirq &= 0x0FFF;
|
||||
else
|
||||
gpio->par_feci2cirq &= 0xF03F;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
#define PHY_ID_BCM5222 0x00406322 /* Broadcom 5222 */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
#define STR_ID_BCM5222 "BCM5222"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_dma *info)
|
||||
{
|
||||
volatile fecdma_t *fecp = (fecdma_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_dma *info;
|
||||
struct eth_device *dev;
|
||||
volatile fecdma_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fecdma_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_dma *info = dev->priv;
|
||||
int phyaddr, pass, temp;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init) {
|
||||
return info->phy_addr;
|
||||
}
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
temp = 0;
|
||||
if (info->index > 0) {
|
||||
/* Some phy have multiple address, to solve the issue
|
||||
where phyno keeps starting from 0, check the
|
||||
previous phy address if both miibase are the same. */
|
||||
if (info->miibase == (info->next)->miibase) {
|
||||
temp = (info->next)->phy_addr + 1;
|
||||
}
|
||||
}
|
||||
|
||||
for (phyno = temp; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_BCM5222:
|
||||
strcpy(info->phy_name, STR_ID_BCM5222);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_BCM5222:
|
||||
printf(STR_ID_BCM5222);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY */
|
||||
|
||||
void mii_init(void) __attribute__ ((weak, alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fecdma_t *fecp;
|
||||
struct fec_info_dma *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fecdma_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
||||
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o mii.o
|
||||
COBJS = $(BOARD).o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
@@ -1,322 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
#include <asm/immap.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/fsl_mcdmafec.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
struct fec_info_dma *info = (struct fec_info_dma *)dev->priv;
|
||||
|
||||
if (setclear) {
|
||||
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
|
||||
gpio->par_feci2cirq |= 0xF000;
|
||||
else
|
||||
gpio->par_feci2cirq |= 0x0FC0;
|
||||
} else {
|
||||
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
|
||||
gpio->par_feci2cirq &= 0x0FFF;
|
||||
else
|
||||
gpio->par_feci2cirq &= 0xF03F;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
#define PHY_ID_BCM5222 0x00406322 /* Broadcom 5222 */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
#define STR_ID_BCM5222 "BCM5222"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_dma *info)
|
||||
{
|
||||
volatile fecdma_t *fecp = (fecdma_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_dma *info;
|
||||
struct eth_device *dev;
|
||||
volatile fecdma_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fecdma_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_dma *info = dev->priv;
|
||||
int phyaddr, pass, temp;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init) {
|
||||
return info->phy_addr;
|
||||
}
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
temp = 0;
|
||||
if (info->index > 0) {
|
||||
/* Some phy have multiple address, to solve the issue
|
||||
where phyno keeps starting from 0, check the
|
||||
previous phy address if both miibase are the same. */
|
||||
if (info->miibase == (info->next)->miibase) {
|
||||
temp = (info->next)->phy_addr + 1;
|
||||
}
|
||||
}
|
||||
|
||||
for (phyno = temp; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_BCM5222:
|
||||
strcpy(info->phy_name, STR_ID_BCM5222);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_BCM5222:
|
||||
printf(STR_ID_BCM5222);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY */
|
||||
|
||||
void mii_init(void) __attribute__ ((weak, alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fecdma_t *fecp;
|
||||
struct fec_info_dma *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fecdma_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
||||
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o flash.o mii.o
|
||||
COBJS = $(BOARD).o flash.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
303
board/idmr/mii.c
303
board/idmr/mii.c
@@ -1,303 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fec.h>
|
||||
#include <asm/immap.h>
|
||||
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||
#undef MII_DEBUG
|
||||
#undef ET_DEBUG
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear)
|
||||
{
|
||||
if (setclear) {
|
||||
/* Enable Ethernet pins */
|
||||
mbar_writeByte(MCF_GPIO_PAR_FECI2C, CONFIG_SYS_FECI2C);
|
||||
} else {
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
|
||||
#include <miiphy.h>
|
||||
|
||||
/* Make MII read/write commands for the FEC. */
|
||||
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
|
||||
|
||||
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
|
||||
|
||||
/* PHY identification */
|
||||
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
|
||||
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
|
||||
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
|
||||
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
|
||||
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
|
||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||
#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
|
||||
#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
|
||||
#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */
|
||||
|
||||
#define STR_ID_LXT970 "LXT970"
|
||||
#define STR_ID_LXT971 "LXT971"
|
||||
#define STR_ID_82555 "Intel82555"
|
||||
#define STR_ID_QS6612 "QS6612"
|
||||
#define STR_ID_AMD79C784 "AMD79C784"
|
||||
#define STR_ID_LSI80225 "LSI80225"
|
||||
#define STR_ID_LSI80225B "LSI80225/B"
|
||||
#define STR_ID_DP83848VV "N83848"
|
||||
#define STR_ID_DP83849 "N83849"
|
||||
#define STR_ID_KS8721BL "KS8721BL"
|
||||
|
||||
/****************************************************************************
|
||||
* mii_init -- Initialize the MII for MII command without ethernet
|
||||
* This function is a subset of eth_init
|
||||
****************************************************************************
|
||||
*/
|
||||
void mii_reset(struct fec_info_s *info)
|
||||
{
|
||||
volatile fec_t *fecp = (fec_t *) (info->miibase);
|
||||
int i;
|
||||
|
||||
fecp->ecr = FEC_ECR_RESET;
|
||||
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
|
||||
udelay(1);
|
||||
}
|
||||
if (i == FEC_RESET_DELAY) {
|
||||
printf("FEC_RESET_DELAY timeout\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* send command to phy using mii, wait for result */
|
||||
uint mii_send(uint mii_cmd)
|
||||
{
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
volatile fec_t *ep;
|
||||
uint mii_reply;
|
||||
int j = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
ep = (fec_t *) info->miibase;
|
||||
|
||||
ep->mmfr = mii_cmd; /* command to phy */
|
||||
|
||||
/* wait for mii complete */
|
||||
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
|
||||
udelay(1);
|
||||
j++;
|
||||
}
|
||||
if (j >= MCFFEC_TOUT_LOOP) {
|
||||
printf("MII not complete\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
mii_reply = ep->mmfr; /* result from phy */
|
||||
ep->eir = FEC_EIR_MII; /* clear MII complete */
|
||||
#ifdef ET_DEBUG
|
||||
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
|
||||
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
|
||||
#endif
|
||||
|
||||
return (mii_reply & 0xffff); /* data read from phy */
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
|
||||
|
||||
#if defined(CONFIG_SYS_DISCOVER_PHY)
|
||||
int mii_discover_phy(struct eth_device *dev)
|
||||
{
|
||||
#define MAX_PHY_PASSES 11
|
||||
struct fec_info_s *info = dev->priv;
|
||||
int phyaddr, pass;
|
||||
uint phyno, phytype;
|
||||
|
||||
if (info->phyname_init)
|
||||
return info->phy_addr;
|
||||
|
||||
phyaddr = -1; /* didn't find a PHY yet */
|
||||
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
|
||||
if (pass > 1) {
|
||||
/* PHY may need more time to recover from reset.
|
||||
* The LXT970 needs 50ms typical, no maximum is
|
||||
* specified, so wait 10ms before try again.
|
||||
* With 11 passes this gives it 100ms to wake up.
|
||||
*/
|
||||
udelay(10000); /* wait 10ms */
|
||||
}
|
||||
|
||||
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
|
||||
|
||||
phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY type 0x%x pass %d type\n", phytype, pass);
|
||||
#endif
|
||||
if (phytype != 0xffff) {
|
||||
phyaddr = phyno;
|
||||
phytype <<= 16;
|
||||
phytype |=
|
||||
mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
|
||||
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_KS8721BL:
|
||||
strcpy(info->phy_name,
|
||||
STR_ID_KS8721BL);
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
default:
|
||||
strcpy(info->phy_name, "unknown");
|
||||
info->phyname_init = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("PHY @ 0x%x pass %d type ", phyno, pass);
|
||||
switch (phytype & 0xffffffff) {
|
||||
case PHY_ID_KS8721BL:
|
||||
printf(STR_ID_KS8721BL);
|
||||
break;
|
||||
default:
|
||||
printf("0x%08x\n", phytype);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
if (phyaddr < 0)
|
||||
printf("No PHY device found.\n");
|
||||
|
||||
return phyaddr;
|
||||
}
|
||||
#endif /* CONFIG_SYS_DISCOVER_PHY */
|
||||
|
||||
void mii_init(void) __attribute__((weak,alias("__mii_init")));
|
||||
|
||||
void __mii_init(void)
|
||||
{
|
||||
volatile fec_t *fecp;
|
||||
struct fec_info_s *info;
|
||||
struct eth_device *dev;
|
||||
int miispd = 0, i = 0;
|
||||
u16 autoneg = 0;
|
||||
|
||||
/* retrieve from register structure */
|
||||
dev = eth_get_dev();
|
||||
info = dev->priv;
|
||||
|
||||
fecp = (fec_t *) info->miibase;
|
||||
|
||||
fecpin_setclear(dev, 1);
|
||||
|
||||
mii_reset(info);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set MII speed */
|
||||
miispd = (gd->bus_clk / 1000000) / 5;
|
||||
fecp->mscr = miispd << 1;
|
||||
|
||||
info->phy_addr = mii_discover_phy(dev);
|
||||
|
||||
#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
|
||||
while (i < MCFFEC_TOUT_LOOP) {
|
||||
autoneg = 0;
|
||||
miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
|
||||
i++;
|
||||
|
||||
if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
if (i >= MCFFEC_TOUT_LOOP) {
|
||||
printf("Auto Negotiation not complete\n");
|
||||
}
|
||||
|
||||
/* adapt to the half/full speed settings */
|
||||
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
|
||||
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Read and write a MII PHY register, routines used by MII Utilities
|
||||
*
|
||||
* FIXME: These routines are expected to return 0 on success, but mii_send
|
||||
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
|
||||
* no PHY connected...
|
||||
* For now always return 0.
|
||||
* FIXME: These routines only work after calling eth_init() at least once!
|
||||
* Otherwise they hang in mii_send() !!! Sorry!
|
||||
*****************************************************************************/
|
||||
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short *value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
rdreg = mii_send(mk_mii_read(addr, reg));
|
||||
|
||||
*value = rdreg;
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", *value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
||||
unsigned short value)
|
||||
{
|
||||
short rdreg; /* register working value */
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
|
||||
#endif
|
||||
|
||||
rdreg = mii_send(mk_mii_write(addr, reg, value));
|
||||
|
||||
#ifdef MII_DEBUG
|
||||
printf("0x%04x\n", value);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
||||
Reference in New Issue
Block a user