clk: at91: clk-master: split master clock in pres and divider
Split master clock in 2 controlling block: one for prescaler one for
divider. This will allow referencing correctly the CPU clock and
master clock in device trees.
Reported-by: Eugen Hristev <eugen.hristev@microchip.com>
Fixes: a64862284f ("clk: at91: sam9x60: add support compatible with
CCF")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
This commit is contained in:
Claudiu Beznea
Eugen Hristev
parent
6beb4a3a59
commit
c05be59ca8
@ -12,13 +12,15 @@
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#include <asm/processor.h>
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#include <clk-uclass.h>
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#include <common.h>
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#include <div64.h>
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#include <dm.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/at91_pmc.h>
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#include "pmc.h"
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#define UBOOT_DM_CLK_AT91_MASTER "at91-master-clk"
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#define UBOOT_DM_CLK_AT91_MASTER_PRES "at91-master-clk-pres"
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#define UBOOT_DM_CLK_AT91_MASTER_DIV "at91-master-clk-div"
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#define UBOOT_DM_CLK_AT91_SAMA7G5_MASTER "at91-sama7g5-master-clk"
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#define MASTER_PRES_MASK 0x7
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@ -73,7 +75,7 @@ static int clk_master_enable(struct clk *clk)
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return 0;
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}
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static ulong clk_master_get_rate(struct clk *clk)
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static ulong clk_master_pres_get_rate(struct clk *clk)
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{
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struct clk_master *master = to_clk_master(clk);
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const struct clk_master_layout *layout = master->layout;
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@ -81,7 +83,7 @@ static ulong clk_master_get_rate(struct clk *clk)
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master->characteristics;
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ulong rate = clk_get_parent_rate(clk);
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unsigned int mckr;
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u8 pres, div;
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u8 pres;
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if (!rate)
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return 0;
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@ -90,29 +92,21 @@ static ulong clk_master_get_rate(struct clk *clk)
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mckr &= layout->mask;
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pres = (mckr >> layout->pres_shift) & MASTER_PRES_MASK;
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div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
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if (characteristics->have_div3_pres && pres == MASTER_PRES_MAX)
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rate /= 3;
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pres = 3;
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else
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rate >>= pres;
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pres = (1 << pres);
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rate /= characteristics->divisors[div];
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if (rate < characteristics->output.min)
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pr_warn("master clk is underclocked");
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else if (rate > characteristics->output.max)
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pr_warn("master clk is overclocked");
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return rate;
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return DIV_ROUND_CLOSEST_ULL(rate, pres);
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}
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static const struct clk_ops master_ops = {
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static const struct clk_ops master_pres_ops = {
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.enable = clk_master_enable,
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.get_rate = clk_master_get_rate,
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.get_rate = clk_master_pres_get_rate,
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};
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struct clk *at91_clk_register_master(void __iomem *base,
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struct clk *at91_clk_register_master_pres(void __iomem *base,
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const char *name, const char * const *parent_names,
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int num_parents, const struct clk_master_layout *layout,
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const struct clk_master_characteristics *characteristics,
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@ -140,7 +134,7 @@ struct clk *at91_clk_register_master(void __iomem *base,
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pmc_read(master->base, master->layout->offset, &val);
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clk = &master->clk;
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clk->flags = CLK_GET_RATE_NOCACHE | CLK_IS_CRITICAL;
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ret = clk_register(clk, UBOOT_DM_CLK_AT91_MASTER, name,
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ret = clk_register(clk, UBOOT_DM_CLK_AT91_MASTER_PRES, name,
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parent_names[val & AT91_PMC_CSS]);
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if (ret) {
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kfree(master);
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@ -150,10 +144,81 @@ struct clk *at91_clk_register_master(void __iomem *base,
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return clk;
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}
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U_BOOT_DRIVER(at91_master_clk) = {
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.name = UBOOT_DM_CLK_AT91_MASTER,
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U_BOOT_DRIVER(at91_master_pres_clk) = {
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.name = UBOOT_DM_CLK_AT91_MASTER_PRES,
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.id = UCLASS_CLK,
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.ops = &master_ops,
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.ops = &master_pres_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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static ulong clk_master_div_get_rate(struct clk *clk)
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{
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struct clk_master *master = to_clk_master(clk);
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const struct clk_master_layout *layout = master->layout;
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const struct clk_master_characteristics *characteristics =
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master->characteristics;
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ulong rate = clk_get_parent_rate(clk);
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unsigned int mckr;
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u8 div;
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if (!rate)
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return 0;
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pmc_read(master->base, master->layout->offset, &mckr);
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mckr &= layout->mask;
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div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
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rate = DIV_ROUND_CLOSEST_ULL(rate, characteristics->divisors[div]);
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if (rate < characteristics->output.min)
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pr_warn("master clk is underclocked");
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else if (rate > characteristics->output.max)
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pr_warn("master clk is overclocked");
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return rate;
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}
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static const struct clk_ops master_div_ops = {
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.enable = clk_master_enable,
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.get_rate = clk_master_div_get_rate,
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};
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struct clk *at91_clk_register_master_div(void __iomem *base,
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const char *name, const char *parent_name,
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const struct clk_master_layout *layout,
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const struct clk_master_characteristics *characteristics)
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{
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struct clk_master *master;
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struct clk *clk;
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int ret;
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if (!base || !name || !parent_name || !layout || !characteristics)
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return ERR_PTR(-EINVAL);
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master = kzalloc(sizeof(*master), GFP_KERNEL);
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if (!master)
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return ERR_PTR(-ENOMEM);
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master->layout = layout;
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master->characteristics = characteristics;
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master->base = base;
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master->num_parents = 1;
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clk = &master->clk;
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clk->flags = CLK_GET_RATE_NOCACHE | CLK_IS_CRITICAL;
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ret = clk_register(clk, UBOOT_DM_CLK_AT91_MASTER_DIV, name,
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parent_name);
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if (ret) {
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kfree(master);
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clk = ERR_PTR(ret);
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}
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return clk;
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}
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U_BOOT_DRIVER(at91_master_div_clk) = {
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.name = UBOOT_DM_CLK_AT91_MASTER_DIV,
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.id = UCLASS_CLK,
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.ops = &master_div_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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@ -97,12 +97,17 @@ sam9x60_clk_register_frac_pll(void __iomem *base, const char *name,
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const struct clk_pll_characteristics *characteristics,
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const struct clk_pll_layout *layout, bool critical);
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struct clk *
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at91_clk_register_master(void __iomem *base, const char *name,
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at91_clk_register_master_pres(void __iomem *base, const char *name,
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const char * const *parent_names, int num_parents,
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const struct clk_master_layout *layout,
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const struct clk_master_characteristics *characteristics,
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const u32 *mux_table);
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struct clk *
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at91_clk_register_master_div(void __iomem *base,
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const char *name, const char *parent_name,
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const struct clk_master_layout *layout,
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const struct clk_master_characteristics *characteristics);
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struct clk *
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at91_clk_sama7g5_register_master(void __iomem *base, const char *name,
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const char * const *parent_names, int num_parents,
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const u32 *mux_table, const u32 *clk_mux_table,
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@ -31,7 +31,7 @@
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* @ID_PLL_A_FRAC: APLL fractional clock identifier
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* @ID_PLL_A_DIV: APLL divider clock identifier
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* @ID_MCK: MCK clock identifier
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* @ID_MCK_DIV: MCK DIV clock identifier
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* @ID_UTMI: UTMI clock identifier
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@ -43,6 +43,8 @@
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* @ID_DDR: DDR system clock identifier
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* @ID_QSPI: QSPI system clock identifier
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*
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* @ID_MCK_PRES: MCK PRES clock identifier
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*
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* Note: if changing the values of this enums please sync them with
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* device tree
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*/
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@ -60,7 +62,7 @@ enum pmc_clk_ids {
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ID_PLL_A_FRAC = 9,
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ID_PLL_A_DIV = 10,
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ID_MCK = 11,
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ID_MCK_DIV = 11,
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ID_UTMI = 12,
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@ -73,6 +75,8 @@ enum pmc_clk_ids {
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ID_DDR = 17,
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ID_QSPI = 18,
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ID_MCK_PRES = 19,
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ID_MAX,
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};
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@ -93,7 +97,8 @@ static const char *clk_names[] = {
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[ID_MAINCK] = "mainck",
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[ID_PLL_U_DIV] = "upll_divpmcck",
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[ID_PLL_A_DIV] = "plla_divpmcck",
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[ID_MCK] = "mck",
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[ID_MCK_PRES] = "mck_pres",
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[ID_MCK_DIV] = "mck_div",
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};
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/* Fractional PLL output range. */
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@ -260,10 +265,10 @@ static const struct {
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u8 id;
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u8 cid;
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} sam9x60_systemck[] = {
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{ .n = "ddrck", .p = "mck", .id = 2, .cid = ID_DDR, },
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{ .n = "ddrck", .p = "mck_pres", .id = 2, .cid = ID_DDR, },
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{ .n = "pck0", .p = "prog0", .id = 8, .cid = ID_PCK0, },
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{ .n = "pck1", .p = "prog1", .id = 9, .cid = ID_PCK1, },
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{ .n = "qspick", .p = "mck", .id = 19, .cid = ID_QSPI, },
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{ .n = "qspick", .p = "mck_pres", .id = 19, .cid = ID_QSPI, },
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};
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/**
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@ -508,7 +513,7 @@ static int sam9x60_clk_probe(struct udevice *dev)
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clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, sam9x60_plls[i].cid), c);
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}
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/* Register MCK clock. */
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/* Register MCK pres clock. */
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p[0] = clk_names[ID_MD_SLCK];
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p[1] = clk_names[ID_MAINCK];
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p[2] = clk_names[ID_PLL_A_DIV];
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@ -519,25 +524,36 @@ static int sam9x60_clk_probe(struct udevice *dev)
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cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV);
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prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, 4,
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fail);
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c = at91_clk_register_master(base, clk_names[ID_MCK], p, 4, &mck_layout,
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&mck_characteristics, tmpclkmux);
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c = at91_clk_register_master_pres(base, clk_names[ID_MCK_PRES], p, 4,
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&mck_layout, &mck_characteristics,
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tmpclkmux);
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if (IS_ERR(c)) {
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ret = PTR_ERR(c);
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goto fail;
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}
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clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK), c);
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clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK_PRES), c);
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/* Register MCK div clock. */
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c = at91_clk_register_master_div(base, clk_names[ID_MCK_DIV],
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clk_names[ID_MCK_PRES],
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&mck_layout, &mck_characteristics);
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if (IS_ERR(c)) {
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ret = PTR_ERR(c);
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goto fail;
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}
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clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK_DIV), c);
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/* Register programmable clocks. */
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p[0] = clk_names[ID_MD_SLCK];
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p[1] = clk_names[ID_TD_SLCK];
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p[2] = clk_names[ID_MAINCK];
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p[3] = clk_names[ID_MCK];
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p[3] = clk_names[ID_MCK_DIV];
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p[4] = clk_names[ID_PLL_A_DIV];
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p[5] = clk_names[ID_PLL_U_DIV];
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cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK);
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cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK);
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cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK);
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cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK);
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cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK_DIV);
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cm[4] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_A_DIV);
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cm[5] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV);
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for (i = 0; i < ARRAY_SIZE(sam9x60_prog); i++) {
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@ -572,7 +588,7 @@ static int sam9x60_clk_probe(struct udevice *dev)
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for (i = 0; i < ARRAY_SIZE(sam9x60_periphck); i++) {
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c = at91_clk_register_sam9x5_peripheral(base, &pcr_layout,
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sam9x60_periphck[i].n,
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clk_names[ID_MCK],
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clk_names[ID_MCK_DIV],
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sam9x60_periphck[i].id,
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&r);
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if (IS_ERR(c)) {
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@ -587,7 +603,7 @@ static int sam9x60_clk_probe(struct udevice *dev)
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p[0] = clk_names[ID_MD_SLCK];
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p[1] = clk_names[ID_TD_SLCK];
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p[2] = clk_names[ID_MAINCK];
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p[3] = clk_names[ID_MCK];
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p[3] = clk_names[ID_MCK_DIV];
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p[4] = clk_names[ID_PLL_A_DIV];
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p[5] = clk_names[ID_PLL_U_DIV];
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m[0] = 0;
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@ -599,7 +615,7 @@ static int sam9x60_clk_probe(struct udevice *dev)
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cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK);
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cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK);
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cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK);
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cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK);
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cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK_DIV);
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cm[4] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_A_DIV);
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cm[5] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV);
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for (i = 0; i < ARRAY_SIZE(sam9x60_gck); i++) {
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@ -44,7 +44,8 @@
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* @ID_PLL_ETH_FRAC: Ethernet PLL fractional clock identifier
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* @ID_PLL_ETH_DIV: Ethernet PLL divider clock identifier
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* @ID_MCK0: MCK0 clock identifier
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* @ID_MCK0_PRES: MCK0 PRES clock identifier
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* @ID_MCK0_DIV: MCK0 DIV clock identifier
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* @ID_MCK1: MCK1 clock identifier
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* @ID_MCK2: MCK2 clock identifier
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* @ID_MCK3: MCK3 clock identifier
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@ -95,7 +96,7 @@ enum pmc_clk_ids {
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ID_PLL_ETH_FRAC = 20,
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ID_PLL_ETH_DIV = 21,
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ID_MCK0 = 22,
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ID_MCK0_DIV = 22,
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ID_MCK1 = 23,
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ID_MCK2 = 24,
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ID_MCK3 = 25,
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@ -121,6 +122,8 @@ enum pmc_clk_ids {
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ID_PCK6 = 42,
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ID_PCK7 = 43,
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ID_MCK0_PRES = 44,
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ID_MAX,
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};
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@ -147,7 +150,8 @@ static const char *clk_names[] = {
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[ID_PLL_AUDIO_DIVPMC] = "audiopll_divpmcck",
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[ID_PLL_AUDIO_DIVIO] = "audiopll_diviock",
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[ID_PLL_ETH_DIV] = "ethpll_divpmcck",
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[ID_MCK0] = "mck0",
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[ID_MCK0_DIV] = "mck0_div",
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[ID_MCK0_PRES] = "mck0_pres",
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};
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/* Fractional PLL output range. */
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@ -504,7 +508,7 @@ static const struct {
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struct clk_range r;
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u8 id;
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} sama7g5_periphck[] = {
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{ .n = "pioA_clk", .p = "mck0", .id = 11, },
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{ .n = "pioA_clk", .p = "mck0_div", .id = 11, },
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{ .n = "sfr_clk", .p = "mck1", .id = 19, },
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{ .n = "hsmc_clk", .p = "mck1", .id = 21, },
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{ .n = "xdmac0_clk", .p = "mck1", .id = 22, },
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@ -514,7 +518,7 @@ static const struct {
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{ .n = "aes_clk", .p = "mck1", .id = 27, },
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{ .n = "tzaesbasc_clk", .p = "mck1", .id = 28, },
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{ .n = "asrc_clk", .p = "mck1", .id = 30, .r = { .max = 200000000, }, },
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{ .n = "cpkcc_clk", .p = "mck0", .id = 32, },
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{ .n = "cpkcc_clk", .p = "mck0_div", .id = 32, },
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{ .n = "csi_clk", .p = "mck3", .id = 33, .r = { .max = 266000000, }, },
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{ .n = "csi2dc_clk", .p = "mck3", .id = 34, .r = { .max = 266000000, }, },
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{ .n = "eic_clk", .p = "mck1", .id = 37, },
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@ -1210,7 +1214,7 @@ static int sama7g5_clk_probe(struct udevice *dev)
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sama7g5_plls[i].c));
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}
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/* Register MCK0 clock. */
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/* Register MCK0_PRES clock. */
|
||||
p[0] = clk_names[ID_MD_SLCK];
|
||||
p[1] = clk_names[ID_MAINCK];
|
||||
p[2] = clk_names[ID_PLL_CPU_DIV];
|
||||
@ -1221,15 +1225,19 @@ static int sama7g5_clk_probe(struct udevice *dev)
|
||||
cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_SYS_DIV);
|
||||
prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, 2,
|
||||
fail);
|
||||
clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0),
|
||||
at91_clk_register_master(base, clk_names[ID_MCK0], p,
|
||||
clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_PRES),
|
||||
at91_clk_register_master_pres(base, clk_names[ID_MCK0_PRES], p,
|
||||
4, &mck0_layout, &mck0_characteristics, tmpclkmux));
|
||||
|
||||
clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV),
|
||||
at91_clk_register_master_div(base, clk_names[ID_MCK0_DIV],
|
||||
clk_names[ID_MCK0_PRES], &mck0_layout, &mck0_characteristics));
|
||||
|
||||
/* Register MCK1-4 clocks. */
|
||||
p[0] = clk_names[ID_MD_SLCK];
|
||||
p[1] = clk_names[ID_TD_SLCK];
|
||||
p[2] = clk_names[ID_MAINCK];
|
||||
p[3] = clk_names[ID_MCK0];
|
||||
p[3] = clk_names[ID_MCK0_DIV];
|
||||
m[0] = 0;
|
||||
m[1] = 1;
|
||||
m[2] = 2;
|
||||
@ -1237,7 +1245,7 @@ static int sama7g5_clk_probe(struct udevice *dev)
|
||||
cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK);
|
||||
cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK);
|
||||
cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK);
|
||||
cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0);
|
||||
cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV);
|
||||
for (i = 0; i < ARRAY_SIZE(sama7g5_mckx); i++) {
|
||||
for (j = 0; j < sama7g5_mckx[i].ep_count; j++) {
|
||||
p[4 + j] = sama7g5_mckx[i].ep[j];
|
||||
@ -1267,7 +1275,7 @@ static int sama7g5_clk_probe(struct udevice *dev)
|
||||
p[0] = clk_names[ID_MD_SLCK];
|
||||
p[1] = clk_names[ID_TD_SLCK];
|
||||
p[2] = clk_names[ID_MAINCK];
|
||||
p[3] = clk_names[ID_MCK0];
|
||||
p[3] = clk_names[ID_MCK0_DIV];
|
||||
p[4] = clk_names[ID_PLL_SYS_DIV];
|
||||
p[5] = clk_names[ID_PLL_DDR_DIV];
|
||||
p[6] = clk_names[ID_PLL_IMG_DIV];
|
||||
@ -1277,7 +1285,7 @@ static int sama7g5_clk_probe(struct udevice *dev)
|
||||
cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK);
|
||||
cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK);
|
||||
cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK);
|
||||
cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0);
|
||||
cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV);
|
||||
cm[4] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_SYS_DIV);
|
||||
cm[5] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_DDR_DIV);
|
||||
cm[6] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_IMG_DIV);
|
||||
@ -1315,7 +1323,7 @@ static int sama7g5_clk_probe(struct udevice *dev)
|
||||
p[0] = clk_names[ID_MD_SLCK];
|
||||
p[1] = clk_names[ID_TD_SLCK];
|
||||
p[2] = clk_names[ID_MAINCK];
|
||||
p[3] = clk_names[ID_MCK0];
|
||||
p[3] = clk_names[ID_MCK0_DIV];
|
||||
m[0] = 0;
|
||||
m[1] = 1;
|
||||
m[2] = 2;
|
||||
@ -1323,7 +1331,7 @@ static int sama7g5_clk_probe(struct udevice *dev)
|
||||
cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK);
|
||||
cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK);
|
||||
cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK);
|
||||
cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0);
|
||||
cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV);
|
||||
for (i = 0; i < ARRAY_SIZE(sama7g5_gck); i++) {
|
||||
for (j = 0; j < sama7g5_gck[i].ep_count; j++) {
|
||||
p[4 + j] = sama7g5_gck[i].ep[j];
|
||||
|
||||
Loading…
Reference in New Issue
Block a user