armv8: fsl-lsch3: Make CCN-504 related code conditional
LS2080 family has CCN-504 cache coherent interconnet. Other SoCs in LSCH3 family may have differnt interconnect. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message] Reviewed-by: York Sun <york.sun@nxp.com>
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@ -322,6 +322,10 @@ build a config tool - later.
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Defined For SoC that has cache coherent interconnect
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CCN-400
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CONFIG_SYS_FSL_HAS_CCN504
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Defined for SoC that has cache coherent interconnect CCN-504
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The following options need to be configured:
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- CPU Type: Define exactly one, e.g. CONFIG_MPC85XX.
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@ -61,6 +61,7 @@ config ARCH_LS2080A
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select SYS_FSL_DDR
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select SYS_FSL_DDR_LE
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select SYS_FSL_DDR_VER_50
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select SYS_FSL_HAS_CCN504
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select SYS_FSL_HAS_DP_DDR
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select SYS_FSL_HAS_SEC
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select SYS_FSL_HAS_DDR4
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@ -269,6 +270,9 @@ config SYS_FSL_IFC_BANK_COUNT
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config SYS_FSL_HAS_CCI400
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bool
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config SYS_FSL_HAS_CCN504
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bool
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config SYS_FSL_HAS_DP_DDR
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bool
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@ -76,7 +76,7 @@ ENTRY(lowlevel_init)
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switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
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1:
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#ifdef CONFIG_FSL_LSCH3
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#if defined (CONFIG_SYS_FSL_HAS_CCN504)
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/* Set Wuo bit for RN-I 20 */
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#ifdef CONFIG_ARCH_LS2080A
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@ -171,7 +171,7 @@ ENTRY(lowlevel_init)
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ldr x0, =CCI_S2_QOS_CONTROL_BASE(20)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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#endif
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#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
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#ifdef SMMU_BASE
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/* Set the SMMU page size in the sACR register */
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@ -338,7 +338,9 @@ get_svr:
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ldr x1, =FSL_LSCH3_SVR
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ldr w0, [x1]
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ret
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#endif
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#ifdef CONFIG_SYS_FSL_HAS_CCN504
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hnf_pstate_poll:
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/* x0 has the desired status, return 0 for success, 1 for timeout
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* clobber x1, x2, x3, x4, x6, x7
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@ -420,7 +422,7 @@ ENTRY(__asm_flush_l3_dcache)
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mov lr, x29
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ret
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ENDPROC(__asm_flush_l3_dcache)
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#endif
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#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
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#ifdef CONFIG_MP
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/* Keep literals not used by the secondary boot code outside it */
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