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dm: pci: Update uclass to support livetree

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Update the PCI uclass to support livetree. This mostly involves fixing
the address decoding from the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass 2017-05-18 20:09:51 -06:00
parent 40a475e841
commit bf501595cd
1 changed files with 12 additions and 14 deletions
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26
drivers/pci/pci-uclass.c
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@ -8,12 +8,11 @@
#include <common.h> #include <common.h>
#include <dm.h> #include <dm.h>
#include <errno.h> #include <errno.h>
#include <fdtdec.h>
#include <inttypes.h> #include <inttypes.h>
#include <pci.h> #include <pci.h>
#include <asm/io.h> #include <asm/io.h>
#include <dm/lists.h>
#include <dm/device-internal.h> #include <dm/device-internal.h>
#include <dm/lists.h>
#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP) #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
#include <asm/fsp/fsp_support.h> #include <asm/fsp/fsp_support.h>
#endif #endif
@ -754,8 +753,8 @@ error:
return ret; return ret;
} }
static int decode_regions(struct pci_controller *hose, const void *blob, static int decode_regions(struct pci_controller *hose, ofnode parent_node,
int parent_node, int node) ofnode node)
{ {
int pci_addr_cells, addr_cells, size_cells; int pci_addr_cells, addr_cells, size_cells;
phys_addr_t base = 0, size; phys_addr_t base = 0, size;
@ -764,12 +763,12 @@ static int decode_regions(struct pci_controller *hose, const void *blob,
int len; int len;
int i; int i;
prop = fdt_getprop(blob, node, "ranges", &len); prop = ofnode_read_prop(node, "ranges", &len);
if (!prop) if (!prop)
return -EINVAL; return -EINVAL;
pci_addr_cells = fdt_address_cells(blob, node); pci_addr_cells = ofnode_read_addr_cells(node);
addr_cells = fdt_address_cells(blob, parent_node); addr_cells = ofnode_read_addr_cells(parent_node);
size_cells = fdt_size_cells(blob, node); size_cells = ofnode_read_size_cells(node);
/* PCI addresses are always 3-cells */ /* PCI addresses are always 3-cells */
len /= sizeof(u32); len /= sizeof(u32);
@ -841,9 +840,8 @@ static int pci_uclass_pre_probe(struct udevice *bus)
/* For bridges, use the top-level PCI controller */ /* For bridges, use the top-level PCI controller */
if (!device_is_on_pci_bus(bus)) { if (!device_is_on_pci_bus(bus)) {
hose->ctlr = bus; hose->ctlr = bus;
ret = decode_regions(hose, gd->fdt_blob, ret = decode_regions(hose, dev_ofnode(bus->parent),
dev_of_offset(bus->parent), dev_ofnode(bus));
dev_of_offset(bus));
if (ret) { if (ret) {
debug("%s: Cannot decode regions\n", __func__); debug("%s: Cannot decode regions\n", __func__);
return ret; return ret;
@ -906,7 +904,7 @@ static int pci_uclass_child_post_bind(struct udevice *dev)
struct fdt_pci_addr addr; struct fdt_pci_addr addr;
int ret; int ret;
if (dev_of_offset(dev) == -1) if (!dev_of_valid(dev))
return 0; return 0;
/* /*
@ -914,8 +912,8 @@ static int pci_uclass_child_post_bind(struct udevice *dev)
* just check the address. * just check the address.
*/ */
pplat = dev_get_parent_platdata(dev); pplat = dev_get_parent_platdata(dev);
ret = fdtdec_get_pci_addr(gd->fdt_blob, dev_of_offset(dev), ret = ofnode_read_pci_addr(dev_ofnode(dev), FDT_PCI_SPACE_CONFIG, "reg",
FDT_PCI_SPACE_CONFIG, "reg", &addr); &addr);
if (ret) { if (ret) {
if (ret != -ENOENT) if (ret != -ENOENT)