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Merge branch 'master' of git://git.denx.de/u-boot-sunxi

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This commit is contained in:
Tom Rini
2015-02-02 10:11:44 -05:00
parent 358b8bc204 5abdb156bb
commit be8ddad9c8
47 changed files with 495 additions and 336 deletions
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2
arch/arm/cpu/armv7/sunxi/Makefile
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@@ -15,8 +15,10 @@ obj-y += pinmux.o
obj-y += usbc.o
obj-$(CONFIG_MACH_SUN6I) += prcm.o
obj-$(CONFIG_MACH_SUN8I) += prcm.o
obj-$(CONFIG_MACH_SUN9I) += prcm.o
obj-$(CONFIG_MACH_SUN6I) += p2wi.o
obj-$(CONFIG_MACH_SUN8I) += rsb.o
obj-$(CONFIG_MACH_SUN9I) += rsb.o
obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o

22
arch/arm/cpu/armv7/sunxi/rsb.c
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@@ -16,14 +16,27 @@
#include <asm/arch/prcm.h>
#include <asm/arch/rsb.h>
static int rsb_set_device_mode(void);
static void rsb_cfg_io(void)
{
#ifdef CONFIG_MACH_SUN8I
sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL0_R_RSB_SCK);
sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL1_R_RSB_SDA);
sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
#elif defined CONFIG_MACH_SUN9I
sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN0_R_RSB_SCK);
sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN1_R_RSB_SDA);
sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
#else
#error unsupported MACH_SUNXI
#endif
}
static void rsb_set_clk(void)
@@ -42,7 +55,7 @@ static void rsb_set_clk(void)
writel((cd_odly << 8) | div, &rsb->ccr);
}
void rsb_init(void)
int rsb_init(void)
{
struct sunxi_rsb_reg * const rsb =
(struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
@@ -54,6 +67,8 @@ void rsb_init(void)
writel(RSB_CTRL_SOFT_RST, &rsb->ctrl);
rsb_set_clk();
return rsb_set_device_mode();
}
static int rsb_await_trans(void)
@@ -88,13 +103,14 @@ static int rsb_await_trans(void)
return ret;
}
int rsb_set_device_mode(u32 device_mode_data)
static int rsb_set_device_mode(void)
{
struct sunxi_rsb_reg * const rsb =
(struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
unsigned long tmo = timer_get_us() + 1000000;
writel(RSB_DMCR_DEVICE_MODE_START | device_mode_data, &rsb->dmcr);
writel(RSB_DMCR_DEVICE_MODE_START | RSB_DMCR_DEVICE_MODE_DATA,
&rsb->dmcr);
while (readl(&rsb->dmcr) & RSB_DMCR_DEVICE_MODE_START) {
if (timer_get_us() > tmo)

2
arch/arm/include/asm/arch-sunxi/clock_sun4i.h
View File

@@ -305,6 +305,8 @@ struct sunxi_ccm_reg {
#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2)
#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2)
#define CCM_GMAC_CTRL_RX_CLK_DELAY(x) ((x) << 5)
#define CCM_GMAC_CTRL_TX_CLK_DELAY(x) ((x) << 10)
#define CCM_USB_CTRL_PHY0_RST (0x1 << 0)
#define CCM_USB_CTRL_PHY1_RST (0x1 << 1)

2
arch/arm/include/asm/arch-sunxi/clock_sun6i.h
View File

@@ -243,6 +243,8 @@ struct sunxi_ccm_reg {
#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2)
#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2)
#define CCM_GMAC_CTRL_RX_CLK_DELAY(x) ((x) << 5)
#define CCM_GMAC_CTRL_TX_CLK_DELAY(x) ((x) << 10)
#define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */

5
arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
View File

@@ -73,7 +73,6 @@
#define SUNXI_CCM_BASE (REGS_APB0_BASE + 0x0000)
#define SUNXI_CCMMODULE_BASE (REGS_APB0_BASE + 0x0400)
#define SUNXI_PIO_BASE (REGS_APB0_BASE + 0x0800)
#define SUNXI_R_PIO_BASE (0x08002C00)
#define SUNXI_TIMER_BASE (REGS_APB0_BASE + 0x0C00)
#define SUNXI_PWM_BASE (REGS_APB0_BASE + 0x1400)
#define SUNXI_LRADC_BASE (REGS_APB0_BASE + 0x1800)
@@ -92,8 +91,10 @@
#define SUNXI_TWI4_BASE (REGS_APB1_BASE + 0x3800)
/* RCPUS Module */
#define SUNXI_RPRCM_BASE (REGS_RCPUS_BASE + 0x1400)
#define SUNXI_PRCM_BASE (REGS_RCPUS_BASE + 0x1400)
#define SUNXI_R_UART_BASE (REGS_RCPUS_BASE + 0x2800)
#define SUNXI_R_PIO_BASE (REGS_RCPUS_BASE + 0x2c00)
#define SUNXI_RSB_BASE (REGS_RCPUS_BASE + 0x3400)
/* Misc. */
#define SUNXI_BROM_BASE 0xFFFF0000 /* 32K */

9
arch/arm/include/asm/arch-sunxi/gpio.h
View File

@@ -45,9 +45,13 @@
*
* sun8i has 1 bank:
* PL0 - PL11
*
* sun9i has 3 banks:
* PL0 - PL9 | PM0 - PM15 | PN0 - PN1
*/
#define SUNXI_GPIO_L 11
#define SUNXI_GPIO_M 12
#define SUNXI_GPIO_N 13
struct sunxi_gpio {
u32 cfg[4];
@@ -114,6 +118,7 @@ enum sunxi_gpio_number {
SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H),
SUNXI_GPIO_L_START = 352,
SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L),
SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M),
SUNXI_GPIO_AXP0_START = 1024,
};
@@ -129,6 +134,7 @@ enum sunxi_gpio_number {
#define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr))
#define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr))
#define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr))
#define SUNXI_GPN(_nr) (SUNXI_GPIO_N_START + (_nr))
#define SUNXI_GPAXP0(_nr) (SUNXI_GPIO_AXP0_START + (_nr))
@@ -187,6 +193,9 @@ enum sunxi_gpio_number {
#define SUN8I_GPL2_R_UART_TX 2
#define SUN8I_GPL3_R_UART_RX 2
#define SUN9I_GPN0_R_RSB_SCK 3
#define SUN9I_GPN1_R_RSB_SDA 3
/* GPIO pin pull-up/down config */
#define SUNXI_GPIO_PULL_DISABLE 0
#define SUNXI_GPIO_PULL_UP 1

4
arch/arm/include/asm/arch-sunxi/rsb.h
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@@ -37,6 +37,7 @@ struct sunxi_rsb_reg {
#define RSB_STAT_TERR_INT (1 << 1)
#define RSB_STAT_LBSY_INT (1 << 2)
#define RSB_DMCR_DEVICE_MODE_DATA 0x7c3e00
#define RSB_DMCR_DEVICE_MODE_START (1 << 31)
#define RSB_CMD_BYTE_WRITE 0x4e
@@ -46,8 +47,7 @@ struct sunxi_rsb_reg {
#define RSB_DEVADDR_RUNTIME_ADDR(x) ((x) << 16)
#define RSB_DEVADDR_DEVICE_ADDR(x) ((x) << 0)
void rsb_init(void);
int rsb_set_device_mode(u32 device_mode_data);
int rsb_init(void);
int rsb_set_device_address(u16 device_addr, u16 runtime_addr);
int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data);
int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data);