Merge tag 'u-boot-imx-20200609' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

Fixes for 2020.07
-----------------

- mx53: mx53menlo Convert to DM_ETH, fix fail boot
- imx8mp_evk: fix boot issue
- MX6, display5: fix environment
- drop warnings (watchdog) for i.MX8mm i.mx8mp
- enable bootaux for i.MX8M

Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/695929999

arch/arm/dts/imx53-m53menlo.dts

@@ -86,8 +86,19 @@
 &fec {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_fec>;
+	phy-handle = <&ethphy0>;
 	phy-mode = "rmii";
 	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+		};
+	};
 };
 
 &i2c1 {

arch/arm/dts/imxrt1050.dtsi

@@ -147,12 +147,12 @@
 		};
 
 		lcdif: lcdif@402b8000 {
-		    compatible = "fsl,imxrt-lcdif";
-		    reg = <0x402b8000 0x10000>;
-		    interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
-		    clocks = <&clks IMXRT1050_CLK_LCDIF>;
-		    clock-names = "per";
-		    status = "disabled";
+			compatible = "fsl,imxrt-lcdif";
+			reg = <0x402b8000 0x4000>;
+			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clks IMXRT1050_CLK_LCDIF>;
+			clock-names = "per";
+			status = "disabled";
 		};
 	};
 };

arch/arm/include/asm/arch-mx7/imx-regs.h

@@ -274,6 +274,7 @@ struct src {
 
 #define SRC_DDRC_RCR_DDRC_CORE_RST_OFFSET	1
 #define SRC_DDRC_RCR_DDRC_CORE_RST_MASK		(1 << 1)
+#define SRC_DDRC_RCR_DDRC_PRST_MASK		(1 << 0)
 
 /* GPR0 Bit Fields */
 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK     0x1u

arch/arm/mach-imx/Kconfig

@@ -23,7 +23,7 @@ config IMX_RDC
 
 config IMX_BOOTAUX
 	bool "Support boot auxiliary core"
-	depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610
+	depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610 || ARCH_IMX8M
 	help
 	  bootaux [addr] to boot auxiliary core.
 

arch/arm/mach-imx/mkimage_fit_atf.sh

@@ -62,6 +62,23 @@ cat << __HEADER_EOF
 			compression = "none";
 			load = <$BL33_LOAD_ADDR>;
 		};
+__HEADER_EOF
+
+cnt=1
+for dtname in $*
+do
+	cat << __FDT_IMAGE_EOF
+		fdt@$cnt {
+			description = "$(basename $dtname .dtb)";
+			data = /incbin/("$dtname");
+			type = "flat_dt";
+			compression = "none";
+		};
+__FDT_IMAGE_EOF
+cnt=$((cnt+1))
+done
+
+cat << __HEADER_EOF
 		atf@1 {
 			description = "ARM Trusted Firmware";
 			os = "arm-trusted-firmware";
@@ -88,20 +105,6 @@ cat << __HEADER_EOF
 __HEADER_EOF
 fi
 
-cnt=1
-for dtname in $*
-do
-	cat << __FDT_IMAGE_EOF
-		fdt@$cnt {
-			description = "$(basename $dtname .dtb)";
-			data = /incbin/("$dtname");
-			type = "flat_dt";
-			compression = "none";
-		};
-__FDT_IMAGE_EOF
-cnt=$((cnt+1))
-done
-
 cat << __CONF_HEADER_EOF
 	};
 	configurations {

arch/arm/mach-imx/mx7/ddr.c

@@ -13,6 +13,7 @@
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/mx7-ddr.h>
 #include <common.h>
+#include <linux/delay.h>
 
 /*
  * Routine: mx7_dram_cfg
@@ -37,8 +38,23 @@ void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
 		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
 	int i;
 
-	/* Assert DDR Controller preset and DDR PHY reset */
-	writel(SRC_DDRC_RCR_DDRC_CORE_RST_MASK, &src_regs->ddrc_rcr);
+	/*
+	 * iMX7D RM 9.2.4.9.3 Power removal flow Table 9-11. Re-enabling power
+	 * row 2 says "Reset controller / PHY by driving core_ddrc_rst = 0 ,
+	 * aresetn_n = 0, presetn = 0. That means reset everything.
+	 */
+	writel(SRC_DDRC_RCR_DDRC_CORE_RST_MASK | SRC_DDRC_RCR_DDRC_PRST_MASK,
+	       &src_regs->ddrc_rcr);
+
+	/*
+	 * iMX7D RM 6.2.7.26 SRC_DDRC_RCR says wait 30 cycles (of unknown).
+	 * If we assume this is 30 cycles at 100 MHz (about the rate of a
+	 * DRAM bus), that's 300 nS, so waiting 10 uS is more then plenty.
+	 */
+	udelay(10);
+
+	/* De-assert DDR Controller 'preset' and DDR PHY reset */
+	clrbits_le32(&src_regs->ddrc_rcr, SRC_DDRC_RCR_DDRC_PRST_MASK);
 
 	/* DDR controller configuration */
 	writel(ddrc_regs_val->mstr, &ddrc_regs->mstr);
@@ -71,7 +87,7 @@ void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
 	writel(ddrc_regs_val->odtcfg, &ddrc_regs->odtcfg);
 	writel(ddrc_regs_val->odtmap, &ddrc_regs->odtmap);
 
-	/* De-assert DDR Controller preset and DDR PHY reset */
+	/* De-assert DDR Controller 'core_ddrc_rstn' and 'aresetn' */
 	clrbits_le32(&src_regs->ddrc_rcr, SRC_DDRC_RCR_DDRC_CORE_RST_MASK);
 
 	/* PHY configuration */