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fsl-ddr: add the override for write leveling

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add the override for write leveling sampling and
start time according to specific board.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Dave Liu 2009-12-16 10:24:37 -06:00 committed by Kumar Gala
parent 0a71c92c7e
commit bdc9f7b5ea
3 changed files with 21 additions and 7 deletions
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20
cpu/mpc8xxx/ddr/ctrl_regs.c
View File

@ -1002,8 +1002,8 @@ static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
} }
/* DDR Write Leveling Control (DDR_WRLVL_CNTL) */ /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
unsigned int wrlvl_en) const memctl_options_t *popts)
{ {
/* /*
* First DQS pulse rising edge after margining mode * First DQS pulse rising edge after margining mode
@ -1030,8 +1030,9 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr,
/* tWL_DQSEN min = 25 nCK, we set it 32 */ /* tWL_DQSEN min = 25 nCK, we set it 32 */
wrlvl_dqsen = 0x5; wrlvl_dqsen = 0x5;
/* /*
* Write leveling sample time at least need 14 clocks * Write leveling sample time at least need 6 clocks
* due to tWLO = 9, we set it 15 clocks * higher than tWLO to allow enough time for progagation
* delay and sampling the prime data bits.
*/ */
wrlvl_smpl = 0xf; wrlvl_smpl = 0xf;
/* /*
@ -1044,9 +1045,16 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr,
* Write leveling start time * Write leveling start time
* The value use for the DQS_ADJUST for the first sample * The value use for the DQS_ADJUST for the first sample
* when write leveling is enabled. * when write leveling is enabled.
* we set it 1 clock delay
*/ */
wrlvl_start = 0x8; wrlvl_start = 0x8;
/*
* Override the write leveling sample and start time
* according to specific board
*/
if (popts->wrlvl_override) {
wrlvl_smpl = popts->wrlvl_sample;
wrlvl_start = popts->wrlvl_start;
}
} }
ddr->ddr_wrlvl_cntl = (0 ddr->ddr_wrlvl_cntl = (0
@ -1332,7 +1340,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
set_timing_cfg_5(ddr); set_timing_cfg_5(ddr);
set_ddr_zq_cntl(ddr, zq_en); set_ddr_zq_cntl(ddr, zq_en);
set_ddr_wrlvl_cntl(ddr, wrlvl_en); set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
set_ddr_sr_cntr(ddr, sr_it); set_ddr_sr_cntr(ddr, sr_it);

1
cpu/mpc8xxx/ddr/options.c
View File

@ -198,6 +198,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
* meet the tQDSS under different loading. * meet the tQDSS under different loading.
*/ */
popts->wrlvl_en = 1; popts->wrlvl_en = 1;
popts->wrlvl_override = 0;
#endif #endif
/* /*

7
include/asm-ppc/fsl_ddr_sdram.h
View File

@ -1,5 +1,5 @@
/* /*
* Copyright 2008 Freescale Semiconductor, Inc. * Copyright 2008-2009 Freescale Semiconductor, Inc.
* *
* This program is free software; you can redistribute it and/or * This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License * modify it under the terms of the GNU General Public License
@ -177,6 +177,11 @@ typedef struct memctl_options_s {
unsigned int clk_adjust; /* */ unsigned int clk_adjust; /* */
unsigned int cpo_override; unsigned int cpo_override;
unsigned int write_data_delay; /* DQS adjust */ unsigned int write_data_delay; /* DQS adjust */
unsigned int wrlvl_override;
unsigned int wrlvl_sample; /* Write leveling */
unsigned int wrlvl_start;
unsigned int half_strength_driver_enable; unsigned int half_strength_driver_enable;
unsigned int twoT_en; unsigned int twoT_en;
unsigned int threeT_en; unsigned int threeT_en;