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riscv: andes_plic.c: use modified IPI scheme

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The IPI scheme in OpenSBI has been updated to support 8-core AE350
platform, the plicsw configuration needs to be modified accordingly.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
This commit is contained in:
Yu Chien Peter Lin 2022-10-14 15:00:18 +08:00 committed by Leo Yu-Chi Liang
parent cb052d7712
commit bdb238355c
1 changed files with 4 additions and 3 deletions
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7
arch/riscv/lib/andes_plic.c
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@ -27,8 +27,8 @@
/* claim register */
#define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000)
#define ENABLE_HART_IPI (0x80808080)
#define SEND_IPI_TO_HART(hart) (0x80 >> (hart))
#define ENABLE_HART_IPI (0x01010101)
#define SEND_IPI_TO_HART(hart) (0x1 << (hart))
DECLARE_GLOBAL_DATA_PTR;
@ -36,8 +36,9 @@ static int enable_ipi(int hart)
{
unsigned int en;
en = ENABLE_HART_IPI >> hart;
en = ENABLE_HART_IPI << hart;
writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart));
writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic + 0x4, hart));
return 0;
}