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ARM: socfpga: Fix Arria10 SPI and NAND U-Boot offset

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The SPL size on Gen5 is 4*64kiB, but on A10 it is 4*256kiB.
Handle the difference.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
This commit is contained in:
Marek Vasut 2018-05-08 18:44:43 +02:00
parent 60082d3b3f
commit bd6363a7b7
1 changed files with 8 additions and 0 deletions
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8
include/configs/socfpga_common.h
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@ -275,12 +275,20 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
/* SPL QSPI boot support */
#ifdef CONFIG_SPL_SPI_SUPPORT
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000
#endif
#endif
/* SPL NAND boot support */
#ifdef CONFIG_SPL_NAND_SUPPORT
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000
#endif
#endif
/*