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rockchip: rk3399: move SoC setting into arch_cpu_init()

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SoC setting like DDR secure region and EMMC clock setting
should go to arch_cpu_init().

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Kever Yang
2019-07-22 19:59:38 +08:00
parent 08f7905bc6
commit bd06a7c88e
2 changed files with 27 additions and 23 deletions
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27
arch/arm/mach-rockchip/rk3399-board-spl.c
View File

@@ -16,7 +16,6 @@
#include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk3399.h> #include <asm/arch-rockchip/cru_rk3399.h>
#include <asm/arch-rockchip/grf_rk3399.h>
#include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/periph.h> #include <asm/arch-rockchip/periph.h>
#include <asm/arch-rockchip/sys_proto.h> #include <asm/arch-rockchip/sys_proto.h>
@@ -65,11 +64,14 @@ __weak void rockchip_stimer_init(void)
{ {
} }
__weak int arch_cpu_init(void)
{
return 0;
}
void board_init_f(ulong dummy) void board_init_f(ulong dummy)
{ {
struct udevice *dev; struct udevice *dev;
struct rk3399_pmusgrf_regs *sgrf;
struct rk3399_grf_regs *grf;
int ret; int ret;
#ifdef CONFIG_DEBUG_UART #ifdef CONFIG_DEBUG_UART
@@ -100,29 +102,14 @@ void board_init_f(ulong dummy)
debug("U-Boot SPL board init\n"); debug("U-Boot SPL board init\n");
#endif #endif
arch_cpu_init();
ret = spl_early_init(); ret = spl_early_init();
if (ret) { if (ret) {
debug("spl_early_init() failed: %d\n", ret); debug("spl_early_init() failed: %d\n", ret);
hang(); hang();
} }
/*
* Disable DDR and SRAM security regions.
*
* As we are entered from the BootROM, the region from
* 0x0 through 0xfffff (i.e. the first MB of memory) will
* be protected. This will cause issues with the DW_MMC
* driver, which tries to DMA from/to the stack (likely)
* located in this range.
*/
sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
/* eMMC clock generator: disable the clock multipilier */
grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
rk_clrreg(&grf->emmccore_con[11], 0x0ff);
rockchip_stimer_init(); rockchip_stimer_init();
ret = uclass_get_device(UCLASS_RAM, 0, &dev); ret = uclass_get_device(UCLASS_RAM, 0, &dev);

23
arch/arm/mach-rockchip/rk3399/rk3399.c
View File

@@ -80,11 +80,28 @@ int dram_init_banksize(void)
int arch_cpu_init(void) int arch_cpu_init(void)
{ {
/* We do some SoC one time setting here. */
struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
/* Emmc clock generator: disable the clock multipilier */ #ifdef CONFIG_SPL_BUILD
struct rk3399_pmusgrf_regs *sgrf;
struct rk3399_grf_regs *grf;
/*
* Disable DDR and SRAM security regions.
*
* As we are entered from the BootROM, the region from
* 0x0 through 0xfffff (i.e. the first MB of memory) will
* be protected. This will cause issues with the DW_MMC
* driver, which tries to DMA from/to the stack (likely)
* located in this range.
*/
sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
/* eMMC clock generator: disable the clock multipilier */
grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
rk_clrreg(&grf->emmccore_con[11], 0x0ff); rk_clrreg(&grf->emmccore_con[11], 0x0ff);
#endif
return 0; return 0;
} }