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net: zynq_gem: Remove check for Versal

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This patch removes check for Versal platform
in gem driver as it now supports clock setting
through clock framework.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Siva Durga Prasad Paladugu
2019-07-01 12:19:25 +05:30
committed by Michal Simek
parent 95105089af
commit bc493d911e
1 changed files with 0 additions and 4 deletions
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4
drivers/net/zynq_gem.c
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@@ -463,7 +463,6 @@ static int zynq_gem_init(struct udevice *dev)
break; break;
} }
#if !defined(CONFIG_ARCH_VERSAL)
ret = clk_set_rate(&priv->clk, clk_rate); ret = clk_set_rate(&priv->clk, clk_rate);
if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) { if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
dev_err(dev, "failed to set tx clock rate\n"); dev_err(dev, "failed to set tx clock rate\n");
@@ -475,9 +474,6 @@ static int zynq_gem_init(struct udevice *dev)
dev_err(dev, "failed to enable tx clock\n"); dev_err(dev, "failed to enable tx clock\n");
return ret; return ret;
} }
#else
debug("requested clk_rate %ld\n", clk_rate);
#endif
setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
ZYNQ_GEM_NWCTRL_TXEN_MASK); ZYNQ_GEM_NWCTRL_TXEN_MASK);