arm: Remove edb9315a board
These boards have not been converted to CONFIG_DM_USB by the deadline and is also missing conversion to CONFIG_DM. Remove it. This is also the last PL010_SERIAL using board, so remove those references. Cc: Sergey Kostanbaev <sergey.kostanbaev@fairwaves.ru> Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
parent
f4a6f75b48
commit
bc08dc563e
4
README
4
README
@ -629,10 +629,6 @@ The following options need to be configured:
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controller register space
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- Serial Ports:
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CONFIG_PL010_SERIAL
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Define this if you want support for Amba PrimeCell PL010 UARTs.
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CONFIG_PL011_SERIAL
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Define this if you want support for Amba PrimeCell PL011 UARTs.
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@ -525,12 +525,6 @@ config ARCH_AT91
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select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
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select SPL_SEPARATE_BSS if SPL
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config TARGET_EDB93XX
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bool "Support edb93xx"
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select CPU_ARM920T
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select GPIO_EXTRA_HEADER
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select PL010_SERIAL
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config TARGET_ASPENITE
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bool "Support aspenite"
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select CPU_ARM926EJS
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@ -2106,7 +2100,6 @@ source "board/broadcom/bcm968360bg/Kconfig"
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source "board/broadcom/bcm968580xref/Kconfig"
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source "board/broadcom/bcmns3/Kconfig"
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source "board/cavium/thunderx/Kconfig"
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source "board/cirrus/edb93xx/Kconfig"
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source "board/eets/pdu001/Kconfig"
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source "board/emulation/qemu-arm/Kconfig"
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source "board/freescale/ls2080aqds/Kconfig"
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@ -1,15 +0,0 @@
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if TARGET_EDB93XX
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config SYS_BOARD
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default "edb93xx"
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config SYS_VENDOR
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default "cirrus"
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config SYS_SOC
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default "ep93xx"
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config SYS_CONFIG_NAME
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default "edb93xx"
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endif
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@ -1,6 +0,0 @@
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EDB93XX BOARD
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M: Sergey Kostanbaev <sergey.kostanbaev@fairwaves.ru>
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S: Maintained
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F: board/cirrus/edb93xx/
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F: include/configs/edb93xx.h
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F: configs/edb9315a_defconfig
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@ -1,10 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2013
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# Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
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#
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# (C) Copyright 2003-2006
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# Wolfgang Denk, DENX Software Engineering, wd <at> denx.de.
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#
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obj-y := edb93xx.o
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@ -1,292 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Board initialization for EP93xx
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*
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* Copyright (C) 2013
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* Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
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*
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* Copyright (C) 2009
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* Matthias Kaehlcke <matthias <at> kaehlcke.net>
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*
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* (C) Copyright 2002 2003
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* Network Audio Technologies, Inc. <www.netaudiotech.com>
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* Adam Bezanson <bezanson <at> netaudiotech.com>
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*/
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#include <config.h>
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#include <common.h>
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#include <cpu_func.h>
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#include <init.h>
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#include <irq_func.h>
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#include <net.h>
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#include <netdev.h>
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#include <status_led.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/mach-types.h>
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#include <asm/arch/ep93xx.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* usb_div: 4, nbyp2: 1, pll2_en: 1
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* pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000,
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* pll2_x2: 384000000.000000, pll2_out: 192000000.000000
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*/
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#define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
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24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
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24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
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1 << SYSCON_CLKSET_PLL_PS_SHIFT | \
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SYSCON_CLKSET2_PLL2_EN | \
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SYSCON_CLKSET2_NBYP2 | \
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3 << SYSCON_CLKSET2_USB_DIV_SHIFT)
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#define SMC_BCR6_VALUE (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \
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SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \
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1 << SMC_BCR_MW_SHIFT)
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/* delay execution before timers are initialized */
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static inline void early_udelay(uint32_t usecs)
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{
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/* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */
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register uint32_t loops = (usecs * 1000) / 20;
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__asm__ volatile ("1:\n"
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"subs %0, %1, #1\n"
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"bne 1b" : "=r" (loops) : "0" (loops));
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}
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#ifndef CONFIG_EP93XX_NO_FLASH_CFG
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static void flash_cfg(void)
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{
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struct smc_regs *smc = (struct smc_regs *)SMC_BASE;
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writel(SMC_BCR6_VALUE, &smc->bcr6);
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}
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#else
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#define flash_cfg()
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#endif
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int board_init(void)
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{
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/*
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* Setup PLL2, PPL1 has been set during lowlevel init
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*/
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struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
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writel(CLKSET2_VAL, &syscon->clkset2);
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/*
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* the user's guide recommends to wait at least 1 ms for PLL2 to
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* stabilize
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*/
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early_udelay(1000);
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/* Go to Async mode */
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__asm__ volatile ("mrc p15, 0, r0, c1, c0, 0");
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__asm__ volatile ("orr r0, r0, #0xc0000000");
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__asm__ volatile ("mcr p15, 0, r0, c1, c0, 0");
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icache_enable();
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#ifdef USE_920T_MMU
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dcache_enable();
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#endif
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/* Machine number, as defined in linux/arch/arm/tools/mach-types */
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gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
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/* We have a console */
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gd->have_console = 1;
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enable_interrupts();
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flash_cfg();
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green_led_on();
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red_led_off();
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return 0;
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}
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int board_early_init_f(void)
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{
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/*
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* set UARTBAUD bit to drive UARTs with 14.7456MHz instead of
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* 14.7456/2 MHz
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*/
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struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
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writel(SYSCON_PWRCNT_UART_BAUD, &syscon->pwrcnt);
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return 0;
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}
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int board_eth_init(struct bd_info *bd)
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{
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return ep93xx_eth_initialize(0, MAC_BASE);
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}
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static void dram_fill_bank_addr(unsigned dram_addr_mask, unsigned dram_bank_cnt,
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unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS])
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{
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if (dram_bank_cnt == 1) {
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dram_bank_base[0] = PHYS_SDRAM_1;
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} else {
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/* Table lookup for holes in address space. Maximum memory
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* for the single SDCS may be up to 256Mb. We start scanning
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* banks from 1Mb, so it could be up to 128 banks theoretically.
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* We need at maximum 7 bits for the loockup, 8 slots is
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* enough for the worst case.
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*/
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unsigned tbl[8];
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unsigned i = dram_bank_cnt / 2;
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unsigned j = 0x00100000; /* 1 Mb */
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unsigned *ptbl = tbl;
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do {
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while (!(dram_addr_mask & j)) {
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j <<= 1;
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}
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*ptbl++ = j;
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j <<= 1;
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i >>= 1;
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} while (i != 0);
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for (i = dram_bank_cnt, j = 0;
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(i != 0) && (j < CONFIG_NR_DRAM_BANKS); --i, ++j) {
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unsigned addr = PHYS_SDRAM_1;
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unsigned k;
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unsigned bit;
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for (k = 0, bit = 1; k < 8; k++, bit <<= 1) {
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if (bit & j)
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addr |= tbl[k];
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}
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dram_bank_base[j] = addr;
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}
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}
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}
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/* called in board_init_f (before relocation) */
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static unsigned dram_init_banksize_int(int print)
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{
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/*
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* Collect information of banks that has been filled during lowlevel
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* initialization
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*/
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unsigned i;
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unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS];
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unsigned dram_total = 0;
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unsigned dram_bank_size = *(unsigned *)
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(PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_SIZE);
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unsigned dram_addr_mask = *(unsigned *)
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(PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_MASK);
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unsigned dram_bank_cnt = *(unsigned *)
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(PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_COUNT);
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dram_fill_bank_addr(dram_addr_mask, dram_bank_cnt, dram_bank_base);
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for (i = 0; i < dram_bank_cnt; i++) {
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gd->bd->bi_dram[i].start = dram_bank_base[i];
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gd->bd->bi_dram[i].size = dram_bank_size;
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dram_total += dram_bank_size;
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}
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for (; i < CONFIG_NR_DRAM_BANKS; i++) {
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gd->bd->bi_dram[i].start = 0;
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gd->bd->bi_dram[i].size = 0;
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}
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if (print) {
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printf("DRAM mask: %08x\n", dram_addr_mask);
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printf("DRAM total %u banks:\n", dram_bank_cnt);
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printf("bank base-address size\n");
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if (dram_bank_cnt > CONFIG_NR_DRAM_BANKS) {
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printf("WARNING! UBoot was configured for %u banks,\n"
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"but %u has been found. "
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"Supressing extra memory banks\n",
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CONFIG_NR_DRAM_BANKS, dram_bank_cnt);
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dram_bank_cnt = CONFIG_NR_DRAM_BANKS;
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}
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for (i = 0; i < dram_bank_cnt; i++) {
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printf(" %u %08x %08x\n",
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i, dram_bank_base[i], dram_bank_size);
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}
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printf(" ------------------------------------------\n"
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"Total %9d\n\n",
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dram_total);
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}
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return dram_total;
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}
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int dram_init_banksize(void)
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{
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dram_init_banksize_int(0);
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return 0;
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}
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/* called in board_init_f (before relocation) */
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int dram_init(void)
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{
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struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
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unsigned sec_id = readl(SECURITY_EXTENSIONID);
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unsigned chip_id = readl(&syscon->chipid);
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printf("CPU: Cirrus Logic ");
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switch (sec_id & 0x000001FE) {
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case 0x00000008:
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printf("EP9301");
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break;
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case 0x00000004:
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printf("EP9307");
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break;
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case 0x00000002:
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printf("EP931x");
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break;
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case 0x00000000:
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printf("EP9315");
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break;
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default:
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printf("<unknown>");
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break;
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}
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printf(" - Rev. ");
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switch (chip_id & 0xF0000000) {
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case 0x00000000:
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printf("A");
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break;
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case 0x10000000:
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printf("B");
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break;
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case 0x20000000:
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printf("C");
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break;
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case 0x30000000:
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printf("D0");
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break;
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case 0x40000000:
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printf("D1");
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break;
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case 0x50000000:
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printf("E0");
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break;
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case 0x60000000:
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printf("E1");
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break;
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case 0x70000000:
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printf("E2");
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break;
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default:
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printf("?");
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break;
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}
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printf(" (SecExtID=%.8x/ChipID=%.8x)\n", sec_id, chip_id);
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gd->ram_size = dram_init_banksize_int(1);
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return 0;
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}
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@ -1,115 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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*
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* Copyright (C) 2013
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* Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
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*
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* Copyright (c) 2004-2008 Texas Instruments
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*
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* (C) Copyright 2002
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
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*/
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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ENTRY(_start)
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SECTIONS
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{
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. = 0x00000000;
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. = ALIGN(4);
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.text : {
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*(.__image_copy_start)
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*(.vectors)
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arch/arm/cpu/arm920t/start.o (.text*)
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. = 0x1000;
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LONG(0x53555243)
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*(.text*)
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}
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. = ALIGN(4);
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.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
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. = ALIGN(4);
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.data : {
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*(.data*)
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}
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. = ALIGN(4);
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. = .;
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. = ALIGN(4);
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.u_boot_list : {
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KEEP(*(SORT(.u_boot_list*)));
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}
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. = ALIGN(4);
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.image_copy_end :
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{
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*(.__image_copy_end)
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}
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.rel_dyn_start :
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{
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*(.__rel_dyn_start)
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}
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.rel.dyn : {
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*(.rel*)
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}
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.rel_dyn_end :
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{
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*(.__rel_dyn_end)
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}
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.end :
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{
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*(.__end)
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}
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_image_binary_end = .;
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/*
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* Deprecated: this MMU section is used by pxa at present but
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* should not be used by new boards/CPUs.
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*/
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. = ALIGN(4096);
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.mmutable : {
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*(.mmutable)
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}
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/*
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* Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
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* __bss_base and __bss_limit are for linker only (overlay ordering)
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*/
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.bss_start __rel_dyn_start (OVERLAY) : {
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KEEP(*(.__bss_start));
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__bss_base = .;
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}
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.bss __bss_base (OVERLAY) : {
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*(.bss*)
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. = ALIGN(4);
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__bss_limit = .;
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}
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.bss_end __bss_limit (OVERLAY) : {
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KEEP(*(.__bss_end));
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}
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.dynsym _image_binary_end : { *(.dynsym) }
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.dynbss : { *(.dynbss) }
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.dynstr : { *(.dynstr*) }
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.dynamic : { *(.dynamic*) }
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.plt : { *(.plt*) }
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.interp : { *(.interp*) }
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.gnu.hash : { *(.gnu.hash) }
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.gnu : { *(.gnu*) }
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.ARM.exidx : { *(.ARM.exidx*) }
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.gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) }
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}
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@ -1,54 +0,0 @@
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CONFIG_ARM=y
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CONFIG_TARGET_EDB93XX=y
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CONFIG_SYS_TEXT_BASE=0x60000000
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CONFIG_NR_DRAM_BANKS=8
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CONFIG_ENV_SIZE=0x20000
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CONFIG_ENV_SECT_SIZE=0x20000
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CONFIG_SYS_EXTRA_OPTIONS="MK_edb9315a"
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="root=/dev/nfs console=ttyAM0,115200 ip=dhcp"
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# CONFIG_DISPLAY_CPUINFO is not set
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# CONFIG_DISPLAY_BOARDINFO is not set
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
# CONFIG_CMDLINE_EDITING is not set
|
||||
# CONFIG_AUTO_COMPLETE is not set
|
||||
CONFIG_SYS_PROMPT="EDB9315A> "
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_IMLS=y
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_JFFS2=y
|
||||
# CONFIG_DOS_PARTITION is not set
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
CONFIG_ENV_ADDR=0x60040000
|
||||
CONFIG_ENV_ADDR_REDUND=0x60060000
|
||||
CONFIG_LED_STATUS=y
|
||||
CONFIG_LED_STATUS0=y
|
||||
CONFIG_LED_STATUS_BIT=0
|
||||
CONFIG_LED_STATUS_STATE=2
|
||||
CONFIG_LED_STATUS1=y
|
||||
CONFIG_LED_STATUS_BIT1=1
|
||||
CONFIG_LED_STATUS_BOOT_ENABLE=y
|
||||
CONFIG_LED_STATUS_BOOT=0
|
||||
CONFIG_LED_STATUS_RED_ENABLE=y
|
||||
CONFIG_LED_STATUS_RED=1
|
||||
CONFIG_LED_STATUS_GREEN_ENABLE=y
|
||||
CONFIG_LED_STATUS_GREEN=0
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_PROTECTION=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_CONS_INDEX=0
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
@ -332,7 +332,7 @@ config DEBUG_UART_APBUART
|
||||
|
||||
config DEBUG_UART_PL010
|
||||
bool "pl010"
|
||||
depends on PL01X_SERIAL || PL010_SERIAL
|
||||
depends on PL01X_SERIAL
|
||||
help
|
||||
Select this to enable a debug UART using the pl01x driver with the
|
||||
PL010 UART type. You will need to provide parameters to make this
|
||||
@ -695,12 +695,6 @@ config INTEL_MID_SERIAL
|
||||
Select this to enable a UART for Intel MID platforms.
|
||||
This uses the ns16550 driver as a library.
|
||||
|
||||
config PL010_SERIAL
|
||||
bool "ARM PL010 driver"
|
||||
depends on !DM_SERIAL
|
||||
help
|
||||
Select this to enable a UART for platforms using PL010.
|
||||
|
||||
config PL011_SERIAL
|
||||
bool "ARM PL011 driver"
|
||||
depends on !DM_SERIAL
|
||||
|
||||
@ -24,7 +24,6 @@ endif
|
||||
ifdef CONFIG_DM_SERIAL
|
||||
obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o
|
||||
else
|
||||
obj-$(CONFIG_PL010_SERIAL) += serial_pl01x.o
|
||||
obj-$(CONFIG_PL011_SERIAL) += serial_pl01x.o
|
||||
obj-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o
|
||||
endif
|
||||
|
||||
@ -191,9 +191,7 @@ static void pl01x_serial_init_baud(int baudrate)
|
||||
{
|
||||
int clock = 0;
|
||||
|
||||
#if defined(CONFIG_PL010_SERIAL)
|
||||
pl01x_type = TYPE_PL010;
|
||||
#elif defined(CONFIG_PL011_SERIAL)
|
||||
#if defined(CONFIG_PL011_SERIAL)
|
||||
pl01x_type = TYPE_PL011;
|
||||
clock = CONFIG_PL011_CLOCK;
|
||||
#endif
|
||||
|
||||
@ -1,184 +0,0 @@
|
||||
/*
|
||||
* U-Boot - Configuration file for Cirrus Logic EDB93xx boards
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#ifdef CONFIG_MK_edb9301
|
||||
#define CONFIG_EDB9301
|
||||
#elif defined(CONFIG_MK_edb9302)
|
||||
#define CONFIG_EDB9302
|
||||
#elif defined(CONFIG_MK_edb9302a)
|
||||
#define CONFIG_EDB9302A
|
||||
#elif defined(CONFIG_MK_edb9307)
|
||||
#define CONFIG_EDB9307
|
||||
#elif defined(CONFIG_MK_edb9307a)
|
||||
#define CONFIG_EDB9307A
|
||||
#elif defined(CONFIG_MK_edb9312)
|
||||
#define CONFIG_EDB9312
|
||||
#elif defined(CONFIG_MK_edb9315)
|
||||
#define CONFIG_EDB9315
|
||||
#elif defined(CONFIG_MK_edb9315a)
|
||||
#define CONFIG_EDB9315A
|
||||
#else
|
||||
#error "no board defined"
|
||||
#endif
|
||||
|
||||
/* Initial environment and monitor configuration options. */
|
||||
#define CONFIG_CMDLINE_TAG 1
|
||||
#define CONFIG_INITRD_TAG 1
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||
#define CONFIG_BOOTFILE "edb93xx.img"
|
||||
|
||||
#ifdef CONFIG_EDB9301
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_EDB9301
|
||||
#elif defined(CONFIG_EDB9302)
|
||||
#define CONFIG_EP9302
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302
|
||||
#elif defined(CONFIG_EDB9302A)
|
||||
#define CONFIG_EP9302
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302A
|
||||
#elif defined(CONFIG_EDB9307)
|
||||
#define CONFIG_EP9307
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307
|
||||
#elif defined(CONFIG_EDB9307A)
|
||||
#define CONFIG_EP9307
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307A
|
||||
#elif defined(CONFIG_EDB9312)
|
||||
#define CONFIG_EP9312
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_EDB9312
|
||||
#elif defined(CONFIG_EDB9315)
|
||||
#define CONFIG_EP9315
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315
|
||||
#elif defined(CONFIG_EDB9315A)
|
||||
#define CONFIG_EP9315
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315A
|
||||
#else
|
||||
#error "no board defined"
|
||||
#endif
|
||||
|
||||
/* High-level configuration options */
|
||||
#define CONFIG_EP93XX 1 /* This is a Cirrus Logic 93xx SoC */
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456 clock */
|
||||
|
||||
/* Monitor configuration */
|
||||
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
|
||||
|
||||
/* Serial port hardware configuration */
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, \
|
||||
115200, 230400}
|
||||
#define CONFIG_SYS_SERIAL0 0x808C0000
|
||||
#define CONFIG_SYS_SERIAL1 0x808D0000
|
||||
/*#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
|
||||
(void *)CONFIG_SYS_SERIAL1} */
|
||||
|
||||
#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0}
|
||||
|
||||
/* Status LED */
|
||||
/* Optional value */
|
||||
|
||||
/* Network hardware configuration */
|
||||
#define CONFIG_DRIVER_EP93XX_MAC
|
||||
#define CONFIG_MII_SUPPRESS_PREAMBLE
|
||||
|
||||
/* SDRAM configuration */
|
||||
#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \
|
||||
defined(CONFIG_EDB9307) || defined CONFIG_EDB9312 || \
|
||||
defined(CONFIG_EDB9315)
|
||||
/*
|
||||
* EDB9301/2 has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
|
||||
* 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
|
||||
* the SROMLL bit on the processor, resulting in this non-contiguous memory map.
|
||||
*
|
||||
* The EDB9307, EDB9312, and EDB9315 have 2 banks of SDRAM consisting of
|
||||
* 2x Samsung K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of
|
||||
* 64 MB of SDRAM.
|
||||
*/
|
||||
|
||||
#define CONFIG_EDB93XX_SDCS3
|
||||
|
||||
#elif defined(CONFIG_EDB9302A) || \
|
||||
defined(CONFIG_EDB9307A) || defined(CONFIG_EDB9315A)
|
||||
/*
|
||||
* EDB9302a has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
|
||||
* 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
|
||||
* the SROMLL bit on the processor, resulting in this non-contiguous memory map.
|
||||
*
|
||||
* The EDB9307A and EDB9315A have 2 banks of SDRAM consisting of 2x Samsung
|
||||
* K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of 64 MB of SDRAM.
|
||||
*/
|
||||
#define CONFIG_EDB93XX_SDCS0
|
||||
|
||||
#else
|
||||
#error "no SDCS configuration for this board"
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_EDB93XX_SDCS3)
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x01000000 /* Default load address */
|
||||
#define PHYS_SDRAM_1 0x00000000
|
||||
#elif defined(CONFIG_EDB93XX_SDCS0)
|
||||
#define CONFIG_SYS_LOAD_ADDR 0xc1000000 /* Default load address */
|
||||
#define PHYS_SDRAM_1 0xc0000000
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_SDRAM_BASE + 32*1024 - GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
/* Must match kernel config */
|
||||
#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
|
||||
|
||||
/* Run-time memory allocatons */
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128
|
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
|
||||
|
||||
/* -----------------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*
|
||||
* The EDB9301, EDB9302(a), EDB9307a, EDB9315a have 1 bank of flash memory at
|
||||
* 0x60000000 consisting of 1x Intel TE28F128J3C-150 128 Mbit flash on a 16-bit
|
||||
* data bus, for a total of 16 MB of CFI-compatible flash.
|
||||
*
|
||||
* The EDB9307, EDB9312, and EDB9315 have 1 bank of flash memory at
|
||||
* 0x60000000 consisting of 2x Micron MT28F128J3-12 128 Mbit flash on a 32-bit
|
||||
* data bus, for a total of 32 MB of CFI-compatible flash.
|
||||
*
|
||||
*
|
||||
* EDB9301/02(a)7a/15a EDB9307/12/15
|
||||
* 0x60000000 - 0x0003FFFF u-boot u-boot
|
||||
* 0x60040000 - 0x0005FFFF environment #1 environment #1
|
||||
* 0x60060000 - 0x0007FFFF environment #2 environment #1 (continued)
|
||||
* 0x60080000 - 0x0009FFFF unused environment #2
|
||||
* 0x600A0000 - 0x000BFFFF unused environment #2 (continued)
|
||||
* 0x600C0000 - 0x00FFFFFF unused unused
|
||||
* 0x61000000 - 0x01FFFFFF not present unused
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT (256+8)
|
||||
|
||||
#define PHYS_FLASH_1 CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
|
||||
|
||||
#define CONFIG_USB_OHCI_NEW
|
||||
#define CONFIG_USB_OHCI_EP93XX
|
||||
#define CONFIG_SYS_USB_OHCI_CPU_INIT
|
||||
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
|
||||
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ep93xx-ohci"
|
||||
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80020000
|
||||
|
||||
/* Define to disable flash configuration*/
|
||||
/* #define CONFIG_EP93XX_NO_FLASH_CFG */
|
||||
|
||||
/* Define this for indusrial rated chips */
|
||||
/* #define CONFIG_EDB93XX_INDUSTRIAL */
|
||||
|
||||
#endif /* !defined (__CONFIG_H) */
|
||||
Loading…
Reference in New Issue
Block a user