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Merge tag 'xilinx-for-v2018.11' of git://git.denx.de/u-boot-microblaze

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Xilinx changes for v2018.11

- Handle BOARD_LATE_INIT via Kconfig

SPL:
- Enable GZIP for all partitions types(not only for kernel)

ZynqMP:
- Rearrange pmufw version handling
- Support newer PMUFW with improved fpga load sequence

Zynq:
- Cleanup config file
- Simplify zybo config by enabling option via Kconfig

net:
- Fix gems max-speed property reading
- Enable support for fixed-link phys
This commit is contained in:
Tom Rini
2018-09-27 08:29:10 -04:00
parent 0ae8dcfef7 3888c8d197
commit bbef20d479
20 changed files with 86 additions and 62 deletions
Download Patch File Download Diff File Expand all files Collapse all files

33
drivers/fpga/zynqmppl.c
View File

@@ -150,7 +150,8 @@ static ulong zynqmp_align_dma_buffer(u32 *buf, u32 len, u32 swap)
new_buf[i] = load_word(&buf[i], swap);
buf = new_buf;
} else if (swap != SWAP_DONE) {
} else if ((swap != SWAP_DONE) &&
(zynqmp_pmufw_version() <= PMUFW_V1_0)) {
/* For bitstream which are aligned */
u32 *new_buf = (u32 *)buf;
@@ -196,27 +197,41 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
bitstream_type bstype)
{
ALLOC_CACHE_ALIGN_BUFFER(u32, bsizeptr, 1);
u32 swap;
u32 swap = 0;
ulong bin_buf;
int ret;
u32 buf_lo, buf_hi;
u32 ret_payload[PAYLOAD_ARG_CNT];
bool xilfpga_old = false;
if (zynqmp_validate_bitstream(desc, buf, bsize, bsize, &swap))
return FPGA_FAIL;
if (zynqmp_pmufw_version() <= PMUFW_V1_0) {
puts("WARN: PMUFW v1.0 or less is detected\n");
puts("WARN: Not all bitstream formats are supported\n");
puts("WARN: Please upgrade PMUFW\n");
xilfpga_old = true;
if (zynqmp_validate_bitstream(desc, buf, bsize, bsize, &swap))
return FPGA_FAIL;
bsizeptr = (u32 *)&bsize;
flush_dcache_range((ulong)bsizeptr,
(ulong)bsizeptr + sizeof(size_t));
bstype |= BIT(ZYNQMP_FPGA_BIT_NS);
}
bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap);
bsizeptr = (u32 *)&bsize;
debug("%s called!\n", __func__);
flush_dcache_range(bin_buf, bin_buf + bsize);
flush_dcache_range((ulong)bsizeptr, (ulong)bsizeptr + sizeof(size_t));
buf_lo = (u32)bin_buf;
buf_hi = upper_32_bits(bin_buf);
bstype |= BIT(ZYNQMP_FPGA_BIT_NS);
ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
(u32)(uintptr_t)bsizeptr, bstype, ret_payload);
if (xilfpga_old)
ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
(u32)(uintptr_t)bsizeptr, bstype, ret_payload);
else
ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
(u32)bsize, 0, ret_payload);
if (ret)
debug("PL FPGA LOAD fail\n");

16
drivers/net/zynq_gem.c
View File

@@ -699,14 +699,17 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
/* Hardcode for now */
priv->phyaddr = -1;
if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
&phandle_args)) {
debug("phy-handle does not exist %s\n", dev->name);
return -ENOENT;
if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
&phandle_args)) {
debug("phy-handle does exist %s\n", dev->name);
priv->phyaddr = ofnode_read_u32_default(phandle_args.node,
"reg", -1);
priv->phy_of_node = phandle_args.node;
priv->max_speed = ofnode_read_u32_default(phandle_args.node,
"max-speed",
SPEED_1000);
}
priv->phyaddr = ofnode_read_u32_default(phandle_args.node, "reg", -1);
priv->phy_of_node = phandle_args.node;
phy_mode = dev_read_prop(dev, "phy-mode", NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
@@ -716,7 +719,6 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
}
priv->interface = pdata->phy_interface;
priv->max_speed = dev_read_u32_default(dev, "max-speed", SPEED_1000);
priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma");
printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,