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rockchip: clk: pll: add common pll setting funcs

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Common PLL setup function, compatible with different SOC.
Mainly for the subsequent new SOC use.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Elaine Zhang
2019-10-25 09:42:17 +08:00
committed by Kever Yang
parent 7acd030210
commit bbda2ed584
3 changed files with 437 additions and 0 deletions
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76
arch/arm/include/asm/arch-rockchip/clock.h
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@@ -9,6 +9,7 @@
/* define pll mode */
#define RKCLK_PLL_MODE_SLOW 0
#define RKCLK_PLL_MODE_NORMAL 1
#define RKCLK_PLL_MODE_DEEP 2
enum {
ROCKCHIP_SYSCON_NOC,
@@ -33,6 +34,81 @@ enum rk_clk_id {
CLK_COUNT,
};
#define PLL(_type, _id, _con, _mode, _mshift, \
_lshift, _pflags, _rtable) \
{ \
.id = _id, \
.type = _type, \
.con_offset = _con, \
.mode_offset = _mode, \
.mode_shift = _mshift, \
.lock_shift = _lshift, \
.pll_flags = _pflags, \
.rate_table = _rtable, \
}
#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
_postdiv2, _dsmpd, _frac) \
{ \
.rate = _rate##U, \
.fbdiv = _fbdiv, \
.postdiv1 = _postdiv1, \
.refdiv = _refdiv, \
.postdiv2 = _postdiv2, \
.dsmpd = _dsmpd, \
.frac = _frac, \
}
struct rockchip_pll_rate_table {
unsigned long rate;
unsigned int nr;
unsigned int nf;
unsigned int no;
unsigned int nb;
/* for RK3036/RK3399 */
unsigned int fbdiv;
unsigned int postdiv1;
unsigned int refdiv;
unsigned int postdiv2;
unsigned int dsmpd;
unsigned int frac;
};
enum rockchip_pll_type {
pll_rk3036,
pll_rk3066,
pll_rk3328,
pll_rk3366,
pll_rk3399,
};
struct rockchip_pll_clock {
unsigned int id;
unsigned int con_offset;
unsigned int mode_offset;
unsigned int mode_shift;
unsigned int lock_shift;
enum rockchip_pll_type type;
unsigned int pll_flags;
struct rockchip_pll_rate_table *rate_table;
unsigned int mode_mask;
};
struct rockchip_cpu_rate_table {
unsigned long rate;
unsigned int aclk_div;
unsigned int pclk_div;
};
int rockchip_pll_set_rate(struct rockchip_pll_clock *pll,
void __iomem *base, ulong clk_id,
ulong drate);
ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll,
void __iomem *base, ulong clk_id);
const struct rockchip_cpu_rate_table *
rockchip_get_cpu_settings(struct rockchip_cpu_rate_table *cpu_table,
ulong rate);
static inline int rk_pll_id(enum rk_clk_id clk_id)
{
return clk_id - 1;