Merge git://git.denx.de/u-boot-fsl-qoriq
This commit is contained in:
commit
bb3d9ed3a9
@ -490,3 +490,10 @@ config SYS_MC_RSV_MEM_ALIGN
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config SPL_LDSCRIPT
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default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
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config HAS_FSL_XHCI_USB
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bool
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default y if ARCH_LS1043A || ARCH_LS1046A
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help
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For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
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pins, select it when the pins are assigned to USB.
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@ -35,6 +35,7 @@ int ppa_init(void)
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unsigned int el = current_el();
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void *ppa_fit_addr;
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u32 *boot_loc_ptr_l, *boot_loc_ptr_h;
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u32 *loadable_l, *loadable_h;
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int ret;
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#ifdef CONFIG_CHAIN_OF_TRUST
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@ -240,9 +241,9 @@ int ppa_init(void)
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PPA_KEY_HASH,
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&ppa_img_addr);
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if (ret != 0)
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printf("PPA validation failed\n");
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printf("SEC firmware(s) validation failed\n");
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else
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printf("PPA validation Successful\n");
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printf("SEC firmware(s) validation Successful\n");
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}
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#if defined(CONFIG_SYS_LS_PPA_FW_IN_MMC) || \
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defined(CONFIG_SYS_LS_PPA_FW_IN_NAND)
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@ -254,15 +255,24 @@ int ppa_init(void)
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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boot_loc_ptr_l = &gur->bootlocptrl;
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boot_loc_ptr_h = &gur->bootlocptrh;
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/* Assign addresses to loadable ptrs */
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loadable_l = &gur->scratchrw[4];
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loadable_h = &gur->scratchrw[5];
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#elif defined(CONFIG_FSL_LSCH2)
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struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
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boot_loc_ptr_l = &scfg->scratchrw[1];
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boot_loc_ptr_h = &scfg->scratchrw[0];
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/* Assign addresses to loadable ptrs */
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loadable_l = &scfg->scratchrw[2];
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loadable_h = &scfg->scratchrw[3];
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#endif
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debug("fsl-ppa: boot_loc_ptr_l = 0x%p, boot_loc_ptr_h =0x%p\n",
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boot_loc_ptr_l, boot_loc_ptr_h);
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ret = sec_firmware_init(ppa_fit_addr, boot_loc_ptr_l, boot_loc_ptr_h);
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ret = sec_firmware_init(ppa_fit_addr, boot_loc_ptr_l, boot_loc_ptr_h,
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loadable_l, loadable_h);
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#if defined(CONFIG_SYS_LS_PPA_FW_IN_MMC) || \
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defined(CONFIG_SYS_LS_PPA_FW_IN_NAND)
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@ -105,6 +105,74 @@ static int sec_firmware_parse_image(const void *sec_firmware_img,
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return 0;
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}
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/*
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* SEC Firmware FIT image parser to check if any loadable is
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* present. If present, verify integrity of the loadable and
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* copy loadable to address provided in (loadable_h, loadable_l).
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*
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* Returns 0 on success and a negative errno on error task fail.
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*/
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static int sec_firmware_check_copy_loadable(const void *sec_firmware_img,
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u32 *loadable_l, u32 *loadable_h)
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{
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phys_addr_t sec_firmware_loadable_addr = 0;
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int conf_node_off, ld_node_off;
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char *conf_node_name = NULL;
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const void *data;
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size_t size;
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ulong load;
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conf_node_name = SEC_FIRMEWARE_FIT_CNF_NAME;
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conf_node_off = fit_conf_get_node(sec_firmware_img, conf_node_name);
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if (conf_node_off < 0) {
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printf("SEC Firmware: %s: no such config\n", conf_node_name);
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return -ENOENT;
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}
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ld_node_off = fit_conf_get_prop_node(sec_firmware_img, conf_node_off,
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FIT_LOADABLE_PROP);
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if (ld_node_off >= 0) {
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printf("SEC Firmware: '%s' present in config\n",
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FIT_LOADABLE_PROP);
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/* Verify secure firmware image */
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if (!(fit_image_verify(sec_firmware_img, ld_node_off))) {
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printf("SEC Loadable: Bad loadable image (bad CRC)\n");
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return -EINVAL;
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}
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if (fit_image_get_data(sec_firmware_img, ld_node_off,
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&data, &size)) {
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printf("SEC Loadable: Can't get subimage data/size");
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return -ENOENT;
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}
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/* Get load address, treated as load offset to secure memory */
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if (fit_image_get_load(sec_firmware_img, ld_node_off, &load)) {
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printf("SEC Loadable: Can't get subimage load");
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return -ENOENT;
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}
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/* Compute load address for loadable in secure memory */
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sec_firmware_loadable_addr = (sec_firmware_addr -
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gd->arch.tlb_size) + load;
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/* Copy loadable to secure memory and flush dcache */
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debug("%s copied to address 0x%p\n",
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FIT_LOADABLE_PROP, (void *)sec_firmware_loadable_addr);
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memcpy((void *)sec_firmware_loadable_addr, data, size);
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flush_dcache_range(sec_firmware_loadable_addr,
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sec_firmware_loadable_addr + size);
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}
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/* Populate address ptrs for loadable image with loadbale addr */
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out_le32(loadable_l, (sec_firmware_loadable_addr & WORD_MASK));
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out_le32(loadable_h, (sec_firmware_loadable_addr >> WORD_SHIFT));
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return 0;
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}
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static int sec_firmware_copy_image(const char *title,
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u64 image_addr, u32 image_size, u64 sec_firmware)
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{
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@ -117,9 +185,11 @@ static int sec_firmware_copy_image(const char *title,
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/*
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* This function will parse the SEC Firmware image, and then load it
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* to secure memory.
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* to secure memory. Also load any loadable if present along with SEC
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* Firmware image.
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*/
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static int sec_firmware_load_image(const void *sec_firmware_img)
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static int sec_firmware_load_image(const void *sec_firmware_img,
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u32 *loadable_l, u32 *loadable_h)
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{
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const void *raw_image_addr;
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size_t raw_image_size = 0;
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@ -172,6 +242,15 @@ static int sec_firmware_load_image(const void *sec_firmware_img)
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if (ret)
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goto out;
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/*
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* Check if any loadable are present along with firmware image, if
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* present load them.
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*/
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ret = sec_firmware_check_copy_loadable(sec_firmware_img, loadable_l,
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loadable_h);
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if (ret)
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goto out;
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sec_firmware_addr |= SEC_FIRMWARE_LOADED;
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debug("SEC Firmware: Entry point: 0x%llx\n",
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sec_firmware_addr & SEC_FIRMWARE_ADDR_MASK);
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@ -289,17 +368,22 @@ int sec_firmware_get_random(uint8_t *rand, int bytes)
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* @sec_firmware_img: the SEC Firmware image address
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* @eret_hold_l: the address to hold exception return address low
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* @eret_hold_h: the address to hold exception return address high
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* @loadable_l: the address to hold loadable address low
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* @loadable_h: the address to hold loadable address high
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*/
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int sec_firmware_init(const void *sec_firmware_img,
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u32 *eret_hold_l,
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u32 *eret_hold_h)
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u32 *eret_hold_h,
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u32 *loadable_l,
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u32 *loadable_h)
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{
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int ret;
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if (!sec_firmware_is_valid(sec_firmware_img))
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return -EINVAL;
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ret = sec_firmware_load_image(sec_firmware_img);
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ret = sec_firmware_load_image(sec_firmware_img, loadable_l,
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loadable_h);
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if (ret) {
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printf("SEC Firmware: Failed to load image\n");
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return ret;
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@ -76,6 +76,20 @@
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num-cs = <4>;
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};
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usb0: usb3@3100000 {
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compatible = "fsl,layerscape-dwc3";
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reg = <0x0 0x3100000 0x0 0x10000>;
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interrupts = <0 80 0x4>; /* Level high type */
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dr_mode = "host";
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};
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usb1: usb3@3110000 {
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compatible = "fsl,layerscape-dwc3";
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reg = <0x0 0x3110000 0x0 0x10000>;
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interrupts = <0 81 0x4>; /* Level high type */
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dr_mode = "host";
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};
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pcie@3400000 {
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compatible = "fsl,ls-pcie", "snps,dw-pcie";
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reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
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@ -16,7 +16,7 @@
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* Reserve secure memory
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* To be aligned with MMU block size
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*/
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#define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */
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#define CONFIG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */
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#define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
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#ifdef CONFIG_ARCH_LS2080A
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@ -9,8 +9,10 @@
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#define PSCI_INVALID_VER 0xffffffff
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#define SEC_JR3_OFFSET 0x40000
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#define WORD_MASK 0xffffffff
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#define WORD_SHIFT 32
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int sec_firmware_init(const void *, u32 *, u32 *);
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int sec_firmware_init(const void *, u32 *, u32 *, u32 *, u32 *);
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int _sec_firmware_entry(const void *, u32 *, u32 *);
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bool sec_firmware_is_valid(const void *);
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bool sec_firmware_support_hwrng(void);
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@ -184,12 +184,18 @@ __secondary_start_page:
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mtspr SPRN_PIR,r4 /* write to PIR register */
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#ifdef CONFIG_SYS_FSL_ERRATUM_A007907
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mfspr r8, L1CSR2
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clrrwi r8, r8, 10 /* clear bit [54-63] DCSTASHID */
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mtspr L1CSR2, r8
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#else
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#ifdef CONFIG_SYS_CACHE_STASHING
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/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
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slwi r8,r4,1
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addi r8,r8,32
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mtspr L1CSR2,r8
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#endif
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#endif /* CONFIG_SYS_FSL_ERRATUM_A007907 */
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#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
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defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
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@ -634,6 +634,7 @@ int board_eth_init(bd_t *bis)
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for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
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switch (wriop_get_enet_if(i)) {
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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ls1088a_handle_phy_interface_rgmii(i);
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break;
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case PHY_INTERFACE_MODE_QSGMII:
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@ -30,3 +30,12 @@ CONFIG_SYS_NS16550=y
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CONFIG_DM_SPI=y
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CONFIG_FSL_DSPI=y
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CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_USB=y
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CONFIG_USB_GADGET=y
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CONFIG_CMD_USB=y
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CONFIG_DM_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_XHCI_DWC3=y
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CONFIG_USB_DWC3=y
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CONFIG_USB_STORAGE=y
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@ -30,3 +30,12 @@ CONFIG_SYS_NS16550=y
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CONFIG_DM_SPI=y
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CONFIG_FSL_DSPI=y
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CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_USB=y
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CONFIG_USB_GADGET=y
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CONFIG_CMD_USB=y
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CONFIG_DM_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_XHCI_DWC3=y
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CONFIG_USB_DWC3=y
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CONFIG_USB_STORAGE=y
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@ -725,9 +725,9 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
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* Initialize the global default MC portal
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* And check that the MC firmware is responding portal commands:
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*/
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root_mc_io = (struct fsl_mc_io *)malloc(sizeof(struct fsl_mc_io));
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root_mc_io = (struct fsl_mc_io *)calloc(sizeof(struct fsl_mc_io), 1);
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if (!root_mc_io) {
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printf(" No memory: malloc() failed\n");
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printf(" No memory: calloc() failed\n");
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return -ENOMEM;
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}
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@ -879,11 +879,12 @@ static int dpio_init(void)
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struct dpio_cfg dpio_cfg;
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int err = 0;
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|
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dflt_dpio = (struct fsl_dpio_obj *)malloc(sizeof(struct fsl_dpio_obj));
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dflt_dpio = (struct fsl_dpio_obj *)calloc(
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sizeof(struct fsl_dpio_obj), 1);
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if (!dflt_dpio) {
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printf("No memory: malloc() failed\n");
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printf("No memory: calloc() failed\n");
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err = -ENOMEM;
|
||||
goto err_malloc;
|
||||
goto err_calloc;
|
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}
|
||||
|
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dpio_cfg.channel_mode = DPIO_LOCAL_CHANNEL;
|
||||
@ -948,7 +949,7 @@ err_get_attr:
|
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dpio_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
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err_create:
|
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free(dflt_dpio);
|
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err_malloc:
|
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err_calloc:
|
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return err;
|
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}
|
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|
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@ -1030,11 +1031,11 @@ static int dprc_init(void)
|
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goto err_create;
|
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}
|
||||
|
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dflt_mc_io = (struct fsl_mc_io *)malloc(sizeof(struct fsl_mc_io));
|
||||
dflt_mc_io = (struct fsl_mc_io *)calloc(sizeof(struct fsl_mc_io), 1);
|
||||
if (!dflt_mc_io) {
|
||||
err = -ENOMEM;
|
||||
printf(" No memory: malloc() failed\n");
|
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goto err_malloc;
|
||||
printf(" No memory: calloc() failed\n");
|
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goto err_calloc;
|
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}
|
||||
|
||||
child_portal_id = MC_PORTAL_OFFSET_TO_PORTAL_ID(mc_portal_offset);
|
||||
@ -1059,7 +1060,7 @@ static int dprc_init(void)
|
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return 0;
|
||||
err_child_open:
|
||||
free(dflt_mc_io);
|
||||
err_malloc:
|
||||
err_calloc:
|
||||
dprc_destroy_container(root_mc_io, MC_CMD_NO_FLAGS,
|
||||
root_dprc_handle, child_dprc_id);
|
||||
err_create:
|
||||
@ -1110,11 +1111,12 @@ static int dpbp_init(void)
|
||||
struct dpbp_attr dpbp_attr;
|
||||
struct dpbp_cfg dpbp_cfg;
|
||||
|
||||
dflt_dpbp = (struct fsl_dpbp_obj *)malloc(sizeof(struct fsl_dpbp_obj));
|
||||
dflt_dpbp = (struct fsl_dpbp_obj *)calloc(
|
||||
sizeof(struct fsl_dpbp_obj), 1);
|
||||
if (!dflt_dpbp) {
|
||||
printf("No memory: malloc() failed\n");
|
||||
printf("No memory: calloc() failed\n");
|
||||
err = -ENOMEM;
|
||||
goto err_malloc;
|
||||
goto err_calloc;
|
||||
}
|
||||
|
||||
dpbp_cfg.options = 512;
|
||||
@ -1164,7 +1166,7 @@ err_get_attr:
|
||||
dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle);
|
||||
dpbp_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle);
|
||||
err_create:
|
||||
err_malloc:
|
||||
err_calloc:
|
||||
return err;
|
||||
}
|
||||
|
||||
@ -1206,11 +1208,12 @@ static int dpni_init(void)
|
||||
struct dpni_extended_cfg dpni_extended_cfg;
|
||||
struct dpni_cfg dpni_cfg;
|
||||
|
||||
dflt_dpni = (struct fsl_dpni_obj *)malloc(sizeof(struct fsl_dpni_obj));
|
||||
dflt_dpni = (struct fsl_dpni_obj *)calloc(
|
||||
sizeof(struct fsl_dpni_obj), 1);
|
||||
if (!dflt_dpni) {
|
||||
printf("No memory: malloc() failed\n");
|
||||
printf("No memory: calloc() failed\n");
|
||||
err = -ENOMEM;
|
||||
goto err_malloc;
|
||||
goto err_calloc;
|
||||
}
|
||||
|
||||
memset(&dpni_extended_cfg, 0, sizeof(dpni_extended_cfg));
|
||||
@ -1272,7 +1275,7 @@ err_get_attr:
|
||||
err_create:
|
||||
err_prepare_extended_cfg:
|
||||
free(dflt_dpni);
|
||||
err_malloc:
|
||||
err_calloc:
|
||||
return err;
|
||||
}
|
||||
|
||||
|
@ -99,7 +99,7 @@ void fsl_rgmii_init(void)
|
||||
ec >>= FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT;
|
||||
|
||||
if (!ec)
|
||||
wriop_init_dpmac_enet_if(4, PHY_INTERFACE_MODE_RGMII);
|
||||
wriop_init_dpmac_enet_if(4, PHY_INTERFACE_MODE_RGMII_ID);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_EC2
|
||||
@ -108,7 +108,7 @@ void fsl_rgmii_init(void)
|
||||
ec >>= FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT;
|
||||
|
||||
if (!ec)
|
||||
wriop_init_dpmac_enet_if(5, PHY_INTERFACE_MODE_RGMII);
|
||||
wriop_init_dpmac_enet_if(5, PHY_INTERFACE_MODE_RGMII_ID);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
@ -71,6 +71,12 @@ config USB_XHCI_DRA7XX_INDEX
|
||||
Select the DRA7XX xHCI USB index.
|
||||
Current supported values: 0, 1.
|
||||
|
||||
config USB_XHCI_FSL
|
||||
bool "Support for NXP Layerscape on-chip xHCI USB controller"
|
||||
default y if ARCH_LS1021A || FSL_LSCH3 || FSL_LSCH2
|
||||
depends on !SPL_NO_USB
|
||||
help
|
||||
Enables support for the on-chip xHCI controller on NXP Layerscape SoCs.
|
||||
endif # USB_XHCI_HCD
|
||||
|
||||
config USB_EHCI_HCD
|
||||
|
@ -32,7 +32,7 @@
|
||||
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
|
||||
|
||||
/* Generic Timer Definitions */
|
||||
#define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ/4 /* 25MHz */
|
||||
#define COUNTER_FREQUENCY 25000000 /* 25MHz */
|
||||
|
||||
/* CSU */
|
||||
#define CONFIG_LAYERSCAPE_NS_ACCESS
|
||||
|
@ -31,16 +31,6 @@
|
||||
"kernel_load=0x96000000\0" \
|
||||
"kernel_size=0x2800000\0"
|
||||
|
||||
/*
|
||||
* USB
|
||||
*/
|
||||
#define CONFIG_HAS_FSL_XHCI_USB
|
||||
|
||||
#ifdef CONFIG_HAS_FSL_XHCI_USB
|
||||
#define CONFIG_USB_XHCI_FSL
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
#endif
|
||||
|
||||
#define CONFIG_CMD_MEMINFO
|
||||
#define CONFIG_CMD_MEMTEST
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
|
@ -118,14 +118,6 @@
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#endif
|
||||
|
||||
/*XHCI Support - enabled by default*/
|
||||
#define CONFIG_HAS_FSL_XHCI_USB
|
||||
|
||||
#ifdef CONFIG_HAS_FSL_XHCI_USB
|
||||
#define CONFIG_USB_XHCI_FSL
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
#endif
|
||||
|
||||
/* MMC */
|
||||
#ifdef CONFIG_MMC
|
||||
#define CONFIG_FSL_ESDHC
|
||||
|
@ -19,15 +19,6 @@
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
|
||||
|
||||
/*
|
||||
* USB
|
||||
*/
|
||||
#define CONFIG_HAS_FSL_XHCI_USB
|
||||
|
||||
#ifdef CONFIG_HAS_FSL_XHCI_USB
|
||||
#define CONFIG_USB_XHCI_FSL
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* I2C IO expander
|
||||
|
@ -19,14 +19,6 @@
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
|
||||
|
||||
/* XHCI Support - enabled by default */
|
||||
#define CONFIG_HAS_FSL_XHCI_USB
|
||||
|
||||
#ifdef CONFIG_HAS_FSL_XHCI_USB
|
||||
#define CONFIG_USB_XHCI_FSL
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 100000000
|
||||
#define CONFIG_DDR_CLK_FREQ 100000000
|
||||
|
||||
|
@ -404,14 +404,6 @@ unsigned long get_board_ddr_clk(void);
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#endif
|
||||
|
||||
/*XHCI Support - enabled by default*/
|
||||
#define CONFIG_HAS_FSL_XHCI_USB
|
||||
|
||||
#ifdef CONFIG_HAS_FSL_XHCI_USB
|
||||
#define CONFIG_USB_XHCI_FSL
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Video
|
||||
*/
|
||||
|
@ -44,14 +44,6 @@
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#endif
|
||||
|
||||
/* XHCI Support - enabled by default */
|
||||
#define CONFIG_HAS_FSL_XHCI_USB
|
||||
|
||||
#ifdef CONFIG_HAS_FSL_XHCI_USB
|
||||
#define CONFIG_USB_XHCI_FSL
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 100000000
|
||||
#define CONFIG_DDR_CLK_FREQ 100000000
|
||||
|
||||
|
@ -370,13 +370,6 @@ unsigned long get_board_ddr_clk(void);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* USB */
|
||||
#define CONFIG_HAS_FSL_XHCI_USB
|
||||
#ifdef CONFIG_HAS_FSL_XHCI_USB
|
||||
#define CONFIG_USB_XHCI_FSL
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
|
@ -284,15 +284,6 @@
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* USB */
|
||||
#ifndef SPL_NO_USB
|
||||
#define CONFIG_HAS_FSL_XHCI_USB
|
||||
#ifdef CONFIG_HAS_FSL_XHCI_USB
|
||||
#define CONFIG_USB_XHCI_FSL
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* SATA */
|
||||
#ifndef SPL_NO_SATA
|
||||
#define CONFIG_LIBATA
|
||||
|
@ -136,13 +136,6 @@ unsigned long get_board_ddr_clk(void);
|
||||
#define CFG_LPUART_EN 0x2
|
||||
#endif
|
||||
|
||||
/* USB */
|
||||
#define CONFIG_HAS_FSL_XHCI_USB
|
||||
#ifdef CONFIG_HAS_FSL_XHCI_USB
|
||||
#define CONFIG_USB_XHCI_FSL
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
|
||||
#endif
|
||||
|
||||
/* SATA */
|
||||
#define CONFIG_LIBATA
|
||||
#define CONFIG_SCSI_AHCI
|
||||
|
@ -209,15 +209,6 @@
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* USB */
|
||||
#ifndef SPL_NO_USB
|
||||
#define CONFIG_HAS_FSL_XHCI_USB
|
||||
#ifdef CONFIG_HAS_FSL_XHCI_USB
|
||||
#define CONFIG_USB_XHCI_FSL
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* SATA */
|
||||
#ifndef SPL_NO_SATA
|
||||
#define CONFIG_LIBATA
|
||||
|
@ -20,7 +20,6 @@ unsigned long get_board_ddr_clk(void);
|
||||
|
||||
|
||||
#if defined(CONFIG_QSPI_BOOT)
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
|
||||
#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
|
||||
#define CONFIG_ENV_SECT_SIZE 0x40000
|
||||
|
@ -12,7 +12,6 @@
|
||||
#define CONFIG_DISPLAY_BOARDINFO_LATE
|
||||
|
||||
#if defined(CONFIG_QSPI_BOOT)
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
|
||||
#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
|
||||
#define CONFIG_ENV_SECT_SIZE 0x40000
|
||||
|
@ -435,13 +435,6 @@ unsigned long get_board_ddr_clk(void);
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* USB
|
||||
*/
|
||||
#define CONFIG_HAS_FSL_XHCI_USB
|
||||
#define CONFIG_USB_XHCI_FSL
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||
|
||||
#include <asm/fsl_secure_boot.h>
|
||||
|
||||
#endif /* __LS2_QDS_H */
|
||||
|
@ -333,13 +333,6 @@ unsigned long get_board_sys_clk(void);
|
||||
|
||||
#define CONFIG_MISC_INIT_R
|
||||
|
||||
/*
|
||||
* USB
|
||||
*/
|
||||
#define CONFIG_HAS_FSL_XHCI_USB
|
||||
#define CONFIG_USB_XHCI_FSL
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||
|
||||
#undef CONFIG_CMDLINE_EDITING
|
||||
#include <config_distro_defaults.h>
|
||||
|
||||
|
@ -58,7 +58,7 @@ struct fsl_xhci {
|
||||
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
|
||||
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
|
||||
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
|
||||
#elif defined(CONFIG_ARCH_LS2080A)
|
||||
#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
|
||||
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
|
||||
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR
|
||||
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
|
||||
|
@ -873,7 +873,6 @@ CONFIG_HAS_ETH7
|
||||
CONFIG_HAS_FEC
|
||||
CONFIG_HAS_FSL_DR_USB
|
||||
CONFIG_HAS_FSL_MPH_USB
|
||||
CONFIG_HAS_FSL_XHCI_USB
|
||||
CONFIG_HAS_POST
|
||||
CONFIG_HCLK_FREQ
|
||||
CONFIG_HDBOOT
|
||||
@ -5027,7 +5026,6 @@ CONFIG_USB_TTY
|
||||
CONFIG_USB_TUSB_OMAP_DMA
|
||||
CONFIG_USB_ULPI_TIMEOUT
|
||||
CONFIG_USB_XHCI_EXYNOS
|
||||
CONFIG_USB_XHCI_FSL
|
||||
CONFIG_USB_XHCI_KEYSTONE
|
||||
CONFIG_USB_XHCI_OMAP
|
||||
CONFIG_USER_LOWLEVEL_INIT
|
||||
|
Loading…
Reference in New Issue
Block a user