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Merge tag 'mips-pull-2020-08-03' of https://gitlab.denx.de/u-boot/custodians/u-boot-mips

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- doc: fix qemu-mips build instructions
- MIPS: add GPIO, CLK and SPI drivers for Octeon MIPS64
This commit is contained in:
Tom Rini
2020-08-04 11:07:16 -04:00
parent d6faedca76 d071ff012e
commit bb3694d5b1
15 changed files with 1072 additions and 8 deletions
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6
arch/mips/Kconfig
View File

@@ -112,9 +112,11 @@ config ARCH_OCTEON
select DISPLAY_CPUINFO
select DMA_ADDR_T_64BIT
select DM
select DM_SERIAL
select DM_GPIO
select DM_ETH
select DM_GPIO
select DM_I2C
select DM_SERIAL
select DM_SPI
select MIPS_L2_CACHE
select MIPS_MACH_EARLY_INIT
select MIPS_TUNE_OCTEON3

66
arch/mips/dts/mrvl,cn73xx.dtsi
View File

@@ -5,6 +5,8 @@
/dts-v1/;
#include <dt-bindings/clock/octeon-clock.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
@@ -38,6 +40,38 @@
#size-cells = <1>;
};
clk: clock {
compatible = "mrvl,octeon-clk";
#clock-cells = <1>;
u-boot,dm-pre-reloc;
};
gpio: gpio-controller@1070000000800 {
#gpio-cells = <2>;
compatible = "cavium,octeon-7890-gpio";
reg = <0x10700 0x00000800 0x0 0x100>;
gpio-controller;
nr-gpios = <32>;
/* Interrupts are specified by two parts:
* 1) GPIO pin number (0..15)
* 2) Triggering (1 - edge rising
* 2 - edge falling
* 4 - level active high
* 8 - level active low)
*/
interrupt-controller;
#interrupt-cells = <2>;
/* The GPIO pins connect to 16 consecutive CUI bits */
interrupts = <0x03000 4>, <0x03001 4>,
<0x03002 4>, <0x03003 4>,
<0x03004 4>, <0x03005 4>,
<0x03006 4>, <0x03007 4>,
<0x03008 4>, <0x03009 4>,
<0x0300a 4>, <0x0300b 4>,
<0x0300c 4>, <0x0300d 4>,
<0x0300e 4>, <0x0300f 4>;
};
reset: reset@1180006001600 {
compatible = "mrvl,cn7xxx-rst";
reg = <0x11800 0x06001600 0x0 0x200>;
@@ -60,5 +94,37 @@
reg-shift = <3>;
interrupts = <0x08040 4>;
};
i2c0: i2c@1180000001000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "cavium,octeon-7890-twsi";
reg = <0x11800 0x00001000 0x0 0x200>;
/* INT_ST, INT_TS, INT_CORE */
interrupts = <0x0b000 1>, <0x0b001 1>, <0x0b002 1>;
clock-frequency = <100000>;
clocks = <&clk OCTEON_CLK_IO>;
};
i2c1: i2c@1180000001200 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "cavium,octeon-7890-twsi";
reg = <0x11800 0x00001200 0x0 0x200>;
/* INT_ST, INT_TS, INT_CORE */
interrupts = <0x0b100 1>, <0x0b101 1>, <0x0b102 1>;
clock-frequency = <100000>;
clocks = <&clk OCTEON_CLK_IO>;
};
spi: spi@1070000001000 {
compatible = "cavium,octeon-3010-spi";
reg = <0x10700 0x00001000 0x0 0x100>;
interrupts = <0x05001 1>;
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <25000000>;
clocks = <&clk OCTEON_CLK_IO>;
};
};
};

21
arch/mips/dts/mrvl,octeon-ebb7304.dts
View File

@@ -5,7 +5,7 @@
/dts-v1/;
/include/ "mrvl,cn73xx.dtsi"
#include "mrvl,cn73xx.dtsi"
/ {
model = "cavium,ebb7304";
@@ -13,6 +13,7 @@
aliases {
serial0 = &uart0;
spi0 = &spi;
};
chosen {
@@ -94,3 +95,21 @@
&uart0 {
clock-frequency = <1200000000>;
};
&i2c0 {
u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */
clock-frequency = <100000>;
};
&i2c1 {
u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */
clock-frequency = <100000>;
};
&spi {
flash@0 {
compatible = "micron,n25q128a11", "jedec,spi-nor";
spi-max-frequency = <2000000>;
reg = <0>;
};
};