clk: at91: Enhance the peripheral clock
Enhance the peripheral clock to support both at9sam9x5's and at91rm9200's peripheral clock via the different compatibles. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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@ -16,6 +16,10 @@
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#define PERIPHERAL_ID_MAX 31
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#define PERIPHERAL_MASK(id) (1 << ((id) & PERIPHERAL_ID_MAX))
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enum periph_clk_type {
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CLK_PERIPH_AT91RM9200 = 0,
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CLK_PERIPH_AT91SAM9X5,
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};
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/**
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* sam9x5_periph_clk_bind() - for the periph clock driver
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* Recursively bind its children as clk devices.
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@ -28,7 +32,14 @@ static int sam9x5_periph_clk_bind(struct udevice *dev)
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}
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static const struct udevice_id sam9x5_periph_clk_match[] = {
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{ .compatible = "atmel,at91sam9x5-clk-peripheral" },
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{
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.compatible = "atmel,at91rm9200-clk-peripheral",
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.data = CLK_PERIPH_AT91RM9200,
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},
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{
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.compatible = "atmel,at91sam9x5-clk-peripheral",
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.data = CLK_PERIPH_AT91SAM9X5,
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},
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{}
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};
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@ -45,12 +56,24 @@ static int periph_clk_enable(struct clk *clk)
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{
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struct pmc_platdata *plat = dev_get_platdata(clk->dev);
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struct at91_pmc *pmc = plat->reg_base;
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enum periph_clk_type clk_type;
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void *addr;
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if (clk->id < PERIPHERAL_ID_MIN)
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return -1;
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writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
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setbits_le32(&pmc->pcr, AT91_PMC_PCR_CMD_WRITE | AT91_PMC_PCR_EN);
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clk_type = dev_get_driver_data(dev_get_parent(clk->dev));
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if (clk_type == CLK_PERIPH_AT91RM9200) {
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addr = &pmc->pcer;
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if (clk->id > PERIPHERAL_ID_MAX)
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addr = &pmc->pcer1;
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setbits_le32(addr, PERIPHERAL_MASK(clk->id));
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} else {
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writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
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setbits_le32(&pmc->pcr,
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AT91_PMC_PCR_CMD_WRITE | AT91_PMC_PCR_EN);
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}
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return 0;
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}
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