dm: x86: baytrail: Correct PCI region 3 when driver model is used
Commit afbbd413a
fixed this for non-driver-model. Make sure that the driver
model code handles this also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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@ -353,6 +353,8 @@ int x86_cpu_init_f(void)
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gd->arch.has_mtrr = has_mtrr();
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gd->arch.has_mtrr = has_mtrr();
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}
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}
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/* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */
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gd->pci_ram_top = 0x80000000U;
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/* Configure fixed range MTRRs for some legacy regions */
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/* Configure fixed range MTRRs for some legacy regions */
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if (gd->arch.has_mtrr) {
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if (gd->arch.has_mtrr) {
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@ -444,6 +444,7 @@ static int decode_regions(struct pci_controller *hose, const void *blob,
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{
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{
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int pci_addr_cells, addr_cells, size_cells;
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int pci_addr_cells, addr_cells, size_cells;
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int cells_per_record;
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int cells_per_record;
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phys_addr_t addr;
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const u32 *prop;
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const u32 *prop;
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int len;
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int len;
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int i;
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int i;
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@ -494,8 +495,11 @@ static int decode_regions(struct pci_controller *hose, const void *blob,
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}
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}
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/* Add a region for our local memory */
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/* Add a region for our local memory */
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pci_set_region(hose->regions + hose->region_count++, 0, 0,
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addr = gd->ram_size;
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gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
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if (gd->pci_ram_top && gd->pci_ram_top < addr)
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addr = gd->pci_ram_top;
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pci_set_region(hose->regions + hose->region_count++, 0, 0, addr,
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PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
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return 0;
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return 0;
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}
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}
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@ -93,6 +93,7 @@ typedef struct global_data {
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#endif
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#endif
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#ifdef CONFIG_PCI
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#ifdef CONFIG_PCI
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struct pci_controller *hose; /* PCI hose for early use */
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struct pci_controller *hose; /* PCI hose for early use */
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phys_addr_t pci_ram_top; /* top of region accessible to PCI */
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#endif
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#endif
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#ifdef CONFIG_PCI_BOOTDELAY
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#ifdef CONFIG_PCI_BOOTDELAY
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int pcidelay_done;
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int pcidelay_done;
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