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socfpga: correctly increment freeze_controller_base address

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Correctly increment the base address of the freeze controller. And since
SYSMGR_FRZCTRL_VIOCTRL_SHIFT is not needed, remove it from the include file.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Dinh Nguyen 2014-11-26 12:14:33 -06:00 committed by Marek Vasut
parent 5d2f930de0
commit b9b5cf0ea3
2 changed files with 2 additions and 5 deletions
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6
arch/arm/cpu/armv7/socfpga/freeze_controller.c
View File

@ -38,8 +38,7 @@ void sys_mgr_frzctrl_freeze_req(void)
/* Freeze channel 0 to 2 */
for (channel_id = 0; channel_id <= 2; channel_id++) {
ioctrl_reg_offset = (u32)(
&freeze_controller_base->vioctrl +
(channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
&freeze_controller_base->vioctrl + channel_id);
/*
* Assert active low enrnsl, plniotri
@ -120,8 +119,7 @@ void sys_mgr_frzctrl_thaw_req(void)
/* Thaw channel 0 to 2 */
for (channel_id = 0; channel_id <= 2; channel_id++) {
ioctrl_reg_offset
= (u32)(&freeze_controller_base->vioctrl
+ (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
= (u32)(&freeze_controller_base->vioctrl + channel_id);
/*
* Assert active low bhniotri signal and

1
arch/arm/include/asm/arch-socfpga/freeze_controller.h
View File

@ -42,7 +42,6 @@ typedef enum {
#define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001
#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2
#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1
#define SYSMGR_FRZCTRL_VIOCTRL_SHIFT 0x2
void sys_mgr_frzctrl_freeze_req(void);
void sys_mgr_frzctrl_thaw_req(void);