Merge with /home/sr/git/u-boot/denx-merge-sr
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commit
b8a8bfc0c6
@ -350,12 +350,19 @@ int misc_init_r(void)
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int checkboard(void)
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{
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char *s = getenv("serial#");
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u8 rev;
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u8 val;
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#ifdef CONFIG_440EPX
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printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
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#else
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printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
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#endif
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rev = *(u8 *)(CFG_CPLD + 0);
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val = *(u8 *)(CFG_CPLD + 5) & 0x01;
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printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
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if (s != NULL) {
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puts(", serial# ");
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puts(s);
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@ -39,24 +39,6 @@ int board_early_init_f(void)
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reg = mfdcr(ebccfgd);
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mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
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mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
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mtebc(pb0cr, 0xfc0da000); /* BAS=0xfc0 64MB r/w 16-bit */
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mtebc(pb1ap, 0x00000000);
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mtebc(pb1cr, 0x00000000);
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mtebc(pb2ap, 0x04814500);
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/*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */
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mtebc(pb3ap, 0x00000000);
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mtebc(pb3cr, 0x00000000);
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mtebc(pb4ap, 0x00000000);
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mtebc(pb4cr, 0x00000000);
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mtebc(pb5ap, 0x00000000);
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mtebc(pb5cr, 0x00000000);
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/*--------------------------------------------------------------------
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* Setup the GPIO pins
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*-------------------------------------------------------------------*/
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@ -190,8 +172,15 @@ int misc_init_r (void)
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int checkboard(void)
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{
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char *s = getenv("serial#");
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u8 rev;
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u8 val;
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printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
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rev = *(u8 *)(CFG_CPLD + 0);
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val = *(u8 *)(CFG_CPLD + 5) & 0x01;
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printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
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if (s != NULL) {
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puts(", serial# ");
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puts(s);
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@ -39,24 +39,6 @@ int board_early_init_f(void)
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reg = mfdcr(ebccfgd);
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mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
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mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
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mtebc(pb0cr, 0xfc0da000); /* BAS=0xfc0 64MB r/w 16-bit */
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mtebc(pb1ap, 0x00000000);
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mtebc(pb1cr, 0x00000000);
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mtebc(pb2ap, 0x04814500);
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/*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */
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mtebc(pb3ap, 0x00000000);
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mtebc(pb3cr, 0x00000000);
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mtebc(pb4ap, 0x00000000);
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mtebc(pb4cr, 0x00000000);
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mtebc(pb5ap, 0x00000000);
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mtebc(pb5cr, 0x00000000);
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/*--------------------------------------------------------------------
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* Setup the GPIO pins
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*-------------------------------------------------------------------*/
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@ -186,8 +168,15 @@ int misc_init_r (void)
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int checkboard(void)
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{
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char *s = getenv("serial#");
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u8 rev;
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u8 val;
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printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
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rev = *(u8 *)(CFG_CPLD + 0);
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val = *(u8 *)(CFG_CPLD + 5) & 0x01;
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printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
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if (s != NULL) {
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puts(", serial# ");
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puts(s);
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@ -332,24 +332,44 @@ int checkcpu (void)
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strcpy(addstr, "No Security/Kasumi support");
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break;
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case PVR_440SP_RA:
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puts("SP Rev. A");
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case PVR_440SP_6_RAB:
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puts("SP Rev. A/B");
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strcpy(addstr, "RAID 6 support");
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break;
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case PVR_440SP_RB:
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puts("SP Rev. B");
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case PVR_440SP_RAB:
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puts("SP Rev. A/B");
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strcpy(addstr, "No RAID 6 support");
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break;
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case PVR_440SP_6_RC:
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puts("SP Rev. C");
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strcpy(addstr, "RAID 6 support");
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break;
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case PVR_440SP_RC:
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puts("SP Rev. C");
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strcpy(addstr, "No RAID 6 support");
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break;
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case PVR_440SPe_6_RA:
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puts("SPe Rev. A");
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strcpy(addstr, "RAID 6 support");
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break;
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case PVR_440SPe_RA:
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puts("SPe Rev. A");
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strcpy(addstr, "No RAID 6 support");
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break;
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case PVR_440SPe_6_RB:
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puts("SPe Rev. B");
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strcpy(addstr, "RAID 6 support");
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break;
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case PVR_440SPe_RB:
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puts("SPe Rev. B");
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strcpy(addstr, "No RAID 6 support");
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break;
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default:
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@ -747,11 +747,14 @@
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#define PVR_440GX_RC 0x51B21892
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#define PVR_440GX_RF 0x51B21894
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#define PVR_405EP_RB 0x51210950
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#define PVR_440SP_RA 0x53221850
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#define PVR_440SP_RB 0x53221891
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#define PVR_440SP_RC 0x53221892
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#define PVR_440SPe_RA 0x53421890
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#define PVR_440SPe_RB 0x53421891
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#define PVR_440SP_6_RAB 0x53221850 /* 440SP rev A&B with RAID 6 support enabled */
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#define PVR_440SP_RAB 0x53321850 /* 440SP rev A&B without RAID 6 support */
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#define PVR_440SP_6_RC 0x53221891 /* 440SP rev C with RAID 6 support enabled */
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#define PVR_440SP_RC 0x53321891 /* 440SP rev C without RAID 6 support */
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#define PVR_440SPe_6_RA 0x53421890 /* 440SPe rev A with RAID 6 support enabled */
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#define PVR_440SPe_RA 0x53521890 /* 440SPe rev A without RAID 6 support */
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#define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled */
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#define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */
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#define PVR_601 0x00010000
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#define PVR_602 0x00050000
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#define PVR_603 0x00030000
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@ -301,6 +301,20 @@
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* External Bus Controller (EBC) Setup
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*----------------------------------------------------------------------*/
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#define CFG_FLASH CFG_FLASH_BASE
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#define CFG_CPLD 0x80000000
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/* Memory Bank 0 (NOR-FLASH) initialization */
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#define CFG_EBC_PB0AP 0x03017300
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#define CFG_EBC_PB0CR (CFG_FLASH | 0xda000)
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/* Memory Bank 2 (CPLD) initialization */
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#define CFG_EBC_PB2AP 0x04814500
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#define CFG_EBC_PB2CR (CFG_CPLD | 0x18000)
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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@ -306,6 +306,20 @@
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* External Bus Controller (EBC) Setup
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*----------------------------------------------------------------------*/
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#define CFG_FLASH CFG_FLASH_BASE
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#define CFG_CPLD 0x80000000
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/* Memory Bank 0 (NOR-FLASH) initialization */
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#define CFG_EBC_PB0AP 0x03017300
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#define CFG_EBC_PB0CR (CFG_FLASH | 0xda000)
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/* Memory Bank 2 (CPLD) initialization */
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#define CFG_EBC_PB2AP 0x04814500
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#define CFG_EBC_PB2CR (CFG_CPLD | 0x18000)
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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