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Merge git://git.denx.de/u-boot-fsl-qoriq

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This commit is contained in:
Tom Rini 2018-08-13 12:34:55 -04:00
commit b8a1f47be3
23 changed files with 805 additions and 210 deletions
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4
arch/arm/cpu/armv7/ls102xa/fdt.c
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@ -64,8 +64,8 @@ void ft_fixup_enet_phy_connect_type(void *fdt)
do_fixup_by_path(fdt, enet_path, "phy-connection-type",
phy_string_for_interface(
PHY_INTERFACE_MODE_RGMII_ID),
sizeof(phy_string_for_interface(
PHY_INTERFACE_MODE_RGMII_ID)),
strlen(phy_string_for_interface(
PHY_INTERFACE_MODE_RGMII_ID)) + 1,
1);
}
}

1
arch/arm/cpu/armv8/fsl-layerscape/Makefile
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@ -37,6 +37,7 @@ endif
ifneq ($(CONFIG_ARCH_LS1046A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
obj-y += icid.o ls1046_ids.o
endif
ifneq ($(CONFIG_ARCH_LS1088A),)

192
arch/arm/cpu/armv8/fsl-layerscape/icid.c Normal file
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@ -0,0 +1,192 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
#include <common.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include <fsl_fman.h>
static void set_icid(struct icid_id_table *tbl, int size)
{
int i;
for (i = 0; i < size; i++)
out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg);
}
#ifdef CONFIG_SYS_DPAA_FMAN
void set_fman_icids(struct fman_icid_id_table *tbl, int size)
{
int i;
ccsr_fman_t *fm = (void *)CONFIG_SYS_FSL_FM1_ADDR;
for (i = 0; i < size; i++) {
out_be32(&fm->fm_bmi_common.fmbm_ppid[tbl[i].port_id - 1],
tbl[i].icid);
}
}
#endif
void set_icids(void)
{
/* setup general icid offsets */
set_icid(icid_tbl, icid_tbl_sz);
#ifdef CONFIG_SYS_DPAA_FMAN
set_fman_icids(fman_icid_tbl, fman_icid_tbl_sz);
#endif
}
int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids)
{
int i, ret;
u32 prop[8];
/*
* Note: The "iommus" property definition mentions Stream IDs while
* this code handles ICIDs. The current implementation assumes that
* ICIDs and Stream IDs are equal.
*/
for (i = 0; i < num_ids; i++) {
prop[i * 2] = cpu_to_fdt32(smmu_ph);
prop[i * 2 + 1] = cpu_to_fdt32(ids[i]);
}
ret = fdt_setprop(blob, off, "iommus",
prop, sizeof(u32) * num_ids * 2);
if (ret) {
printf("WARNING unable to set iommus: %s\n", fdt_strerror(ret));
return ret;
}
return 0;
}
int fdt_fixup_icid_tbl(void *blob, int smmu_ph,
struct icid_id_table *tbl, int size)
{
int i, err, off;
for (i = 0; i < size; i++) {
if (!tbl[i].compat)
continue;
off = fdt_node_offset_by_compat_reg(blob,
tbl[i].compat,
tbl[i].compat_addr);
if (off > 0) {
err = fdt_set_iommu_prop(blob, off, smmu_ph,
&tbl[i].id, 1);
if (err)
return err;
} else {
printf("WARNING could not find node %s: %s.\n",
tbl[i].compat, fdt_strerror(off));
}
}
return 0;
}
#ifdef CONFIG_SYS_DPAA_FMAN
int get_fman_port_icid(int port_id, struct fman_icid_id_table *tbl,
const int size)
{
int i;
for (i = 0; i < size; i++) {
if (tbl[i].port_id == port_id)
return tbl[i].icid;
}
return -1;
}
void fdt_fixup_fman_port_icid_by_compat(void *blob, int smmu_ph,
const char *compat)
{
int noff, len, icid;
const u32 *prop;
noff = fdt_node_offset_by_compatible(blob, -1, compat);
while (noff > 0) {
prop = fdt_getprop(blob, noff, "cell-index", &len);
if (!prop) {
printf("WARNING missing cell-index for fman port\n");
continue;
}
if (len != 4) {
printf("WARNING bad cell-index size for fman port\n");
continue;
}
icid = get_fman_port_icid(fdt32_to_cpu(*prop),
fman_icid_tbl, fman_icid_tbl_sz);
if (icid < 0) {
printf("WARNING unknown ICID for fman port %d\n",
*prop);
continue;
}
fdt_set_iommu_prop(blob, noff, smmu_ph, (u32 *)&icid, 1);
noff = fdt_node_offset_by_compatible(blob, noff, compat);
}
}
void fdt_fixup_fman_icids(void *blob, int smmu_ph)
{
static const char * const compats[] = {
"fsl,fman-v3-port-oh",
"fsl,fman-v3-port-rx",
"fsl,fman-v3-port-tx",
};
int i;
for (i = 0; i < ARRAY_SIZE(compats); i++)
fdt_fixup_fman_port_icid_by_compat(blob, smmu_ph, compats[i]);
}
#endif
int fdt_get_smmu_phandle(void *blob)
{
int noff, smmu_ph;
noff = fdt_node_offset_by_compatible(blob, -1, "arm,mmu-500");
if (noff < 0) {
printf("WARNING failed to get smmu node: %s\n",
fdt_strerror(noff));
return noff;
}
smmu_ph = fdt_get_phandle(blob, noff);
if (!smmu_ph) {
smmu_ph = fdt_create_phandle(blob, noff);
if (!smmu_ph) {
printf("WARNING failed to get smmu phandle\n");
return -1;
}
}
return smmu_ph;
}
void fdt_fixup_icid(void *blob)
{
int smmu_ph;
smmu_ph = fdt_get_smmu_phandle(blob);
if (smmu_ph < 0)
return;
fdt_fixup_icid_tbl(blob, smmu_ph, icid_tbl, icid_tbl_sz);
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_icids(blob, smmu_ph);
#endif
}

89
arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c Normal file
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@ -0,0 +1,89 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
#include <common.h>
#include <asm/arch-fsl-layerscape/immap_lsch2.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include <asm/arch-fsl-layerscape/fsl_portals.h>
#ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
};
#endif
struct icid_id_table icid_tbl[] = {
#ifdef CONFIG_SYS_DPAA_QBMAN
SET_QMAN_ICID(FSL_DPAA1_STREAM_ID_START),
SET_BMAN_ICID(FSL_DPAA1_STREAM_ID_START + 1),
#endif
SET_SDHC_ICID(FSL_SDHC_STREAM_ID),
SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
SET_USB_ICID(3, "snps,dwc3", FSL_USB3_STREAM_ID),
SET_SATA_ICID("fsl,ls1046a-ahci", FSL_SATA_STREAM_ID),
SET_QDMA_ICID("fsl,ls1046a-qdma", FSL_QDMA_STREAM_ID),
SET_EDMA_ICID(FSL_EDMA_STREAM_ID),
SET_ETR_ICID(FSL_ETR_STREAM_ID),
SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID),
#ifdef CONFIG_FSL_CAAM
SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_START + 2),
SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 3),
SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 4),
SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 5),
SET_SEC_JR_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 6),
SET_SEC_RTIC_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 7),
SET_SEC_RTIC_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 8),
SET_SEC_RTIC_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 9),
SET_SEC_RTIC_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 10),
SET_SEC_DECO_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 11),
SET_SEC_DECO_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 12),
SET_SEC_DECO_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 13),
#endif
};
int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
#ifdef CONFIG_SYS_DPAA_FMAN
struct fman_icid_id_table fman_icid_tbl[] = {
/* port id, icid */
SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END),
SET_FMAN_ICID_ENTRY(0x03, FSL_DPAA1_STREAM_ID_END),
SET_FMAN_ICID_ENTRY(0x04, FSL_DPAA1_STREAM_ID_END),
SET_FMAN_ICID_ENTRY(0x05, FSL_DPAA1_STREAM_ID_END),
SET_FMAN_ICID_ENTRY(0x06, FSL_DPAA1_STREAM_ID_END),
SET_FMAN_ICID_ENTRY(0x07, FSL_DPAA1_STREAM_ID_END),
SET_FMAN_ICID_ENTRY(0x08, FSL_DPAA1_STREAM_ID_END),
SET_FMAN_ICID_ENTRY(0x09, FSL_DPAA1_STREAM_ID_END),
SET_FMAN_ICID_ENTRY(0x0a, FSL_DPAA1_STREAM_ID_END),
SET_FMAN_ICID_ENTRY(0x0b, FSL_DPAA1_STREAM_ID_END),
SET_FMAN_ICID_ENTRY(0x0c, FSL_DPAA1_STREAM_ID_END),
SET_FMAN_ICID_ENTRY(0x0d, FSL_DPAA1_STREAM_ID_END),
SET_FMAN_ICID_ENTRY(0x28, FSL_DPAA1_STREAM_ID_END),
SET_FMAN_ICID_ENTRY(0x29, FSL_DPAA1_STREAM_ID_END),
SET_FMAN_ICID_ENTRY(0x2a, FSL_DPAA1_STREAM_ID_END),
SET_FMAN_ICID_ENTRY(0x2b, FSL_DPAA1_STREAM_ID_END),
SET_FMAN_ICID_ENTRY(0x2c, FSL_DPAA1_STREAM_ID_END),
SET_FMAN_ICID_ENTRY(0x2d, FSL_DPAA1_STREAM_ID_END),
SET_FMAN_ICID_ENTRY(0x10, FSL_DPAA1_STREAM_ID_END),
SET_FMAN_ICID_ENTRY(0x11, FSL_DPAA1_STREAM_ID_END),
SET_FMAN_ICID_ENTRY(0x30, FSL_DPAA1_STREAM_ID_END),
SET_FMAN_ICID_ENTRY(0x31, FSL_DPAA1_STREAM_ID_END),
};
int fman_icid_tbl_sz = ARRAY_SIZE(fman_icid_tbl);
#endif

14
arch/arm/cpu/armv8/fsl-layerscape/soc.c
View File

@ -11,6 +11,8 @@
#include <asm/io.h>
#include <asm/global_data.h>
#include <asm/arch-fsl-layerscape/config.h>
#include <asm/arch-fsl-layerscape/ns_access.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
#include <fsl_csu.h>
#endif
@ -614,6 +616,14 @@ void fsl_lsch2_early_init_f(void)
CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
}
/*
* Program Central Security Unit (CSU) to grant access
* permission for USB 2.0 controller
*/
#if defined(CONFIG_ARCH_LS1012A) && defined(CONFIG_USB_EHCI_FSL)
if (current_el() == 3)
set_devices_ns_access(CSU_CSLX_USB_2, CSU_ALL_RW);
#endif
/* Erratum */
erratum_a008850_early(); /* part 1 of 2 */
erratum_a009929();
@ -623,6 +633,10 @@ void fsl_lsch2_early_init_f(void)
erratum_a009798();
erratum_a008997();
erratum_a009007();
#ifdef CONFIG_ARCH_LS1046A
set_icids();
#endif
}
#endif

1
arch/arm/include/asm/arch-fsl-layerscape/config.h
View File

@ -257,6 +257,7 @@
#elif defined(CONFIG_ARCH_LS1046A)
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_FSL_QMAN_V3
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 8
#define CONFIG_SYS_NUM_FM1_10GEC 2

115
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h Normal file
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@ -0,0 +1,115 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018 NXP
*/
#ifndef _FSL_ICID_H_
#define _FSL_ICID_H_
#include <asm/types.h>
#include <fsl_qbman.h>
#include <fsl_sec.h>
struct icid_id_table {
const char *compat;
u32 id;
u32 reg;
phys_addr_t compat_addr;
phys_addr_t reg_addr;
};
struct fman_icid_id_table {
u32 port_id;
u32 icid;
};
u32 get_ppid_icid(int ppid_tbl_idx, int ppid);
int fdt_get_smmu_phandle(void *blob);
int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids);
void set_icids(void);
void fdt_fixup_icid(void *blob);
#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr) \
{ .compat = name, \
.id = idA, \
.reg = regA, \
.compat_addr = compataddr, \
.reg_addr = addr, \
}
#define SET_SCFG_ICID(compat, streamid, name, compataddr) \
SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \
offsetof(struct ccsr_scfg, name) + CONFIG_SYS_FSL_SCFG_ADDR, \
compataddr)
#define SET_USB_ICID(usb_num, compat, streamid) \
SET_SCFG_ICID(compat, streamid, usb##usb_num##_icid,\
CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
#define SET_SATA_ICID(compat, streamid) \
SET_SCFG_ICID(compat, streamid, sata_icid,\
AHCI_BASE_ADDR)
#define SET_SDHC_ICID(streamid) \
SET_SCFG_ICID("fsl,esdhc", streamid, sdhc_icid,\
CONFIG_SYS_FSL_ESDHC_ADDR)
#define SET_QDMA_ICID(compat, streamid) \
SET_SCFG_ICID(compat, streamid, dma_icid,\
QDMA_BASE_ADDR)
#define SET_EDMA_ICID(streamid) \
SET_SCFG_ICID("fsl,vf610-edma", streamid, edma_icid,\
EDMA_BASE_ADDR)
#define SET_ETR_ICID(streamid) \
SET_SCFG_ICID(NULL, streamid, etr_icid, 0)
#define SET_DEBUG_ICID(streamid) \
SET_SCFG_ICID(NULL, streamid, debug_icid, 0)
#define SET_QMAN_ICID(streamid) \
SET_ICID_ENTRY("fsl,qman", streamid, streamid, \
offsetof(struct ccsr_qman, liodnr) + \
CONFIG_SYS_FSL_QMAN_ADDR, \
CONFIG_SYS_FSL_QMAN_ADDR)
#define SET_BMAN_ICID(streamid) \
SET_ICID_ENTRY("fsl,bman", streamid, streamid, \
offsetof(struct ccsr_bman, liodnr) + \
CONFIG_SYS_FSL_BMAN_ADDR, \
CONFIG_SYS_FSL_BMAN_ADDR)
#define SET_FMAN_ICID_ENTRY(_port_id, streamid) \
{ .port_id = (_port_id), .icid = (streamid) }
#define SET_SEC_QI_ICID(streamid) \
SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
(((streamid) << 16) | (streamid)), \
offsetof(ccsr_sec_t, qilcr_ls) + \
CONFIG_SYS_FSL_SEC_ADDR, \
CONFIG_SYS_FSL_SEC_ADDR)
#define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \
SET_ICID_ENTRY("fsl,sec-v4.0-job-ring", streamid, \
(((streamid) << 16) | (streamid)), \
offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \
CONFIG_SYS_FSL_SEC_ADDR, \
FSL_SEC_JR##jr_num##_BASE_ADDR)
#define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \
SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \
offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \
CONFIG_SYS_FSL_SEC_ADDR, 0)
#define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \
SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \
offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \
CONFIG_SYS_FSL_SEC_ADDR, 0)
extern struct icid_id_table icid_tbl[];
extern struct fman_icid_id_table fman_icid_tbl[];
extern int icid_tbl_sz;
extern int fman_icid_tbl_sz;
#endif

24
arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h Normal file
View File

@ -0,0 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018 NXP
*/
#ifndef _FSL_PORTALS_H_
#define _FSL_PORTALS_H_
struct qportal_info {
u16 dicid; /* DQRR ICID */
u16 ficid; /* frame data ICID */
u16 icid;
u8 sdest;
};
#define SET_QP_INFO(streamid, dest) \
{ .dicid = (streamid), .ficid = (streamid), .icid = (streamid), \
.sdest = (dest) }
extern struct qportal_info qp_info[];
void fdt_portal(void *blob, const char *compat, const char *container,
u64 addr, u32 size);
#endif

15
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
View File

@ -57,8 +57,7 @@
#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0x3E80
#define CONFIG_SYS_QMAN_NUM_PORTALS 10
#define CONFIG_SYS_QMAN_MEM_BASE 0x500000000
#define CONFIG_SYS_QMAN_MEM_PHYS (0xf00000000ull + \
CONFIG_SYS_QMAN_MEM_BASE)
#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
#define CONFIG_SYS_QMAN_MEM_SIZE 0x08000000
#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x10000
#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x10000
@ -88,8 +87,12 @@
#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
#define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x01c00000)
#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
#define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000)
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL
@ -197,10 +200,18 @@ struct sys_info {
#define CONFIG_SYS_FSL_SEC_OFFSET 0x700000ull
#define CONFIG_SYS_FSL_JR0_OFFSET 0x710000ull
#define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET
#define FSL_SEC_JR1_OFFSET 0x720000ull
#define FSL_SEC_JR2_OFFSET 0x730000ull
#define FSL_SEC_JR3_OFFSET 0x740000ull
#define CONFIG_SYS_FSL_SEC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
#define CONFIG_SYS_FSL_JR0_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)
#define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET)
/* Device Configuration and Pin Control */
#define DCFG_DCSR_PORCR1 0x0

81
arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
View File

@ -39,6 +39,7 @@ enum csu_cslx_ind {
CSU_CSLX_ESDHC,
CSU_CSLX_IFC = 45,
CSU_CSLX_I2C1,
CSU_CSLX_USB_2,
CSU_CSLX_I2C3 = 48,
CSU_CSLX_I2C2,
CSU_CSLX_DUART2 = 50,
@ -87,84 +88,4 @@ enum csu_cslx_ind {
CSU_CSLX_DSCR = 121,
};
static struct csu_ns_dev ns_dev[] = {
{CSU_CSLX_PCIE2_IO, CSU_ALL_RW},
{CSU_CSLX_PCIE1_IO, CSU_ALL_RW},
{CSU_CSLX_MG2TPR_IP, CSU_ALL_RW},
{CSU_CSLX_IFC_MEM, CSU_ALL_RW},
{CSU_CSLX_OCRAM, CSU_ALL_RW},
{CSU_CSLX_GIC, CSU_ALL_RW},
{CSU_CSLX_PCIE1, CSU_ALL_RW},
{CSU_CSLX_OCRAM2, CSU_ALL_RW},
{CSU_CSLX_QSPI_MEM, CSU_ALL_RW},
{CSU_CSLX_PCIE2, CSU_ALL_RW},
{CSU_CSLX_SATA, CSU_ALL_RW},
{CSU_CSLX_USB1, CSU_ALL_RW},
{CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW},
{CSU_CSLX_PCIE3, CSU_ALL_RW},
{CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
{CSU_CSLX_USB3, CSU_ALL_RW},
{CSU_CSLX_USB2, CSU_ALL_RW},
{CSU_CSLX_PFE, CSU_ALL_RW},
{CSU_CSLX_SERDES, CSU_ALL_RW},
{CSU_CSLX_QDMA, CSU_ALL_RW},
{CSU_CSLX_LPUART2, CSU_ALL_RW},
{CSU_CSLX_LPUART1, CSU_ALL_RW},
{CSU_CSLX_LPUART4, CSU_ALL_RW},
{CSU_CSLX_LPUART3, CSU_ALL_RW},
{CSU_CSLX_LPUART6, CSU_ALL_RW},
{CSU_CSLX_LPUART5, CSU_ALL_RW},
{CSU_CSLX_DSPI1, CSU_ALL_RW},
{CSU_CSLX_QSPI, CSU_ALL_RW},
{CSU_CSLX_ESDHC, CSU_ALL_RW},
{CSU_CSLX_IFC, CSU_ALL_RW},
{CSU_CSLX_I2C1, CSU_ALL_RW},
{CSU_CSLX_I2C3, CSU_ALL_RW},
{CSU_CSLX_I2C2, CSU_ALL_RW},
{CSU_CSLX_DUART2, CSU_ALL_RW},
{CSU_CSLX_DUART1, CSU_ALL_RW},
{CSU_CSLX_WDT2, CSU_ALL_RW},
{CSU_CSLX_WDT1, CSU_ALL_RW},
{CSU_CSLX_EDMA, CSU_ALL_RW},
{CSU_CSLX_SYS_CNT, CSU_ALL_RW},
{CSU_CSLX_DMA_MUX2, CSU_ALL_RW},
{CSU_CSLX_DMA_MUX1, CSU_ALL_RW},
{CSU_CSLX_DDR, CSU_ALL_RW},
{CSU_CSLX_QUICC, CSU_ALL_RW},
{CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW},
{CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW},
{CSU_CSLX_SFP, CSU_ALL_RW},
{CSU_CSLX_TMU, CSU_ALL_RW},
{CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW},
{CSU_CSLX_SCFG, CSU_ALL_RW},
{CSU_CSLX_FM, CSU_ALL_RW},
{CSU_CSLX_SEC5_5, CSU_ALL_RW},
{CSU_CSLX_BM, CSU_ALL_RW},
{CSU_CSLX_QM, CSU_ALL_RW},
{CSU_CSLX_GPIO2, CSU_ALL_RW},
{CSU_CSLX_GPIO1, CSU_ALL_RW},
{CSU_CSLX_GPIO4, CSU_ALL_RW},
{CSU_CSLX_GPIO3, CSU_ALL_RW},
{CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW},
{CSU_CSLX_CSU, CSU_ALL_RW},
{CSU_CSLX_IIC4, CSU_ALL_RW},
{CSU_CSLX_WDT4, CSU_ALL_RW},
{CSU_CSLX_WDT3, CSU_ALL_RW},
{CSU_CSLX_ESDHC2, CSU_ALL_RW},
{CSU_CSLX_WDT5, CSU_ALL_RW},
{CSU_CSLX_SAI2, CSU_ALL_RW},
{CSU_CSLX_SAI1, CSU_ALL_RW},
{CSU_CSLX_SAI4, CSU_ALL_RW},
{CSU_CSLX_SAI3, CSU_ALL_RW},
{CSU_CSLX_FTM2, CSU_ALL_RW},
{CSU_CSLX_FTM1, CSU_ALL_RW},
{CSU_CSLX_FTM4, CSU_ALL_RW},
{CSU_CSLX_FTM3, CSU_ALL_RW},
{CSU_CSLX_FTM6, CSU_ALL_RW},
{CSU_CSLX_FTM5, CSU_ALL_RW},
{CSU_CSLX_FTM8, CSU_ALL_RW},
{CSU_CSLX_FTM7, CSU_ALL_RW},
{CSU_CSLX_DSCR, CSU_ALL_RW},
};
#endif

1
arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
View File

@ -50,6 +50,7 @@
#define FSL_QDMA_STREAM_ID 7
#define FSL_EDMA_STREAM_ID 8
#define FSL_ETR_STREAM_ID 9
#define FSL_DEBUG_STREAM_ID 10
/* PCI - programmed in PEXn_LUT */
#define FSL_PEX_STREAM_ID_START 11

84
arch/arm/include/asm/arch-ls102xa/ns_access.h
View File

@ -91,88 +91,4 @@ enum csu_cslx_ind {
CSU_CSLX_MAX,
};
static struct csu_ns_dev ns_dev[] = {
{ CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
{ CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
{ CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
{ CSU_CSLX_IFC_MEM, CSU_ALL_RW },
{ CSU_CSLX_OCRAM, CSU_ALL_RW },
{ CSU_CSLX_GIC, CSU_ALL_RW },
{ CSU_CSLX_PCIE1, CSU_ALL_RW },
{ CSU_CSLX_OCRAM2, CSU_ALL_RW },
{ CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
{ CSU_CSLX_PCIE2, CSU_ALL_RW },
{ CSU_CSLX_SATA, CSU_ALL_RW },
{ CSU_CSLX_USB3, CSU_ALL_RW },
{ CSU_CSLX_SERDES, CSU_ALL_RW },
{ CSU_CSLX_QDMA, CSU_ALL_RW },
{ CSU_CSLX_LPUART2, CSU_ALL_RW },
{ CSU_CSLX_LPUART1, CSU_ALL_RW },
{ CSU_CSLX_LPUART4, CSU_ALL_RW },
{ CSU_CSLX_LPUART3, CSU_ALL_RW },
{ CSU_CSLX_LPUART6, CSU_ALL_RW },
{ CSU_CSLX_LPUART5, CSU_ALL_RW },
{ CSU_CSLX_DSPI2, CSU_ALL_RW },
{ CSU_CSLX_DSPI1, CSU_ALL_RW },
{ CSU_CSLX_QSPI, CSU_ALL_RW },
{ CSU_CSLX_ESDHC, CSU_ALL_RW },
{ CSU_CSLX_2D_ACE, CSU_ALL_RW },
{ CSU_CSLX_IFC, CSU_ALL_RW },
{ CSU_CSLX_I2C1, CSU_ALL_RW },
{ CSU_CSLX_USB2, CSU_ALL_RW },
{ CSU_CSLX_I2C3, CSU_ALL_RW },
{ CSU_CSLX_I2C2, CSU_ALL_RW },
{ CSU_CSLX_DUART2, CSU_ALL_RW },
{ CSU_CSLX_DUART1, CSU_ALL_RW },
{ CSU_CSLX_WDT2, CSU_ALL_RW },
{ CSU_CSLX_WDT1, CSU_ALL_RW },
{ CSU_CSLX_EDMA, CSU_ALL_RW },
{ CSU_CSLX_SYS_CNT, CSU_ALL_RW },
{ CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
{ CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
{ CSU_CSLX_DDR, CSU_ALL_RW },
{ CSU_CSLX_QUICC, CSU_ALL_RW },
{ CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
{ CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
{ CSU_CSLX_SFP, CSU_ALL_RW },
{ CSU_CSLX_TMU, CSU_ALL_RW },
{ CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
{ CSU_CSLX_RESERVED0, CSU_ALL_RW },
{ CSU_CSLX_ETSEC1, CSU_ALL_RW },
{ CSU_CSLX_SEC5_5, CSU_ALL_RW },
{ CSU_CSLX_ETSEC3, CSU_ALL_RW },
{ CSU_CSLX_ETSEC2, CSU_ALL_RW },
{ CSU_CSLX_GPIO2, CSU_ALL_RW },
{ CSU_CSLX_GPIO1, CSU_ALL_RW },
{ CSU_CSLX_GPIO4, CSU_ALL_RW },
{ CSU_CSLX_GPIO3, CSU_ALL_RW },
{ CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
{ CSU_CSLX_CSU, CSU_ALL_RW },
{ CSU_CSLX_ASRC, CSU_ALL_RW },
{ CSU_CSLX_SPDIF, CSU_ALL_RW },
{ CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
{ CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
{ CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
{ CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
{ CSU_CSLX_SAI2, CSU_ALL_RW },
{ CSU_CSLX_SAI1, CSU_ALL_RW },
{ CSU_CSLX_SAI4, CSU_ALL_RW },
{ CSU_CSLX_SAI3, CSU_ALL_RW },
{ CSU_CSLX_FTM2, CSU_ALL_RW },
{ CSU_CSLX_FTM1, CSU_ALL_RW },
{ CSU_CSLX_FTM4, CSU_ALL_RW },
{ CSU_CSLX_FTM3, CSU_ALL_RW },
{ CSU_CSLX_FTM6, CSU_ALL_RW },
{ CSU_CSLX_FTM5, CSU_ALL_RW },
{ CSU_CSLX_FTM8, CSU_ALL_RW },
{ CSU_CSLX_FTM7, CSU_ALL_RW },
{ CSU_CSLX_COP_DCSR, CSU_ALL_RW },
{ CSU_CSLX_EPU, CSU_ALL_RW },
{ CSU_CSLX_GDI, CSU_ALL_RW },
{ CSU_CSLX_DDI, CSU_ALL_RW },
{ CSU_CSLX_RESERVED1, CSU_ALL_RW },
{ CSU_CSLX_USB3_PHY, CSU_ALL_RW },
{ CSU_CSLX_RESERVED2, CSU_ALL_RW },
};
#endif

167
board/freescale/common/ns_access.c
View File

@ -9,6 +9,173 @@
#include <asm/arch/ns_access.h>
#include <asm/arch/fsl_serdes.h>
#ifdef CONFIG_ARCH_LS1021A
static struct csu_ns_dev ns_dev[] = {
{ CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
{ CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
{ CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
{ CSU_CSLX_IFC_MEM, CSU_ALL_RW },
{ CSU_CSLX_OCRAM, CSU_ALL_RW },
{ CSU_CSLX_GIC, CSU_ALL_RW },
{ CSU_CSLX_PCIE1, CSU_ALL_RW },
{ CSU_CSLX_OCRAM2, CSU_ALL_RW },
{ CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
{ CSU_CSLX_PCIE2, CSU_ALL_RW },
{ CSU_CSLX_SATA, CSU_ALL_RW },
{ CSU_CSLX_USB3, CSU_ALL_RW },
{ CSU_CSLX_SERDES, CSU_ALL_RW },
{ CSU_CSLX_QDMA, CSU_ALL_RW },
{ CSU_CSLX_LPUART2, CSU_ALL_RW },
{ CSU_CSLX_LPUART1, CSU_ALL_RW },
{ CSU_CSLX_LPUART4, CSU_ALL_RW },
{ CSU_CSLX_LPUART3, CSU_ALL_RW },
{ CSU_CSLX_LPUART6, CSU_ALL_RW },
{ CSU_CSLX_LPUART5, CSU_ALL_RW },
{ CSU_CSLX_DSPI2, CSU_ALL_RW },
{ CSU_CSLX_DSPI1, CSU_ALL_RW },
{ CSU_CSLX_QSPI, CSU_ALL_RW },
{ CSU_CSLX_ESDHC, CSU_ALL_RW },
{ CSU_CSLX_2D_ACE, CSU_ALL_RW },
{ CSU_CSLX_IFC, CSU_ALL_RW },
{ CSU_CSLX_I2C1, CSU_ALL_RW },
{ CSU_CSLX_USB2, CSU_ALL_RW },
{ CSU_CSLX_I2C3, CSU_ALL_RW },
{ CSU_CSLX_I2C2, CSU_ALL_RW },
{ CSU_CSLX_DUART2, CSU_ALL_RW },
{ CSU_CSLX_DUART1, CSU_ALL_RW },
{ CSU_CSLX_WDT2, CSU_ALL_RW },
{ CSU_CSLX_WDT1, CSU_ALL_RW },
{ CSU_CSLX_EDMA, CSU_ALL_RW },
{ CSU_CSLX_SYS_CNT, CSU_ALL_RW },
{ CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
{ CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
{ CSU_CSLX_DDR, CSU_ALL_RW },
{ CSU_CSLX_QUICC, CSU_ALL_RW },
{ CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
{ CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
{ CSU_CSLX_SFP, CSU_ALL_RW },
{ CSU_CSLX_TMU, CSU_ALL_RW },
{ CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
{ CSU_CSLX_RESERVED0, CSU_ALL_RW },
{ CSU_CSLX_ETSEC1, CSU_ALL_RW },
{ CSU_CSLX_SEC5_5, CSU_ALL_RW },
{ CSU_CSLX_ETSEC3, CSU_ALL_RW },
{ CSU_CSLX_ETSEC2, CSU_ALL_RW },
{ CSU_CSLX_GPIO2, CSU_ALL_RW },
{ CSU_CSLX_GPIO1, CSU_ALL_RW },
{ CSU_CSLX_GPIO4, CSU_ALL_RW },
{ CSU_CSLX_GPIO3, CSU_ALL_RW },
{ CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
{ CSU_CSLX_CSU, CSU_ALL_RW },
{ CSU_CSLX_ASRC, CSU_ALL_RW },
{ CSU_CSLX_SPDIF, CSU_ALL_RW },
{ CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
{ CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
{ CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
{ CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
{ CSU_CSLX_SAI2, CSU_ALL_RW },
{ CSU_CSLX_SAI1, CSU_ALL_RW },
{ CSU_CSLX_SAI4, CSU_ALL_RW },
{ CSU_CSLX_SAI3, CSU_ALL_RW },
{ CSU_CSLX_FTM2, CSU_ALL_RW },
{ CSU_CSLX_FTM1, CSU_ALL_RW },
{ CSU_CSLX_FTM4, CSU_ALL_RW },
{ CSU_CSLX_FTM3, CSU_ALL_RW },
{ CSU_CSLX_FTM6, CSU_ALL_RW },
{ CSU_CSLX_FTM5, CSU_ALL_RW },
{ CSU_CSLX_FTM8, CSU_ALL_RW },
{ CSU_CSLX_FTM7, CSU_ALL_RW },
{ CSU_CSLX_COP_DCSR, CSU_ALL_RW },
{ CSU_CSLX_EPU, CSU_ALL_RW },
{ CSU_CSLX_GDI, CSU_ALL_RW },
{ CSU_CSLX_DDI, CSU_ALL_RW },
{ CSU_CSLX_RESERVED1, CSU_ALL_RW },
{ CSU_CSLX_USB3_PHY, CSU_ALL_RW },
{ CSU_CSLX_RESERVED2, CSU_ALL_RW },
};
#else
static struct csu_ns_dev ns_dev[] = {
{CSU_CSLX_PCIE2_IO, CSU_ALL_RW},
{CSU_CSLX_PCIE1_IO, CSU_ALL_RW},
{CSU_CSLX_MG2TPR_IP, CSU_ALL_RW},
{CSU_CSLX_IFC_MEM, CSU_ALL_RW},
{CSU_CSLX_OCRAM, CSU_ALL_RW},
{CSU_CSLX_GIC, CSU_ALL_RW},
{CSU_CSLX_PCIE1, CSU_ALL_RW},
{CSU_CSLX_OCRAM2, CSU_ALL_RW},
{CSU_CSLX_QSPI_MEM, CSU_ALL_RW},
{CSU_CSLX_PCIE2, CSU_ALL_RW},
{CSU_CSLX_SATA, CSU_ALL_RW},
{CSU_CSLX_USB1, CSU_ALL_RW},
{CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW},
{CSU_CSLX_PCIE3, CSU_ALL_RW},
{CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
{CSU_CSLX_USB3, CSU_ALL_RW},
{CSU_CSLX_USB2, CSU_ALL_RW},
{CSU_CSLX_PFE, CSU_ALL_RW},
{CSU_CSLX_SERDES, CSU_ALL_RW},
{CSU_CSLX_QDMA, CSU_ALL_RW},
{CSU_CSLX_LPUART2, CSU_ALL_RW},
{CSU_CSLX_LPUART1, CSU_ALL_RW},
{CSU_CSLX_LPUART4, CSU_ALL_RW},
{CSU_CSLX_LPUART3, CSU_ALL_RW},
{CSU_CSLX_LPUART6, CSU_ALL_RW},
{CSU_CSLX_LPUART5, CSU_ALL_RW},
{CSU_CSLX_DSPI1, CSU_ALL_RW},
{CSU_CSLX_QSPI, CSU_ALL_RW},
{CSU_CSLX_ESDHC, CSU_ALL_RW},
{CSU_CSLX_IFC, CSU_ALL_RW},
{CSU_CSLX_I2C1, CSU_ALL_RW},
{CSU_CSLX_I2C3, CSU_ALL_RW},
{CSU_CSLX_I2C2, CSU_ALL_RW},
{CSU_CSLX_DUART2, CSU_ALL_RW},
{CSU_CSLX_DUART1, CSU_ALL_RW},
{CSU_CSLX_WDT2, CSU_ALL_RW},
{CSU_CSLX_WDT1, CSU_ALL_RW},
{CSU_CSLX_EDMA, CSU_ALL_RW},
{CSU_CSLX_SYS_CNT, CSU_ALL_RW},
{CSU_CSLX_DMA_MUX2, CSU_ALL_RW},
{CSU_CSLX_DMA_MUX1, CSU_ALL_RW},
{CSU_CSLX_DDR, CSU_ALL_RW},
{CSU_CSLX_QUICC, CSU_ALL_RW},
{CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW},
{CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW},
{CSU_CSLX_SFP, CSU_ALL_RW},
{CSU_CSLX_TMU, CSU_ALL_RW},
{CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW},
{CSU_CSLX_SCFG, CSU_ALL_RW},
{CSU_CSLX_FM, CSU_ALL_RW},
{CSU_CSLX_SEC5_5, CSU_ALL_RW},
{CSU_CSLX_BM, CSU_ALL_RW},
{CSU_CSLX_QM, CSU_ALL_RW},
{CSU_CSLX_GPIO2, CSU_ALL_RW},
{CSU_CSLX_GPIO1, CSU_ALL_RW},
{CSU_CSLX_GPIO4, CSU_ALL_RW},
{CSU_CSLX_GPIO3, CSU_ALL_RW},
{CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW},
{CSU_CSLX_CSU, CSU_ALL_RW},
{CSU_CSLX_IIC4, CSU_ALL_RW},
{CSU_CSLX_WDT4, CSU_ALL_RW},
{CSU_CSLX_WDT3, CSU_ALL_RW},
{CSU_CSLX_ESDHC2, CSU_ALL_RW},
{CSU_CSLX_WDT5, CSU_ALL_RW},
{CSU_CSLX_SAI2, CSU_ALL_RW},
{CSU_CSLX_SAI1, CSU_ALL_RW},
{CSU_CSLX_SAI4, CSU_ALL_RW},
{CSU_CSLX_SAI3, CSU_ALL_RW},
{CSU_CSLX_FTM2, CSU_ALL_RW},
{CSU_CSLX_FTM1, CSU_ALL_RW},
{CSU_CSLX_FTM4, CSU_ALL_RW},
{CSU_CSLX_FTM3, CSU_ALL_RW},
{CSU_CSLX_FTM6, CSU_ALL_RW},
{CSU_CSLX_FTM5, CSU_ALL_RW},
{CSU_CSLX_FTM8, CSU_ALL_RW},
{CSU_CSLX_FTM7, CSU_ALL_RW},
{CSU_CSLX_DSCR, CSU_ALL_RW},
};
#endif
void set_devices_ns_access(unsigned long index, u16 val)
{
u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;

85
board/freescale/ls1012ardb/ls1012ardb.c
View File

@ -25,6 +25,9 @@
DECLARE_GLOBAL_DATA_PTR;
#define BOOT_FROM_UPPER_BANK 0x2
#define BOOT_FROM_LOWER_BANK 0x1
int checkboard(void)
{
#ifdef CONFIG_TARGET_LS1012ARDB
@ -211,3 +214,85 @@ int ft_board_setup(void *blob, bd_t *bd)
return 0;
}
static int switch_to_bank1(void)
{
u8 data;
int ret;
i2c_set_bus_num(0);
data = 0xf4;
ret = i2c_write(0x24, 0x3, 1, &data, 1);
if (ret) {
printf("i2c write error to chip : %u, addr : %u, data : %u\n",
0x24, 0x3, data);
}
return ret;
}
static int switch_to_bank2(void)
{
u8 data;
int ret;
i2c_set_bus_num(0);
data = 0xfc;
ret = i2c_write(0x24, 0x7, 1, &data, 1);
if (ret) {
printf("i2c write error to chip : %u, addr : %u, data : %u\n",
0x24, 0x7, data);
goto err;
}
data = 0xf5;
ret = i2c_write(0x24, 0x3, 1, &data, 1);
if (ret) {
printf("i2c write error to chip : %u, addr : %u, data : %u\n",
0x24, 0x3, data);
}
err:
return ret;
}
static int convert_flash_bank(int bank)
{
int ret = 0;
switch (bank) {
case BOOT_FROM_UPPER_BANK:
ret = switch_to_bank2();
break;
case BOOT_FROM_LOWER_BANK:
ret = switch_to_bank1();
break;
default:
ret = CMD_RET_USAGE;
break;
};
return ret;
}
static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
if (argc != 2)
return CMD_RET_USAGE;
if (strcmp(argv[1], "1") == 0)
convert_flash_bank(BOOT_FROM_LOWER_BANK);
else if (strcmp(argv[1], "2") == 0)
convert_flash_bank(BOOT_FROM_UPPER_BANK);
else
return CMD_RET_USAGE;
return 0;
}
U_BOOT_CMD(
boot_bank, 2, 0, flash_bank_cmd,
"Flash bank Selection Control",
"bank[1-lower bank/2-upper bank] (e.g. boot_bank 1)"
);

3
board/freescale/ls1046aqds/ls1046aqds.c
View File

@ -14,6 +14,7 @@
#include <asm/arch/fdt.h>
#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include <ahci.h>
#include <hwconfig.h>
#include <mmc.h>
@ -309,6 +310,8 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_board_enet(blob);
#endif
fdt_fixup_icid(blob);
reg = QIXIS_READ(brdcfg[0]);
reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;

3
board/freescale/ls1046ardb/ls1046ardb.c
View File

@ -11,6 +11,7 @@
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/ppa.h>
#include <asm/arch/soc.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include <hwconfig.h>
#include <ahci.h>
#include <mmc.h>
@ -174,6 +175,8 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_fman_ethernet(blob);
#endif
fdt_fixup_icid(blob);
return 0;
}
#endif

4
configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
View File

@ -48,6 +48,10 @@ CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y

45
drivers/misc/fsl_portals.c
View File

@ -13,6 +13,9 @@
#ifdef CONFIG_PPC
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#else
#include <asm/arch-fsl-layerscape/fsl_portals.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#endif
#include <fsl_qbman.h>
@ -24,7 +27,6 @@ void setup_qbman_portals(void)
CONFIG_SYS_BMAN_SWP_ISDR_REG;
void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE +
CONFIG_SYS_QMAN_SWP_ISDR_REG;
#ifdef CONFIG_PPC
struct ccsr_qman *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
/* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
@ -32,7 +34,6 @@ void setup_qbman_portals(void)
out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
#endif
out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
#endif
#ifdef CONFIG_FSL_CORENET
int i;
@ -47,6 +48,22 @@ void setup_qbman_portals(void)
/* set frame liodn */
out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn);
}
#else
#ifdef CONFIG_ARCH_LS1046A
int i;
for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
u8 sdest = qp_info[i].sdest;
u16 ficid = qp_info[i].ficid;
u16 dicid = qp_info[i].dicid;
u16 icid = qp_info[i].icid;
out_be32(&qman->qcsp[i].qcsp_lio_cfg, (icid << 16) |
dicid);
/* set frame icid */
out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | ficid);
}
#endif
#endif
/* Change default state of BMan ISDR portals to all 1s */
@ -180,6 +197,10 @@ void fdt_fixup_qportals(void *blob)
char compat[64];
int compat_len;
#ifdef CONFIG_ARCH_LS1046A
int smmu_ph = fdt_get_smmu_phandle(blob);
#endif
maj = (rev_1 >> 8) & 0xff;
min = rev_1 & 0xff;
ip_cfg = rev_2 & 0xff;
@ -190,7 +211,7 @@ void fdt_fixup_qportals(void *blob)
off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
while (off != -FDT_ERR_NOTFOUND) {
#ifdef CONFIG_PPC
#if defined(CONFIG_PPC) || defined(CONFIG_ARCH_LS1046A)
#ifdef CONFIG_FSL_CORENET
u32 liodns[2];
#endif
@ -200,12 +221,12 @@ void fdt_fixup_qportals(void *blob)
if (!ci)
goto err;
i = *ci;
#ifdef CONFIG_SYS_DPAA_FMAN
i = fdt32_to_cpu(*ci);
#if defined(CONFIG_SYS_DPAA_FMAN) && defined(CONFIG_PPC)
int j;
#endif
#endif /* CONFIG_PPC */
#endif /* CONFIG_PPC || CONFIG_ARCH_LS1046A */
err = fdt_setprop(blob, off, "compatible", compat, compat_len);
if (err < 0)
goto err;
@ -253,6 +274,18 @@ void fdt_fixup_qportals(void *blob)
if (err < 0)
goto err;
#endif
#else
#ifdef CONFIG_ARCH_LS1046A
if (smmu_ph >= 0) {
u32 icids[3];
icids[0] = qp_info[i].icid;
icids[1] = qp_info[i].dicid;
icids[2] = qp_info[i].ficid;
fdt_set_iommu_prop(blob, off, smmu_ph, icids, 3);
}
#endif
#endif /* CONFIG_PPC */
err:

69
drivers/mtd/nand/fsl_ifc_nand.c
View File

@ -242,31 +242,6 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
ctrl->index += mtd->writesize;
}
static int is_blank(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
unsigned int bufnum)
{
struct nand_chip *chip = mtd_to_nand(mtd);
struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
u32 __iomem *main = (u32 *)addr;
u8 __iomem *oob = addr + mtd->writesize;
int i;
for (i = 0; i < mtd->writesize / 4; i++) {
if (__raw_readl(&main[i]) != 0xffffffff)
return 0;
}
for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
int pos = chip->ecc.layout->eccpos[i];
if (__raw_readb(&oob[pos]) != 0xff)
return 0;
}
return 1;
}
/* returns nonzero if entire page is blank */
static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
u32 eccstat, unsigned int bufnum)
@ -331,16 +306,14 @@ static int fsl_ifc_run_command(struct mtd_info *mtd)
if (errors == 15) {
/*
* Uncorrectable error.
* OK only if the whole page is blank.
* We'll check for blank pages later.
*
* We disable ECCER reporting due to erratum
* IFC-A002770 -- so report it now if we
* see an uncorrectable error in ECCSTAT.
*/
if (!is_blank(mtd, ctrl, bufnum))
ctrl->status |=
IFC_NAND_EVTER_STAT_ECCER;
break;
ctrl->status |= IFC_NAND_EVTER_STAT_ECCER;
continue;
}
mtd->ecc_stats.corrected += errors;
@ -727,6 +700,39 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
return status | NAND_STATUS_WP;
}
/*
* The controller does not check for bitflips in erased pages,
* therefore software must check instead.
*/
static int
check_erased_page(struct nand_chip *chip, u8 *buf, struct mtd_info *mtd)
{
u8 *ecc = chip->oob_poi;
const int ecc_size = chip->ecc.bytes;
const int pkt_size = chip->ecc.size;
int i, res, bitflips;
/* IFC starts ecc bytes at offset 8 in the spare area. */
ecc += 8;
bitflips = 0;
for (i = 0; i < chip->ecc.steps; i++) {
res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size,
NULL, 0, chip->ecc.strength);
if (res < 0) {
printf("fsl-ifc: NAND Flash ECC Uncorrectable Error\n");
mtd->ecc_stats.failed++;
} else if (res > 0) {
mtd->ecc_stats.corrected += res;
}
bitflips = max(res, bitflips);
buf += pkt_size;
ecc += ecc_size;
}
return bitflips;
}
static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
uint8_t *buf, int oob_required, int page)
{
@ -736,6 +742,9 @@ static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
fsl_ifc_read_buf(mtd, buf, mtd->writesize);
fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
if (ctrl->status & IFC_NAND_EVTER_STAT_ECCER)
return check_erased_page(chip, buf, mtd);
if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
mtd->ecc_stats.failed++;

6
drivers/net/fsl-mc/mc.c
View File

@ -322,7 +322,7 @@ static int mc_fixup_dpc_mac_addr(void *blob, int dpmac_id,
static int mc_fixup_mac_addrs(void *blob, enum mc_fixup_type type)
{
int i, err = 0, ret = 0;
char ethname[10];
char ethname[ETH_NAME_LEN];
struct eth_device *eth_dev;
for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
@ -331,8 +331,8 @@ static int mc_fixup_mac_addrs(void *blob, enum mc_fixup_type type)
(wriop_get_phy_address(i) == -1))
continue;
sprintf(ethname, "DPMAC%d@%s", i,
phy_interface_strings[wriop_get_enet_if(i)]);
snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s", i,
phy_interface_strings[wriop_get_enet_if(i)]);
eth_dev = eth_get_dev_by_name(ethname);
if (eth_dev == NULL)

4
drivers/net/ldpaa_eth/ldpaa_eth.c
View File

@ -993,8 +993,8 @@ static int ldpaa_eth_netdev_init(struct eth_device *net_dev,
int err;
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
sprintf(net_dev->name, "DPMAC%d@%s", priv->dpmac_id,
phy_interface_strings[enet_if]);
snprintf(net_dev->name, ETH_NAME_LEN, "DPMAC%d@%s", priv->dpmac_id,
phy_interface_strings[enet_if]);
net_dev->iobase = 0;
net_dev->init = ldpaa_eth_open;

6
drivers/pci/fsl_pci_init.c
View File

@ -321,6 +321,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
pci_setup_indirect(hose, cfg_addr, cfg_data);
#ifdef PEX_CCB_DIV
/* Configure the PCIE controller core clock ratio */
pci_hose_write_config_dword(hose, dev, 0x440,
((gd->bus_clk / 1000000) *
(16 / PEX_CCB_DIV)) / 333);
#endif
block_rev = in_be32(&pci->block_rev1);
if (PEX_IP_BLK_REV_2_2 <= block_rev) {
pi = &pci->pit[2]; /* 0xDC0 */

2
include/net.h
View File

@ -164,7 +164,7 @@ void eth_halt_state_only(void); /* Set passive state */
#ifndef CONFIG_DM_ETH
struct eth_device {
#define ETH_NAME_LEN 16
#define ETH_NAME_LEN 20
char name[ETH_NAME_LEN];
unsigned char enetaddr[ARP_HLEN];
phys_addr_t iobase;