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Merge tag 'u-boot-imx-2019-02-16' of git://git.denx.de/u-boot-imx

Browse Source 
u-boot-imx-2019-02-16
---------------------

- vhybrid: add calibration
- gw_ventana: fixes
- Improve documentation for Secure Boot (HABv4)
- Fix Marvell Switch
- MX6 Sabre, switch to DM
- Fixes for NAND
This commit is contained in:
Tom Rini
2019-02-16 08:31:05 -05:00
parent d391c13c99 6ed4d26c21
commit b89074f650
70 changed files with 5154 additions and 768 deletions
Download Patch File Download Diff File Expand all files Collapse all files

91
board/freescale/mx6sabreauto/mx6sabreauto.c
View File

@@ -159,44 +159,6 @@ static iomux_v3_cfg_t const port_exp[] = {
IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
/*Define for building port exp gpio, pin starts from 0*/
#define PORTEXP_IO_NR(chip, pin) \
((chip << 5) + pin)
/*Get the chip addr from a ioexp gpio*/
#define PORTEXP_IO_TO_CHIP(gpio_nr) \
(gpio_nr >> 5)
/*Get the pin number from a ioexp gpio*/
#define PORTEXP_IO_TO_PIN(gpio_nr) \
(gpio_nr & 0x1f)
static int port_exp_direction_output(unsigned gpio, int value)
{
int ret;
i2c_set_bus_num(2);
ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
if (ret)
return ret;
ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
(1 << PORTEXP_IO_TO_PIN(gpio)),
(PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
if (ret)
return ret;
ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
(1 << PORTEXP_IO_TO_PIN(gpio)),
(value << PORTEXP_IO_TO_PIN(gpio)));
if (ret)
return ret;
return 0;
}
#ifdef CONFIG_MTD_NOR_FLASH
static iomux_v3_cfg_t const eimnor_pads[] = {
IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
@@ -501,6 +463,7 @@ iomux_v3_cfg_t const backlight_pads[] = {
static void setup_iomux_backlight(void)
{
gpio_request(IMX_GPIO_NR(2, 9), "backlight");
gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
SETUP_IOMUX_PADS(backlight_pads);
}
@@ -594,6 +557,7 @@ int board_init(void)
else
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
/* I2C 3 Steer */
gpio_request(IMX_GPIO_NR(5, 4), "steer logic");
gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
SETUP_IOMUX_PADS(i2c3_pads);
#ifndef CONFIG_SYS_FLASH_CFI
@@ -602,6 +566,7 @@ int board_init(void)
else
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
#endif
gpio_request(IMX_GPIO_NR(1, 15), "expander en");
gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
SETUP_IOMUX_PADS(port_exp);
@@ -678,19 +643,10 @@ int checkboard(void)
}
#ifdef CONFIG_USB_EHCI_MX6
#define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7)
#define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1)
iomux_v3_cfg_t const usb_otg_pads[] = {
IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
int board_ehci_hcd_init(int port)
{
switch (port) {
case 0:
SETUP_IOMUX_PADS(usb_otg_pads);
/*
* Set daisy chain for otg_pin_id on 6q.
* For 6dl, this bit is reserved.
@@ -705,29 +661,6 @@ int board_ehci_hcd_init(int port)
}
return 0;
}
int board_ehci_power(int port, int on)
{
switch (port) {
case 0:
if (on)
port_exp_direction_output(USB_OTG_PWR, 1);
else
port_exp_direction_output(USB_OTG_PWR, 0);
break;
case 1:
if (on)
port_exp_direction_output(USB_HOST1_PWR, 1);
else
port_exp_direction_output(USB_HOST1_PWR, 0);
break;
default:
printf("MXC USB port %d not yet supported\n", port);
return -EINVAL;
}
return 0;
}
#endif
#ifdef CONFIG_SPL_BUILD
@@ -1097,3 +1030,21 @@ void board_init_f(ulong dummy)
board_init_r(NULL, 0);
}
#endif
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
if (is_mx6dq()) {
if (!strcmp(name, "imx6q-sabreauto"))
return 0;
} else if (is_mx6dqp()) {
if (!strcmp(name, "imx6qp-sabreauto"))
return 0;
} else if (is_mx6dl()) {
if (!strcmp(name, "imx6dl-sabreauto"))
return 0;
}
return -1;
}
#endif

78
board/freescale/mx6sabresd/mx6sabresd.c
View File

@@ -94,12 +94,6 @@ static iomux_v3_cfg_t const enet_pads[] = {
static void setup_iomux_enet(void)
{
SETUP_IOMUX_PADS(enet_pads);
/* Reset AR8031 PHY */
gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
mdelay(10);
gpio_set_value(IMX_GPIO_NR(1, 25), 1);
udelay(100);
}
static iomux_v3_cfg_t const usdhc2_pads[] = {
@@ -189,6 +183,7 @@ static iomux_v3_cfg_t const bl_pads[] = {
static void enable_backlight(void)
{
SETUP_IOMUX_PADS(bl_pads);
gpio_request(DISP0_PWR_EN, "Display Power Enable");
gpio_direction_output(DISP0_PWR_EN, 1);
}
@@ -307,11 +302,13 @@ int board_mmc_init(bd_t *bis)
switch (i) {
case 0:
SETUP_IOMUX_PADS(usdhc2_pads);
gpio_request(USDHC2_CD_GPIO, "USDHC2 CD");
gpio_direction_input(USDHC2_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
break;
case 1:
SETUP_IOMUX_PADS(usdhc3_pads);
gpio_request(USDHC3_CD_GPIO, "USDHC3 CD");
gpio_direction_input(USDHC3_CD_GPIO);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
break;
@@ -559,63 +556,13 @@ int board_eth_init(bd_t *bis)
}
#ifdef CONFIG_USB_EHCI_MX6
#define USB_OTHERREGS_OFFSET 0x800
#define UCTRL_PWR_POL (1 << 9)
static iomux_v3_cfg_t const usb_otg_pads[] = {
IOMUX_PADS(PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static iomux_v3_cfg_t const usb_hc1_pads[] = {
IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static void setup_usb(void)
{
SETUP_IOMUX_PADS(usb_otg_pads);
/*
* set daisy chain for otg_pin_id on 6q.
* for 6dl, this bit is reserved
*/
imx_iomux_set_gpr_register(1, 13, 1, 0);
SETUP_IOMUX_PADS(usb_hc1_pads);
}
int board_ehci_hcd_init(int port)
{
u32 *usbnc_usb_ctrl;
if (port > 1)
return -EINVAL;
usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
port * 4);
setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
return 0;
}
int board_ehci_power(int port, int on)
{
switch (port) {
case 0:
break;
case 1:
if (on)
gpio_direction_output(IMX_GPIO_NR(1, 29), 1);
else
gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
break;
default:
printf("MXC USB port %d not yet supported\n", port);
return -EINVAL;
}
return 0;
}
#endif
@@ -729,6 +676,7 @@ int checkboard(void)
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
gpio_request(KEY_VOL_UP, "KEY Volume UP");
gpio_direction_input(KEY_VOL_UP);
/* Only enter in Falcon mode if KEY_VOL_UP is pressed */
@@ -1062,3 +1010,21 @@ void board_init_f(ulong dummy)
board_init_r(NULL, 0);
}
#endif
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
if (is_mx6dq()) {
if (!strcmp(name, "imx6q-sabresd"))
return 0;
} else if (is_mx6dqp()) {
if (!strcmp(name, "imx6qp-sabresd"))
return 0;
} else if (is_mx6dl()) {
if (!strcmp(name, "imx6dl-sabresd"))
return 0;
}
return -1;
}
#endif

514
board/gateworks/gw_ventana/common.c
View File

@@ -18,12 +18,6 @@
#include "common.h"
/* UART1: Function varies per baseboard */
static iomux_v3_cfg_t const uart1_pads[] = {
IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
/* UART2: Serial Console */
static iomux_v3_cfg_t const uart2_pads[] = {
IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
@@ -32,7 +26,6 @@ static iomux_v3_cfg_t const uart2_pads[] = {
void setup_iomux_uart(void)
{
SETUP_IOMUX_PADS(uart1_pads);
SETUP_IOMUX_PADS(uart2_pads);
}
@@ -85,95 +78,96 @@ static iomux_v3_cfg_t const usdhc3_pads[] = {
IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
/* I2C1: GSC */
static struct i2c_pads_info mx6q_i2c_pad_info0 = {
.scl = {
.i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
.gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
.gp = IMX_GPIO_NR(3, 21)
},
.sda = {
.i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
.gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
.gp = IMX_GPIO_NR(3, 28)
}
};
static struct i2c_pads_info mx6dl_i2c_pad_info0 = {
.scl = {
.i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
.gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
.gp = IMX_GPIO_NR(3, 21)
},
.sda = {
.i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
.gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
.gp = IMX_GPIO_NR(3, 28)
/*
* I2C pad configs:
* I2C1: GSC
* I2C2: PMIC,PCIe Switch,Clock,Mezz
* I2C3: Multimedia/Expansion
*/
static struct i2c_pads_info mx6q_i2c_pad_info[] = {
{
.scl = {
.i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
.gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
.gp = IMX_GPIO_NR(3, 21)
},
.sda = {
.i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
.gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
.gp = IMX_GPIO_NR(3, 28)
}
}, {
.scl = {
.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
.gp = IMX_GPIO_NR(4, 13)
}
}, {
.scl = {
.i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
.gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
.gp = IMX_GPIO_NR(1, 3)
},
.sda = {
.i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
.gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
.gp = IMX_GPIO_NR(1, 6)
}
}
};
/* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
static struct i2c_pads_info mx6q_i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
.gp = IMX_GPIO_NR(4, 13)
}
};
static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
.gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
.i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
.gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
.gp = IMX_GPIO_NR(4, 13)
static struct i2c_pads_info mx6dl_i2c_pad_info[] = {
{
.scl = {
.i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
.gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
.gp = IMX_GPIO_NR(3, 21)
},
.sda = {
.i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
.gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
.gp = IMX_GPIO_NR(3, 28)
}
}, {
.scl = {
.i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
.gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
.i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
.gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
.gp = IMX_GPIO_NR(4, 13)
}
}, {
.scl = {
.i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
.gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
.gp = IMX_GPIO_NR(1, 3)
},
.sda = {
.i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
.gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
.gp = IMX_GPIO_NR(1, 6)
}
}
};
/* I2C3: Misc/Expansion */
static struct i2c_pads_info mx6q_i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
.gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
.gp = IMX_GPIO_NR(1, 3)
},
.sda = {
.i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
.gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
.gp = IMX_GPIO_NR(1, 6)
}
};
static struct i2c_pads_info mx6dl_i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
.gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
.gp = IMX_GPIO_NR(1, 3)
},
.sda = {
.i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
.gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
.gp = IMX_GPIO_NR(1, 6)
}
};
void setup_ventana_i2c(void)
void setup_ventana_i2c(int i2c)
{
if (is_cpu_type(MXC_CPU_MX6Q)) {
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
} else {
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
}
struct i2c_pads_info *p;
if (is_cpu_type(MXC_CPU_MX6Q))
p = &mx6q_i2c_pad_info[i2c];
else
p = &mx6dl_i2c_pad_info[i2c];
setup_i2c(i2c, CONFIG_SYS_I2C_SPEED, 0x7f, p);
}
/*
@@ -395,6 +389,51 @@ static iomux_v3_cfg_t const gw560x_gpio_pads[] = {
IOMUX_PADS(PAD_DISP0_DAT5__GPIO4_IO26 | DIO_PAD_CFG),
};
static iomux_v3_cfg_t const gw5901_gpio_pads[] = {
/* MX6_LOCLED# */
IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
/* ETH1_EN */
IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG),
/* CAN_STBY */
IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
/* PCI_RST# */
IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
/* PMIC reset */
IOMUX_PADS(PAD_DISP0_DAT8__WDOG1_B | DIO_PAD_CFG),
/* COM_CFGA/B/C/D */
IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14 | DIO_PAD_CFG),
IOMUX_PADS(PAD_DISP0_DAT21__GPIO5_IO15 | DIO_PAD_CFG),
IOMUX_PADS(PAD_DISP0_DAT22__GPIO5_IO16 | DIO_PAD_CFG),
IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
/* ETI_IRQ# */
IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 | DIO_PAD_CFG),
/* DIO_IRQ# */
IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
/* FIBER_SIGDET */
IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
};
static iomux_v3_cfg_t const gw5902_gpio_pads[] = {
/* MX6_LOCLED# */
IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
/* CAN1_STBY */
IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
/* CAN2_STBY */
IOMUX_PADS(PAD_SD3_CLK__GPIO7_IO03 | DIO_PAD_CFG),
/* UART1_EN# */
IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
/* PCI_RST# */
IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
/* 5V_UVLO */
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
/* ETI_IRQ# */
IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 | DIO_PAD_CFG),
/* DIO_IRQ# */
IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
/* USBOTG_PEN */
IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | DIO_PAD_CFG),
};
static iomux_v3_cfg_t const gw5903_gpio_pads[] = {
/* BKLT_12VEN */
IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
@@ -461,6 +500,49 @@ static iomux_v3_cfg_t const gw5904_gpio_pads[] = {
IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | DIO_PAD_CFG),
/* M2_RST# */
IOMUX_PADS(PAD_SD2_DAT2__GPIO1_IO13 | DIO_PAD_CFG),
/* RS232_EN# */
IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
};
static iomux_v3_cfg_t const gw5905_gpio_pads[] = {
/* EMMY_PDN# */
IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | DIO_PAD_CFG),
/* MX6_LOCLED# */
IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
/* MIPI_RST */
IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | DIO_PAD_CFG),
/* MIPI_PWDN */
IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | DIO_PAD_CFG),
/* USBEHCI_SEL */
IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
/* PCI_RST# */
IOMUX_PADS(PAD_GPIO_16__GPIO7_IO11 | DIO_PAD_CFG),
/* LVDS_BKLEN # */
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
/* PCIESKT_WDIS# */
IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | DIO_PAD_CFG),
/* SPK_SHDN# */
IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
/* LOCLED# */
IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
/* FLASH LED1 */
IOMUX_PADS(PAD_DISP0_DAT11__GPIO5_IO05 | DIO_PAD_CFG),
/* FLASH LED2 */
IOMUX_PADS(PAD_DISP0_DAT12__GPIO5_IO06 | DIO_PAD_CFG),
/* DECT_RST# */
IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14 | DIO_PAD_CFG),
/* USBH1_PEN (EHCI) */
IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
/* LVDS_PWM */
IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
/* CODEC_RST */
IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
/* GYRO_CONTROL/DATA_EN */
IOMUX_PADS(PAD_CSI0_DAT8__GPIO5_IO26 | DIO_PAD_CFG),
/* TOUCH_RST */
IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG),
/* TOUCH_IRQ */
IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
};
/* Digital I/O */
@@ -704,6 +786,60 @@ struct dio_cfg gw560x_dio[] = {
},
};
struct dio_cfg gw5901_dio[] = {
{
{ IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14) },
IMX_GPIO_NR(5, 14),
{ 0, 0 },
0
},
{
{ IOMUX_PADS(PAD_DISP0_DAT21__GPIO5_IO15) },
IMX_GPIO_NR(5, 15),
{ 0, 0 },
0
},
{
{ IOMUX_PADS(PAD_DISP0_DAT22__GPIO5_IO16) },
IMX_GPIO_NR(5, 16),
{ 0, 0 },
0
},
{
{ IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17) },
IMX_GPIO_NR(5, 17),
{ 0, 0 },
0
},
};
struct dio_cfg gw5902_dio[] = {
{
{ IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14) },
IMX_GPIO_NR(5, 14),
{ 0, 0 },
0
},
{
{ IOMUX_PADS(PAD_DISP0_DAT21__GPIO5_IO15) },
IMX_GPIO_NR(5, 15),
{ 0, 0 },
0
},
{
{ IOMUX_PADS(PAD_DISP0_DAT22__GPIO5_IO16) },
IMX_GPIO_NR(5, 16),
{ 0, 0 },
0
},
{
{ IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17) },
IMX_GPIO_NR(5, 17),
{ 0, 0 },
0
},
};
struct dio_cfg gw5903_dio[] = {
};
@@ -782,6 +918,33 @@ struct dio_cfg gw5904_dio[] = {
},
};
struct dio_cfg gw5906_dio[] = {
{
{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
IMX_GPIO_NR(1, 16),
{ 0, 0 },
0
},
{
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
IMX_GPIO_NR(1, 19),
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
2
},
{
{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
IMX_GPIO_NR(1, 17),
{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
3
},
{
{IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
IMX_GPIO_NR(1, 20),
{ 0, 0 },
0
},
};
/*
* Board Specific GPIO
*/
@@ -824,6 +987,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.vidin_en = IMX_GPIO_NR(5, 20),
.wdis = IMX_GPIO_NR(7, 12),
.otgpwr_en = IMX_GPIO_NR(3, 22),
.nand = true,
},
/* GW52xx */
@@ -849,6 +1013,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.otgpwr_en = IMX_GPIO_NR(3, 22),
.vsel_pin = IMX_GPIO_NR(6, 14),
.mmc_cd = IMX_GPIO_NR(7, 0),
.nand = true,
},
/* GW53xx */
@@ -873,6 +1038,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.otgpwr_en = IMX_GPIO_NR(3, 22),
.vsel_pin = IMX_GPIO_NR(6, 14),
.mmc_cd = IMX_GPIO_NR(7, 0),
.nand = true,
},
/* GW54xx */
@@ -899,6 +1065,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.otgpwr_en = IMX_GPIO_NR(3, 22),
.vsel_pin = IMX_GPIO_NR(6, 14),
.mmc_cd = IMX_GPIO_NR(7, 0),
.nand = true,
},
/* GW551x */
@@ -912,6 +1079,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
},
.pcie_rst = IMX_GPIO_NR(1, 0),
.wdis = IMX_GPIO_NR(7, 12),
.nand = true,
},
/* GW552x */
@@ -929,6 +1097,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.usb_sel = IMX_GPIO_NR(1, 7),
.wdis = IMX_GPIO_NR(7, 12),
.msata_en = GP_MSATA_SEL,
.nand = true,
},
/* GW553x */
@@ -947,6 +1116,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.otgpwr_en = IMX_GPIO_NR(3, 22),
.vsel_pin = IMX_GPIO_NR(6, 14),
.mmc_cd = IMX_GPIO_NR(7, 0),
.nand = true,
},
/* GW560x */
@@ -970,6 +1140,32 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.mmc_cd = IMX_GPIO_NR(7, 0),
},
/* GW5901 */
{
.gpio_pads = gw5901_gpio_pads,
.num_pads = ARRAY_SIZE(gw5901_gpio_pads)/2,
.dio_cfg = gw5901_dio,
.leds = {
IMX_GPIO_NR(4, 15),
},
.pcie_rst = IMX_GPIO_NR(1, 29),
.nand = true,
},
/* GW5902 */
{
.gpio_pads = gw5902_gpio_pads,
.num_pads = ARRAY_SIZE(gw5902_gpio_pads)/2,
.dio_cfg = gw5902_dio,
.leds = {
IMX_GPIO_NR(4, 15),
},
.pcie_rst = IMX_GPIO_NR(1, 0),
.rs232_en = GP_RS232_EN,
.otgpwr_en = IMX_GPIO_NR(3, 23),
.nand = true,
},
/* GW5903 */
{
.gpio_pads = gw5903_gpio_pads,
@@ -999,8 +1195,96 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.mezz_irq = IMX_GPIO_NR(2, 18),
.otgpwr_en = IMX_GPIO_NR(3, 22),
},
/* GW5905 */
{
.gpio_pads = gw5905_gpio_pads,
.num_pads = ARRAY_SIZE(gw5905_gpio_pads)/2,
.leds = {
IMX_GPIO_NR(6, 14),
},
.pcie_rst = IMX_GPIO_NR(7, 11),
.wdis = IMX_GPIO_NR(7, 13),
},
/* GW5906 */
{
.gpio_pads = gw552x_gpio_pads,
.num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
.dio_cfg = gw5906_dio,
.dio_num = ARRAY_SIZE(gw5906_dio),
.leds = {
IMX_GPIO_NR(4, 6),
IMX_GPIO_NR(4, 7),
IMX_GPIO_NR(4, 15),
},
.pcie_rst = IMX_GPIO_NR(1, 29),
.usb_sel = IMX_GPIO_NR(1, 7),
.wdis = IMX_GPIO_NR(7, 12),
.msata_en = GP_MSATA_SEL,
.nand = true,
},
/* GW5907 */
{
.gpio_pads = gw51xx_gpio_pads,
.num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
.dio_cfg = gw51xx_dio,
.dio_num = ARRAY_SIZE(gw51xx_dio),
.leds = {
IMX_GPIO_NR(4, 6),
IMX_GPIO_NR(4, 10),
},
.pcie_rst = IMX_GPIO_NR(1, 0),
.wdis = IMX_GPIO_NR(7, 12),
.nand = true,
},
/* GW5908 */
{
.gpio_pads = gw53xx_gpio_pads,
.num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
.dio_cfg = gw53xx_dio,
.dio_num = ARRAY_SIZE(gw53xx_dio),
.leds = {
IMX_GPIO_NR(4, 6),
IMX_GPIO_NR(4, 7),
IMX_GPIO_NR(4, 15),
},
.pcie_rst = IMX_GPIO_NR(1, 29),
.mezz_pwren = IMX_GPIO_NR(2, 19),
.mezz_irq = IMX_GPIO_NR(2, 18),
.gps_shdn = IMX_GPIO_NR(1, 27),
.vidin_en = IMX_GPIO_NR(3, 31),
.wdis = IMX_GPIO_NR(7, 12),
.msata_en = GP_MSATA_SEL,
.rs232_en = GP_RS232_EN,
},
/* GW5909 */
{
.gpio_pads = gw5904_gpio_pads,
.num_pads = ARRAY_SIZE(gw5904_gpio_pads)/2,
.dio_cfg = gw5904_dio,
.dio_num = ARRAY_SIZE(gw5904_dio),
.leds = {
IMX_GPIO_NR(4, 6),
IMX_GPIO_NR(4, 7),
IMX_GPIO_NR(4, 15),
},
.pcie_rst = IMX_GPIO_NR(1, 0),
.mezz_pwren = IMX_GPIO_NR(2, 19),
.mezz_irq = IMX_GPIO_NR(2, 18),
.otgpwr_en = IMX_GPIO_NR(3, 22),
},
};
#define SETUP_GPIO_OUTPUT(gpio, name, level) \
gpio_request(gpio, name); \
gpio_direction_output(gpio, level);
#define SETUP_GPIO_INPUT(gpio, name) \
gpio_request(gpio, name); \
gpio_direction_input(gpio);
void setup_iomux_gpio(int board, struct ventana_board_info *info)
{
int i;
@@ -1119,6 +1403,14 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info)
gpio_request(IMX_GPIO_NR(4, 26), "12p0_en");
gpio_direction_output(IMX_GPIO_NR(4, 26), 1);
break;
case GW5901:
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 2), "can_stby", 0);
break;
case GW5902:
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 2), "can1_stby", 0);
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(7, 3), "can2_stby", 0);
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(7, 12), "5P0V_EN", 1);
break;
case GW5903:
gpio_request(IMX_GPIO_NR(3, 31) , "usbh1-ehci_pwr");
gpio_direction_output(IMX_GPIO_NR(3, 31), 1);
@@ -1135,7 +1427,10 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info)
gpio_request(IMX_GPIO_NR(1, 7) , "bklt_12ven");
gpio_direction_output(IMX_GPIO_NR(1, 7), 1);
break;
case GW5909:
case GW5904:
gpio_request(IMX_GPIO_NR(4, 23), "rs485_en");
gpio_direction_output(IMX_GPIO_NR(4, 23), 0);
gpio_request(IMX_GPIO_NR(5, 11), "skt1_wdis#");
gpio_direction_output(IMX_GPIO_NR(5, 11), 1);
gpio_request(IMX_GPIO_NR(5, 12), "skt1_rst#");
@@ -1149,6 +1444,28 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info)
gpio_request(IMX_GPIO_NR(1, 13), "m2_rst#");
gpio_direction_output(IMX_GPIO_NR(1, 13), 1);
break;
case GW5905:
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 7), "usb_pcisel", 0);
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 9), "lvds_cabc", 1);
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 14), "mipi_pdwn", 1);
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 15), "mipi_rst#", 0);
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(2, 3), "emmy_pdwn#", 1);
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 5), "spk_shdn#", 0);
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 8), "touch_rst", 0);
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 6), "touch_irq", 0);
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 5), "flash_en1", 0);
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 6), "flash_en2", 0);
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 14), "dect_rst#", 1);
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 17), "codec_rst#", 0);
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 26), "imu_den", 1);
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(7, 12), "lvds_cabc", 0);
mdelay(100);
/*
* gauruntee touch controller comes out of reset with INT
* low for address
*/
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 8), "touch_rst", 1);
break;
}
}
@@ -1298,7 +1615,7 @@ void setup_pmic(void)
pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
break;
case GW5903:
/* mask PGOOD during SW1 transition */
/* mask PGOOD during SW3 transition */
pmic_reg_write(p, LTC3676_DVB3B,
0x1f | LTC3676_PGOOD_MASK);
/* set SW3 (VDD_ARM) */
@@ -1310,6 +1627,19 @@ void setup_pmic(void)
/* set SW4 (VDD_SOC) */
pmic_reg_write(p, LTC3676_DVB4A, 0x1f);
break;
case GW5905:
/* mask PGOOD during SW1 transition */
pmic_reg_write(p, LTC3676_DVB1B,
0x1f | LTC3676_PGOOD_MASK);
/* set SW1 (VDD_ARM) */
pmic_reg_write(p, LTC3676_DVB1A, 0x1f);
/* mask PGOOD during SW3 transition */
pmic_reg_write(p, LTC3676_DVB3B,
0x1f | LTC3676_PGOOD_MASK);
/* set SW3 (VDD_SOC) */
pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
break;
default:
/* mask PGOOD during SW1 transition */
pmic_reg_write(p, LTC3676_DVB1B,
@@ -1377,6 +1707,8 @@ int board_mmc_init(bd_t *bis)
usdhc_cfg[1].max_bus_width = 4;
return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
case GW5904:
case GW5905:
case GW5909:
/* usdhc3: 8bit eMMC */
SETUP_IOMUX_PADS(gw5904_emmc_pads);
usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
@@ -1405,6 +1737,8 @@ int board_mmc_getcd(struct mmc *mmc)
break;
case GW5903:
case GW5904:
case GW5905:
case GW5909:
/* emmc is always present */
if (cfg->esdhc_base == USDHC3_BASE_ADDR)
return 1;

3
board/gateworks/gw_ventana/common.h
View File

@@ -80,12 +80,13 @@ struct ventana {
int mmc_cd;
/* various features */
bool usd_vsel;
bool nand;
};
extern struct ventana gpio_cfg[GW_UNKNOWN];
/* configure i2c iomux */
void setup_ventana_i2c(void);
void setup_ventana_i2c(int);
/* configure uart iomux */
void setup_iomux_uart(void);
/* conifgure PMIC */

18
board/gateworks/gw_ventana/eeprom.c
View File

@@ -97,10 +97,24 @@ read_eeprom(int bus, struct ventana_board_info *info)
type = GW560x;
break;
case '9':
if (info->model[4] == '0' && info->model[5] == '3')
if (info->model[4] == '0' && info->model[5] == '1')
type = GW5901;
else if (info->model[4] == '0' && info->model[5] == '2')
type = GW5902;
else if (info->model[4] == '0' && info->model[5] == '3')
type = GW5903;
if (info->model[4] == '0' && info->model[5] == '4')
else if (info->model[4] == '0' && info->model[5] == '4')
type = GW5904;
else if (info->model[4] == '0' && info->model[5] == '5')
type = GW5905;
else if (info->model[4] == '0' && info->model[5] == '6')
type = GW5906;
else if (info->model[4] == '0' && info->model[5] == '7')
type = GW5907;
else if (info->model[4] == '0' && info->model[5] == '8')
type = GW5908;
else if (info->model[4] == '0' && info->model[5] == '9')
type = GW5909;
break;
}
return type;

6
board/gateworks/gw_ventana/gsc.c
View File

@@ -70,7 +70,7 @@ static void read_hwmon(const char *name, uint reg, uint size)
puts("fRD\n");
} else {
ui = buf[0] | (buf[1]<<8) | (buf[2]<<16);
if (reg == GSC_HWMON_TEMP && ui > 0x8000)
if (size == 2 && ui > 0x8000)
ui -= 0xffff;
if (ui == 0xffffff)
puts("invalid\n");
@@ -140,6 +140,10 @@ int gsc_info(int verbose)
read_hwmon("VDD_IO4", GSC_HWMON_VDD_IO4, 3);
read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3);
break;
case '9': /* GW590x */
read_hwmon("AMONBMON", GSC_HWMON_VDD_IO3, 3);
read_hwmon("BAT_VOLT", GSC_HWMON_VDD_EXT, 3);
read_hwmon("BAT_TEMP", GSC_HWMON_VDD_IO4, 2);
}
return 0;
}

3
board/gateworks/gw_ventana/gsc.h
View File

@@ -48,9 +48,10 @@ enum {
GSC_HWMON_VBATT = 0x08,
GSC_HWMON_VDD_5P0 = 0x0b,
GSC_HWMON_VDD_CORE = 0x0e,
GSC_HWMON_VDD_SOC = 0x11,
GSC_HWMON_VDD_HIGH = 0x14,
GSC_HWMON_VDD_DDR = 0x17,
GSC_HWMON_VDD_SOC = 0x11,
GSC_HWMON_VDD_EXT = 0x1a,
GSC_HWMON_VDD_1P8 = 0x1d,
GSC_HWMON_VDD_IO2 = 0x20,
GSC_HWMON_VDD_2P5 = 0x23,

151
board/gateworks/gw_ventana/gw_ventana.c
View File

@@ -155,6 +155,7 @@ int board_ehci_hcd_init(int port)
switch (board_type) {
case GW53xx:
case GW552x:
case GW5906:
gpio = (IMX_GPIO_NR(1, 9));
break;
case GW54proto:
@@ -267,11 +268,11 @@ int mv88e61xx_hw_reset(struct phy_device *phydev)
phydev->speed = SPEED_1000;
phydev->duplex = DUPLEX_FULL;
/* LED configuration: 7:4-green (8=Activity) 3:0 amber (9=10Link) */
bus->write(bus, 0x10, 0, 0x16, 0x8089);
bus->write(bus, 0x11, 0, 0x16, 0x8089);
bus->write(bus, 0x12, 0, 0x16, 0x8089);
bus->write(bus, 0x13, 0, 0x16, 0x8089);
/* LED configuration: 7:4-green (8=Activity) 3:0 amber (8=Link) */
bus->write(bus, 0x10, 0, 0x16, 0x8088);
bus->write(bus, 0x11, 0, 0x16, 0x8088);
bus->write(bus, 0x12, 0, 0x16, 0x8088);
bus->write(bus, 0x13, 0, 0x16, 0x8088);
return 0;
}
@@ -384,8 +385,8 @@ struct display_info_t const displays[] = {{
.vmode = FB_VMODE_NONINTERLACED
} }, {
/* DLC700JMG-T-4 */
.bus = 0,
.addr = 0,
.bus = 2,
.addr = 0x38,
.detect = NULL,
.enable = enable_lvds,
.pixfmt = IPU_PIX_FMT_LVDS666,
@@ -405,8 +406,8 @@ struct display_info_t const displays[] = {{
.vmode = FB_VMODE_NONINTERLACED
} }, {
/* DLC800FIG-T-3 */
.bus = 0,
.addr = 0,
.bus = 2,
.addr = 0x14,
.detect = NULL,
.enable = enable_lvds,
.pixfmt = IPU_PIX_FMT_LVDS666,
@@ -424,7 +425,29 @@ struct display_info_t const displays[] = {{
.vsync_len = 10,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
} } };
} }, {
.bus = 2,
.addr = 0x5d,
.detect = detect_i2c,
.enable = enable_lvds,
.pixfmt = IPU_PIX_FMT_LVDS666,
.mode = {
.name = "Z101WX01",
.refresh = 60,
.xres = 1280,
.yres = 800,
.pixclock = 15385, /* 64MHz */
.left_margin = 220,
.right_margin = 40,
.upper_margin = 21,
.lower_margin = 7,
.hsync_len = 60,
.vsync_len = 10,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
}
},
};
size_t display_count = ARRAY_SIZE(displays);
static void setup_display(void)
@@ -625,19 +648,23 @@ int board_init(void)
/* address of linux boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
/* read Gateworks EEPROM into global struct (used later) */
setup_ventana_i2c(0);
board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
#ifdef CONFIG_CMD_NAND
setup_gpmi_nand();
if (gpio_cfg[board_type].nand)
setup_gpmi_nand();
#endif
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
setup_ventana_i2c();
setup_ventana_i2c(1);
setup_ventana_i2c(2);
#ifdef CONFIG_SATA
setup_sata();
#endif
/* read Gateworks EEPROM into global struct (used later) */
board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
setup_iomux_gpio(board_type, &ventana_info);
@@ -707,7 +734,7 @@ static const struct boot_mode board_boot_modes[] = {
/* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
{ "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
{ "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */
{ "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/GW5904 */
{ "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/4/5 */
{ NULL, 0 },
};
#endif
@@ -852,34 +879,12 @@ static int ft_sethdmiinfmt(void *blob, char *mode)
return 0;
}
/* enable a property of a node if the node is found */
static inline void ft_enable_path(void *blob, const char *path)
{
int i = fdt_path_offset(blob, path);
if (i >= 0) {
debug("enabling %s\n", path);
fdt_status_okay(blob, i);
}
}
/* remove a property of a node if the node is found */
static inline void ft_delprop_path(void *blob, const char *path,
const char *name)
{
int i = fdt_path_offset(blob, path);
if (i) {
debug("removing %s/%s\n", path, name);
fdt_delprop(blob, i, name);
}
}
#if defined(CONFIG_CMD_PCI)
#define PCI_ID(x) ( \
(PCI_BUS(x->devfn)<<16)| \
(PCI_DEV(x->devfn)<<11)| \
(PCI_FUNC(x->devfn)<<8) \
)
#define PCIE_PATH "/soc/pcie@0x01000000"
int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
{
uint32_t reg[5];
@@ -912,7 +917,7 @@ int fdt_add_pci_path(void *blob, struct pci_dev *dev)
int k, np;
/* build list of parents */
np = fdt_path_offset(blob, PCIE_PATH);
np = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
if (np < 0)
return np;
@@ -949,7 +954,7 @@ int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
int i;
/* build irq-map based on host controllers map */
host = fdt_path_offset(blob, PCIE_PATH);
host = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
if (host < 0) {
printf(" %s failed: missing host\n", __func__);
return host;
@@ -1091,10 +1096,14 @@ void ft_board_pci_fixup(void *blob, bd_t *bd)
}
#endif /* if defined(CONFIG_CMD_PCI) */
void ft_board_wdog_fixup(void *blob, const char *path)
void ft_board_wdog_fixup(void *blob, phys_addr_t addr)
{
ft_delprop_path(blob, path, "ext-reset-output");
ft_delprop_path(blob, path, "fsl,ext-reset-output");
int off = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", addr);
if (off) {
fdt_delprop(blob, off, "ext-reset-output");
fdt_delprop(blob, off, "fsl,ext-reset-output");
}
}
/*
@@ -1106,10 +1115,11 @@ void ft_board_wdog_fixup(void *blob, const char *path)
* - board (full model from EEPROM)
* - peripherals removed from DTB if not loaded on board (per EEPROM config)
*/
#define UART1_PATH "/soc/aips-bus@02100000/serial@021ec000"
#define WDOG1_PATH "/soc/aips-bus@02000000/wdog@020bc000"
#define WDOG2_PATH "/soc/aips-bus@02000000/wdog@020c0000"
#define GPIO3_PATH "/soc/aips-bus@02000000/gpio@020a4000"
#define WDOG1_ADDR 0x20bc000
#define WDOG2_ADDR 0x20c0000
#define GPIO3_ADDR 0x20a4000
#define USDHC3_ADDR 0x2198000
#define PWM0_ADDR 0x2080000
int ft_board_setup(void *blob, bd_t *bd)
{
struct ventana_board_info *info = &ventana_info;
@@ -1172,14 +1182,15 @@ int ft_board_setup(void *blob, bd_t *bd)
* errata causing wdog timer to be unreliable.
*/
if (rev >= 'A' && rev < 'C') {
i = fdt_path_offset(blob, WDOG1_PATH);
i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt",
WDOG1_ADDR);
if (i)
fdt_status_disabled(blob, i);
}
/* GW51xx-E adds WDOG1_B external reset */
if (rev < 'E')
ft_board_wdog_fixup(blob, WDOG1_PATH);
ft_board_wdog_fixup(blob, WDOG1_ADDR);
break;
case GW52xx:
@@ -1195,7 +1206,8 @@ int ft_board_setup(void *blob, bd_t *bd)
"reset-gpio", NULL);
if (range) {
i = fdt_path_offset(blob, GPIO3_PATH);
i = fdt_node_offset_by_compat_reg(blob,
"fsl,imx6q-gpio", GPIO3_ADDR);
if (i)
handle = fdt_get_phandle(blob, i);
if (handle) {
@@ -1210,18 +1222,19 @@ int ft_board_setup(void *blob, bd_t *bd)
gpio_cfg[board_type].usd_vsel = 0;
/* GW522x-B adds WDOG1_B external reset */
ft_board_wdog_fixup(blob, WDOG1_PATH);
if (rev < 'B')
ft_board_wdog_fixup(blob, WDOG1_ADDR);
}
/* GW520x-E adds WDOG1_B external reset */
else if (info->model[4] == '0' && rev < 'E')
ft_board_wdog_fixup(blob, WDOG1_PATH);
ft_board_wdog_fixup(blob, WDOG1_ADDR);
break;
case GW53xx:
/* GW53xx-E adds WDOG1_B external reset */
if (rev < 'E')
ft_board_wdog_fixup(blob, WDOG1_PATH);
ft_board_wdog_fixup(blob, WDOG1_ADDR);
break;
case GW54xx:
@@ -1229,13 +1242,12 @@ int ft_board_setup(void *blob, bd_t *bd)
* disable serial2 node for GW54xx for compatibility with older
* 3.10.x kernel that improperly had this node enabled in the DT
*/
i = fdt_path_offset(blob, UART1_PATH);
if (i)
fdt_del_node(blob, i);
fdt_set_status_by_alias(blob, "serial2", FDT_STATUS_DISABLED,
0);
/* GW54xx-E adds WDOG2_B external reset */
if (rev < 'E')
ft_board_wdog_fixup(blob, WDOG2_PATH);
ft_board_wdog_fixup(blob, WDOG2_ADDR);
break;
case GW551x:
@@ -1284,7 +1296,13 @@ int ft_board_setup(void *blob, bd_t *bd)
/* GW551x-C adds WDOG1_B external reset */
if (rev < 'C')
ft_board_wdog_fixup(blob, WDOG1_PATH);
ft_board_wdog_fixup(blob, WDOG1_ADDR);
break;
case GW5901:
case GW5902:
/* GW5901/GW5901 revB adds WDOG1_B as an external reset */
if (rev < 'B')
ft_board_wdog_fixup(blob, WDOG1_ADDR);
break;
}
@@ -1298,20 +1316,27 @@ int ft_board_setup(void *blob, bd_t *bd)
continue;
if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
{
char path[48];
sprintf(path, "/soc/aips-bus@02000000/pwm@%08x",
0x02080000 + (0x4000 * (cfg->pwm_param - 1)));
phys_addr_t addr;
int off;
printf(" Enabling pwm%d for DIO%d\n",
cfg->pwm_param, i);
ft_enable_path(blob, path);
addr = PWM0_ADDR + (0x4000 * (cfg->pwm_param - 1));
off = fdt_node_offset_by_compat_reg(blob,
"fsl,imx6q-pwm",
addr);
if (off)
fdt_status_okay(blob, off);
}
}
/* remove no-1-8-v if UHS-I support is present */
if (gpio_cfg[board_type].usd_vsel) {
debug("Enabling UHS-I support\n");
ft_delprop_path(blob, "/soc/aips-bus@02100000/usdhc@02198000",
"no-1-8-v");
i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-usdhc",
USDHC3_ADDR);
if (i)
fdt_delprop(blob, i, "no-1-8-v");
}
#if defined(CONFIG_CMD_PCI)

97
board/gateworks/gw_ventana/gw_ventana_spl.c
View File

@@ -217,6 +217,46 @@ static struct mx6_mmdc_calibration mx6sdl_64x16_mmdc_calib = {
.p0_mpwrdlctl = 0x33382C31,
};
/* TODO: update with calibrated values */
static struct mx6_mmdc_calibration mx6dq_64x64_mmdc_calib = {
/* write leveling calibration determine */
.p0_mpwldectrl0 = 0x00190017,
.p0_mpwldectrl1 = 0x00140026,
.p1_mpwldectrl0 = 0x0021001C,
.p1_mpwldectrl1 = 0x0011001D,
/* Read DQS Gating calibration */
.p0_mpdgctrl0 = 0x43380347,
.p0_mpdgctrl1 = 0x433C034D,
.p1_mpdgctrl0 = 0x032C0324,
.p1_mpdgctrl1 = 0x03310232,
/* Read Calibration: DQS delay relative to DQ read access */
.p0_mprddlctl = 0x3C313539,
.p1_mprddlctl = 0x37343141,
/* Write Calibration: DQ/DM delay relative to DQS write access */
.p0_mpwrdlctl = 0x36393C39,
.p1_mpwrdlctl = 0x42344438,
};
/* TODO: update with calibrated values */
static struct mx6_mmdc_calibration mx6sdl_64x64_mmdc_calib = {
/* write leveling calibration determine */
.p0_mpwldectrl0 = 0x003C003C,
.p0_mpwldectrl1 = 0x001F002A,
.p1_mpwldectrl0 = 0x00330038,
.p1_mpwldectrl1 = 0x0022003F,
/* Read DQS Gating calibration */
.p0_mpdgctrl0 = 0x42410244,
.p0_mpdgctrl1 = 0x4234023A,
.p1_mpdgctrl0 = 0x022D022D,
.p1_mpdgctrl1 = 0x021C0228,
/* Read Calibration: DQS delay relative to DQ read access */
.p0_mprddlctl = 0x484A4C4B,
.p1_mprddlctl = 0x4B4D4E4B,
/* Write Calibration: DQ/DM delay relative to DQS write access */
.p0_mpwrdlctl = 0x33342B32,
.p1_mpwrdlctl = 0x3933332B,
};
static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = {
/* write leveling calibration determine */
.p0_mpwldectrl0 = 0x001B0016,
@@ -390,6 +430,25 @@ static struct mx6_mmdc_calibration mx6sdl_256x64x2_mmdc_calib = {
.p1_mpwrdlctl = 0x3F36363F,
};
static struct mx6_mmdc_calibration mx6sdl_128x64x2_mmdc_calib = {
/* write leveling calibration determine */
.p0_mpwldectrl0 = 0x001F003F,
.p0_mpwldectrl1 = 0x001F001F,
.p1_mpwldectrl0 = 0x001F004E,
.p1_mpwldectrl1 = 0x0059001F,
/* Read DQS Gating calibration */
.p0_mpdgctrl0 = 0x42220225,
.p0_mpdgctrl1 = 0x0213021F,
.p1_mpdgctrl0 = 0x022C0242,
.p1_mpdgctrl1 = 0x022C0244,
/* Read Calibration: DQS delay relative to DQ read access */
.p0_mprddlctl = 0x474A4C4A,
.p1_mprddlctl = 0x48494C45,
/* Write Calibration: DQ/DM delay relative to DQS write access */
.p0_mpwrdlctl = 0x3F3F3F36,
.p1_mpwrdlctl = 0x3F36363F,
};
static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = {
/* write leveling calibration determine */
.p0_mpwldectrl0 = 0x002A0025,
@@ -511,6 +570,10 @@ static void spl_dram_init(int width, int size_mb, int board_model)
} else if (width == 64 && size_mb == 512) {
mem = &mt41k64m16jt_125;
debug("1gB density\n");
if (is_cpu_type(MXC_CPU_MX6Q))
calib = &mx6dq_64x64_mmdc_calib;
else
calib = &mx6sdl_64x64_mmdc_calib;
} else if (width == 64 && size_mb == 1024) {
mem = &mt41k128m16jt_125;
if (is_cpu_type(MXC_CPU_MX6Q))
@@ -519,18 +582,33 @@ static void spl_dram_init(int width, int size_mb, int board_model)
calib = &mx6sdl_128x64_mmdc_calib;
debug("2gB density\n");
} else if (width == 64 && size_mb == 2048) {
mem = &mt41k256m16ha_125;
if (is_cpu_type(MXC_CPU_MX6Q))
calib = &mx6dq_256x64_mmdc_calib;
else
calib = &mx6sdl_256x64_mmdc_calib;
debug("4gB density\n");
switch(board_model) {
case GW5905:
/* 8xMT41K128M16 (2GiB) fly-by mirrored 2-chipsels */
mem = &mt41k128m16jt_125;
debug("2gB density - 2 chipsel\n");
if (!is_cpu_type(MXC_CPU_MX6Q)) {
calib = &mx6sdl_128x64x2_mmdc_calib;
sysinfo.ncs = 2;
sysinfo.cs_density = 10; /* CS0_END=39 */
sysinfo.cs1_mirror = 1; /* mirror enabled */
}
break;
default:
mem = &mt41k256m16ha_125;
if (is_cpu_type(MXC_CPU_MX6Q))
calib = &mx6dq_256x64_mmdc_calib;
else
calib = &mx6sdl_256x64_mmdc_calib;
debug("4gB density\n");
break;
}
} else if (width == 64 && size_mb == 4096) {
switch(board_model) {
case GW5903:
/* 8xMT41K256M16 (4GiB) fly-by mirrored 2-chipsels */
mem = &mt41k256m16ha_125;
debug("4gB density\n");
debug("4gB density - 2 chipsel\n");
if (!is_cpu_type(MXC_CPU_MX6Q)) {
calib = &mx6sdl_256x64x2_mmdc_calib;
sysinfo.ncs = 2;
@@ -599,9 +677,10 @@ void board_init_f(ulong dummy)
/* setup AXI */
gpr_init();
/* iomux and setup of i2c */
/* iomux and setup of uart/i2c */
setup_iomux_uart();
setup_ventana_i2c();
setup_ventana_i2c(0);
setup_ventana_i2c(1);
/* setup GP timer */
timer_init();

7
board/gateworks/gw_ventana/ventana_eeprom.h
View File

@@ -112,8 +112,15 @@ enum {
GW552x,
GW553x,
GW560x,
GW5901,
GW5902,
GW5903,
GW5904,
GW5905,
GW5906,
GW5907,
GW5908,
GW5909,
GW_UNKNOWN,
GW_BADCRC,
};

79
board/logicpd/imx6/imx6logic.c
View File

@@ -60,57 +60,6 @@ static iomux_v3_cfg_t const uart3_pads[] = {
MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
};
#ifndef CONFIG_SPL_BUILD
static void fixup_enet_clock(void)
{
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
struct gpio_desc nint;
struct gpio_desc reset;
int ret;
/* Set Ref Clock to 50 MHz */
enable_fec_anatop_clock(0, ENET_50MHZ);
/* Set GPIO_16 as ENET_REF_CLK_OUT */
setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
/* Request GPIO Pins to reset Ethernet with new clock */
ret = dm_gpio_lookup_name("GPIO4_7", &nint);
if (ret) {
printf("Unable to lookup GPIO4_7\n");
return;
}
ret = dm_gpio_request(&nint, "eth0_nInt");
if (ret) {
printf("Unable to request eth0_nInt\n");
return;
}
/* Ensure nINT is input or PHY won't startup */
dm_gpio_set_dir_flags(&nint, GPIOD_IS_IN);
ret = dm_gpio_lookup_name("GPIO4_9", &reset);
if (ret) {
printf("Unable to lookup GPIO4_9\n");
return;
}
ret = dm_gpio_request(&reset, "eth0_reset");
if (ret) {
printf("Unable to request eth0_reset\n");
return;
}
/* Reset LAN8710A PHY */
dm_gpio_set_dir_flags(&reset, GPIOD_IS_OUT);
dm_gpio_set_value(&reset, 0);
udelay(150);
dm_gpio_set_value(&reset, 1);
mdelay(50);
}
#endif
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
@@ -141,8 +90,33 @@ static void setup_nand_pins(void)
imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
}
static int ar8031_phy_fixup(struct phy_device *phydev)
{
unsigned short val;
/* To enable AR8031 output a 125MHz clk from CLK_25M */
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
val &= 0xffe3;
val |= 0x18;
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
/* introduce tx clock delay */
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
val |= 0x0100;
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
ar8031_phy_fixup(phydev);
if (phydev->drv->config)
phydev->drv->config(phydev);
@@ -160,9 +134,6 @@ int overwrite_console(void)
int board_early_init_f(void)
{
#ifndef CONFIG_SPL_BUILD
fixup_enet_clock();
#endif
setup_iomux_uart();
setup_nand_pins();
return 0;