video: seps525: Add seps525 SPI driver
Add support for the WiseChip Semiconductor Inc. (UG-6028GDEBF02) display using the SEPS525 (Syncoam) LCD Controller. Syncoam Seps525 PM-Oled is RGB 160x128 display. This driver has been tested through zynq-spi driver. ZynqMP> load mmc 1 100000 rainbow.bmp 61562 bytes read in 20 ms (2.9 MiB/s) ZynqMP> bmp info 100000 Image size : 160 x 128 Bits per pixel: 24 Compression : 0 ZynqMP> bmp display 100000 ZynqMP> setenv stdout vidconsole Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Michal Simek
parent
1ac1a04b9e
commit
b66d7af41f
@ -590,6 +590,7 @@ F: drivers/spi/zynq_qspi.c
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F: drivers/spi/zynq_spi.c
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F: drivers/timer/cadence-ttc.c
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F: drivers/usb/host/ehci-zynq.c
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F: drivers/video/seps525.c
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F: drivers/watchdog/cdns_wdt.c
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F: include/zynqmppl.h
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F: include/zynqmp_firmware.h
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@ -652,6 +652,13 @@ config VIDEO_NX
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HDMI. This option enables this support which can be used on devices
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which have an eDP display connected.
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config VIDEO_SEPS525
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bool "Enable video support for Seps525"
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depends on DM_VIDEO
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help
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Enable support for the Syncoam PM-OLED display driver (RGB 160x128).
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Currently driver is supporting only SPI interface.
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source "drivers/video/nexell/Kconfig"
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config VIDEO
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@ -70,6 +70,7 @@ obj-$(CONFIG_VIDEO_SIMPLE) += simplefb.o
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obj-$(CONFIG_VIDEO_TEGRA20) += tegra.o
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obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
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obj-$(CONFIG_VIDEO_VESA) += vesa.o
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obj-$(CONFIG_VIDEO_SEPS525) += seps525.o
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obj-y += bridge/
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obj-y += sunxi/
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327
drivers/video/seps525.c
Normal file
327
drivers/video/seps525.c
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@ -0,0 +1,327 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* FB driver for the WiseChip Semiconductor Inc. (UG-6028GDEBF02) display
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* using the SEPS525 (Syncoam) LCD Controller
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*
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* Copyright (C) 2020 Xilinx Inc.
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*/
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#include <common.h>
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#include <command.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <errno.h>
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#include <spi.h>
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#include <video.h>
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#include <asm/gpio.h>
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#include <dm/device_compat.h>
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#include <linux/delay.h>
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#define WIDTH 160
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#define HEIGHT 128
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#define SEPS525_INDEX 0x00
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#define SEPS525_STATUS_RD 0x01
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#define SEPS525_OSC_CTL 0x02
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#define SEPS525_IREF 0x80
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#define SEPS525_CLOCK_DIV 0x03
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#define SEPS525_REDUCE_CURRENT 0x04
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#define SEPS525_SOFT_RST 0x05
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#define SEPS525_DISP_ONOFF 0x06
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#define SEPS525_PRECHARGE_TIME_R 0x08
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#define SEPS525_PRECHARGE_TIME_G 0x09
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#define SEPS525_PRECHARGE_TIME_B 0x0A
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#define SEPS525_PRECHARGE_CURRENT_R 0x0B
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#define SEPS525_PRECHARGE_CURRENT_G 0x0C
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#define SEPS525_PRECHARGE_CURRENT_B 0x0D
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#define SEPS525_DRIVING_CURRENT_R 0x10
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#define SEPS525_DRIVING_CURRENT_G 0x11
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#define SEPS525_DRIVING_CURRENT_B 0x12
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#define SEPS525_DISPLAYMODE_SET 0x13
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#define SEPS525_RGBIF 0x14
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#define SEPS525_RGB_POL 0x15
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#define SEPS525_MEMORY_WRITEMODE 0x16
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#define SEPS525_MX1_ADDR 0x17
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#define SEPS525_MX2_ADDR 0x18
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#define SEPS525_MY1_ADDR 0x19
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#define SEPS525_MY2_ADDR 0x1A
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#define SEPS525_MEMORY_ACCESS_POINTER_X 0x20
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#define SEPS525_MEMORY_ACCESS_POINTER_Y 0x21
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#define SEPS525_DDRAM_DATA_ACCESS_PORT 0x22
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#define SEPS525_GRAY_SCALE_TABLE_INDEX 0x50
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#define SEPS525_GRAY_SCALE_TABLE_DATA 0x51
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#define SEPS525_DUTY 0x28
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#define SEPS525_DSL 0x29
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#define SEPS525_D1_DDRAM_FAC 0x2E
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#define SEPS525_D1_DDRAM_FAR 0x2F
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#define SEPS525_D2_DDRAM_SAC 0x31
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#define SEPS525_D2_DDRAM_SAR 0x32
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#define SEPS525_SCR1_FX1 0x33
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#define SEPS525_SCR1_FX2 0x34
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#define SEPS525_SCR1_FY1 0x35
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#define SEPS525_SCR1_FY2 0x36
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#define SEPS525_SCR2_SX1 0x37
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#define SEPS525_SCR2_SX2 0x38
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#define SEPS525_SCR2_SY1 0x39
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#define SEPS525_SCR2_SY2 0x3A
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#define SEPS525_SCREEN_SAVER_CONTEROL 0x3B
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#define SEPS525_SS_SLEEP_TIMER 0x3C
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#define SEPS525_SCREEN_SAVER_MODE 0x3D
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#define SEPS525_SS_SCR1_FU 0x3E
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#define SEPS525_SS_SCR1_MXY 0x3F
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#define SEPS525_SS_SCR2_FU 0x40
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#define SEPS525_SS_SCR2_MXY 0x41
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#define SEPS525_MOVING_DIRECTION 0x42
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#define SEPS525_SS_SCR2_SX1 0x47
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#define SEPS525_SS_SCR2_SX2 0x48
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#define SEPS525_SS_SCR2_SY1 0x49
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#define SEPS525_SS_SCR2_SY2 0x4A
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/* SEPS525_DISPLAYMODE_SET */
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#define MODE_SWAP_BGR BIT(7)
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#define MODE_SM BIT(6)
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#define MODE_RD BIT(5)
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#define MODE_CD BIT(4)
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/**
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* struct seps525_priv - Private structure
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* @reset_gpio: Reset gpio pin
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* @dc_gpio: Data/command control gpio pin
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* @dev: Device uclass for video_ops
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*/
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struct seps525_priv {
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struct gpio_desc reset_gpio;
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struct gpio_desc dc_gpio;
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struct udevice *dev;
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};
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static int seps525_spi_write_cmd(struct udevice *dev, u32 reg)
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{
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struct seps525_priv *priv = dev_get_priv(dev);
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u8 buf8 = reg;
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int ret;
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ret = dm_gpio_set_value(&priv->dc_gpio, 0);
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if (ret) {
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dev_dbg(dev, "Failed to handle dc\n");
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return ret;
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}
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ret = dm_spi_xfer(dev, 8, &buf8, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
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if (ret)
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dev_dbg(dev, "Failed to write command\n");
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return ret;
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}
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static int seps525_spi_write_data(struct udevice *dev, u32 val)
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{
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struct seps525_priv *priv = dev_get_priv(dev);
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u8 buf8 = val;
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int ret;
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ret = dm_gpio_set_value(&priv->dc_gpio, 1);
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if (ret) {
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dev_dbg(dev, "Failed to handle dc\n");
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return ret;
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}
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ret = dm_spi_xfer(dev, 8, &buf8, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
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if (ret)
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dev_dbg(dev, "Failed to write data\n");
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return ret;
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}
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static void seps525_spi_write(struct udevice *dev, u32 reg, u32 val)
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{
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(void)seps525_spi_write_cmd(dev, reg);
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(void)seps525_spi_write_data(dev, val);
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}
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static int seps525_display_init(struct udevice *dev)
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{
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/* Disable Oscillator Power Down */
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seps525_spi_write(dev, SEPS525_REDUCE_CURRENT, 0x03);
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mdelay(5);
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/* Set Normal Driving Current */
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seps525_spi_write(dev, SEPS525_REDUCE_CURRENT, 0x00);
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mdelay(5);
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seps525_spi_write(dev, SEPS525_SCREEN_SAVER_CONTEROL, 0x00);
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/* Set EXPORT1 Pin at Internal Clock */
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seps525_spi_write(dev, SEPS525_OSC_CTL, 0x01);
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/* Set Clock as 120 Frames/Sec */
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seps525_spi_write(dev, SEPS525_CLOCK_DIV, 0x90);
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/* Set Reference Voltage Controlled by External Resister */
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seps525_spi_write(dev, SEPS525_IREF, 0x01);
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/* precharge time R G B */
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seps525_spi_write(dev, SEPS525_PRECHARGE_TIME_R, 0x04);
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seps525_spi_write(dev, SEPS525_PRECHARGE_TIME_G, 0x05);
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seps525_spi_write(dev, SEPS525_PRECHARGE_TIME_B, 0x05);
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/* precharge current R G B (uA) */
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seps525_spi_write(dev, SEPS525_PRECHARGE_CURRENT_R, 0x9D);
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seps525_spi_write(dev, SEPS525_PRECHARGE_CURRENT_G, 0x8C);
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seps525_spi_write(dev, SEPS525_PRECHARGE_CURRENT_B, 0x57);
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/* driving current R G B (uA) */
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seps525_spi_write(dev, SEPS525_DRIVING_CURRENT_R, 0x56);
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seps525_spi_write(dev, SEPS525_DRIVING_CURRENT_G, 0x4D);
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seps525_spi_write(dev, SEPS525_DRIVING_CURRENT_B, 0x46);
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/* Set Color Sequence */
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seps525_spi_write(dev, SEPS525_DISPLAYMODE_SET, 0x00);
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/* Set MCU Interface Mode */
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seps525_spi_write(dev, SEPS525_RGBIF, 0x01);
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/* Set Memory Write Mode */
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seps525_spi_write(dev, SEPS525_MEMORY_WRITEMODE, 0x66);
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/* 1/128 Duty (0x0F~0x7F) */
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seps525_spi_write(dev, SEPS525_DUTY, 0x7F);
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/* Set Mapping RAM Display Start Line (0x00~0x7F) */
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seps525_spi_write(dev, SEPS525_DSL, 0x00);
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/* Display On (0x00/0x01) */
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seps525_spi_write(dev, SEPS525_DISP_ONOFF, 0x01);
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/* Set All Internal Register Value as Normal Mode */
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seps525_spi_write(dev, SEPS525_SOFT_RST, 0x00);
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/* Set RGB Interface Polarity as Active Low */
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seps525_spi_write(dev, SEPS525_RGB_POL, 0x00);
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/* Enable access for data */
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(void)seps525_spi_write_cmd(dev, SEPS525_DDRAM_DATA_ACCESS_PORT);
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return 0;
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}
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static int seps525_spi_startup(struct udevice *dev)
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{
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struct seps525_priv *priv = dev_get_priv(dev);
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int ret;
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ret = dm_gpio_set_value(&priv->reset_gpio, 1);
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if (ret)
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return ret;
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ret = dm_gpio_set_value(&priv->reset_gpio, 0);
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if (ret)
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return ret;
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ret = dm_spi_claim_bus(dev);
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if (ret) {
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dev_err(dev, "Failed to claim SPI bus: %d\n", ret);
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return ret;
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}
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ret = seps525_display_init(dev);
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if (ret)
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return ret;
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dm_spi_release_bus(dev);
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return 0;
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}
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static int seps525_sync(struct udevice *vid)
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{
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struct video_priv *uc_priv = dev_get_uclass_priv(vid);
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struct seps525_priv *priv = dev_get_priv(vid);
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struct udevice *dev = priv->dev;
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int i, ret;
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u8 data1, data2;
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u8 *start = uc_priv->fb;
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ret = dm_spi_claim_bus(dev);
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if (ret) {
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dev_err(dev, "Failed to claim SPI bus: %d\n", ret);
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return ret;
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}
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/* start position X,Y */
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seps525_spi_write(dev, SEPS525_MEMORY_ACCESS_POINTER_X, 0);
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seps525_spi_write(dev, SEPS525_MEMORY_ACCESS_POINTER_Y, 0);
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/* Enable access for data */
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(void)seps525_spi_write_cmd(dev, SEPS525_DDRAM_DATA_ACCESS_PORT);
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for (i = 0; i < (uc_priv->xsize * uc_priv->ysize); i++) {
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data2 = *start++;
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data1 = *start++;
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(void)seps525_spi_write_data(dev, data1);
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(void)seps525_spi_write_data(dev, data2);
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}
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dm_spi_release_bus(dev);
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return 0;
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}
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static int seps525_probe(struct udevice *dev)
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{
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struct video_priv *uc_priv = dev_get_uclass_priv(dev);
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struct seps525_priv *priv = dev_get_priv(dev);
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u32 buswidth;
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int ret;
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buswidth = dev_read_u32_default(dev, "buswidth", 0);
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if (buswidth != 8) {
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dev_err(dev, "Only 8bit buswidth is supported now");
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return -EINVAL;
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}
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ret = gpio_request_by_name(dev, "reset-gpios", 0,
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&priv->reset_gpio, GPIOD_IS_OUT);
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if (ret) {
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dev_err(dev, "missing reset GPIO\n");
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return ret;
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}
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ret = gpio_request_by_name(dev, "dc-gpios", 0,
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&priv->dc_gpio, GPIOD_IS_OUT);
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if (ret) {
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dev_err(dev, "missing dc GPIO\n");
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return ret;
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}
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uc_priv->bpix = VIDEO_BPP16;
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uc_priv->xsize = WIDTH;
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uc_priv->ysize = HEIGHT;
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uc_priv->rot = 0;
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priv->dev = dev;
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ret = seps525_spi_startup(dev);
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if (ret)
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return ret;
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return 0;
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}
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static int seps525_bind(struct udevice *dev)
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{
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struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
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plat->size = WIDTH * HEIGHT * 16;
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return 0;
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}
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static const struct video_ops seps525_ops = {
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.video_sync = seps525_sync,
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};
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static const struct udevice_id seps525_ids[] = {
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{ .compatible = "syncoam,seps525" },
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{ }
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};
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U_BOOT_DRIVER(seps525_video) = {
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.name = "seps525_video",
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.id = UCLASS_VIDEO,
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.of_match = seps525_ids,
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.ops = &seps525_ops,
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.platdata_auto_alloc_size = sizeof(struct video_uc_platdata),
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.bind = seps525_bind,
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.probe = seps525_probe,
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.priv_auto_alloc_size = sizeof(struct seps525_priv),
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};
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